Commit Graph

463 Commits

Author SHA1 Message Date
Eshan dhawan 55a6e49a08 Removed Soft float from MIPS
This Patch removes Soft Float code from MIPS.
Instead It adds the soft float code from RISCV

The code came from FreeBSD and assumes the FreeBSD softfp
implementation not the one with GCC. That was an overlooked and
fixed in the other fenv code already.

Signed-off-by: Eshan Dhawan <eshandhawan51@gmail.com>
2021-02-05 10:32:16 +01:00
Jeff Johnston 415fdd4279 Bump up newlib version to 4.1.0 2020-12-18 18:50:49 -05:00
Sebastian Huber 6cc47c4c33 arm: Fix memchr() for Armv8-R
The Cortex-R52 processor is an Armv8-R processor with a NEON unit.  This
fix prevents conflicting architecture profiles A/R errors issued by the
linker.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2020-12-14 16:10:30 -05:00
Jeff Johnston 14123c991b Bump newlib release to 4.0.0 2020-12-11 14:37:12 -05:00
Jojo R 8315a90822 Port of C-SKY for newlib
Contributor list:  

  - Lifang Xia <lifang_xia@c-sky.com>  
  - Jojo R <jiejie_rong@c-sky.com>
  - Xianmiao Qu <xianmiao_qu@c-sky.com>
  - Yunhai Shang <yunhai_shang@c-sky.com>
2020-09-23 15:08:59 -04:00
Eshan dhawan b7a6e02dc6 arm: Fix fenv support
The previous fenv support for ARM used the soft-float implementation of
FreeBSD.  Newlib uses the one from libgcc by default.  They are not
compatible.  Having an GCC incompatible soft-float fenv support in
Newlib makes no sense.  A long-term solution could be to provide a
libgcc compatible soft-float support.  This likely requires changes in
the GCC configuration.  For now, provide a stub implementation for
soft-float multilibs similar to RISC-V.

Move implementation to one file and delete now unused files.  Hide
implementation details.  Remove function parameter names from header
file to avoid name conflicts.

Provide VFP support if __SOFTFP__ is not defined like glibc.

Reviewed-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-29 06:58:17 +02:00
PkmX via Newlib 123b806523 riscv: fix integer wraparound in memcpy
This patch fixes a bug in RISC-V's memcpy implementation where an
integer wraparound occurs when src + size < 8 * sizeof(long), causing
the word-sized copy loop to be incorrectly entered.

Signed-off-by: Chih-Mao Chen <cmchen@andestech.com>
2020-07-27 10:14:34 +02:00
Eshan dhawan via Newlib 104caeb7b1 Removed #ifndef _ARM_PCS_VFP_ from sys/fenv.h for arm
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-06 13:18:28 +02:00
Eshan dhawan via Newlib 65918715a0 mips fenv support
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-03 10:41:45 +02:00
Eshan dhawan via Newlib 03bf9f431c SPARC fenv support
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-03 10:41:45 +02:00
Eshan dhawan via Newlib fd5e27d362 fenv aarch64 support
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-02 12:12:39 +02:00
Eshan dhawan via Newlib a97bdf100f fenv support arm
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-06-09 21:13:17 -04:00
Eshan dhawan via Newlib e6ce6f1430 hard float support for PowerPC taken from FreeBSD
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-06-03 11:17:47 +02:00
Richard Earnshaw f973a7d8be arm: Finish moving newlib to unified syntax for Thumb1
Most code in newlib already uses unified syntax, but just a couple of
laggards remain.  This patch removes these and means the the entire
code base has now been converted.
2020-03-02 13:33:11 +00:00
Keith Packard 9042d0ce65 Use remove-advertising-clause script to edit BSD licenses
This edits licenses held by Berkeley and NetBSD, both of which
have removed the advertising requirement from their licenses.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-01-29 19:03:31 +01:00
Jeff Johnston 4e78f8ea16 Bump up newlib release to 3.3.0 2020-01-21 15:17:43 -05:00
Keith Packard 5377a84776 riscv: Map between ieeefp.h exception bits and RISC-V FCSR bits
If we had architecture-specific exception bits, we could just set them
to match the processor, but instead ieeefp.h is shared by all targets
so we need to map between the public values and the register contents.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-01-21 10:28:35 +01:00
Keith Packard 8e74c7119f riscv: Add 'break' statements to fpsetround switch
This makes the fpsetround function actually do something rather than
just return -1 due to the default 'fall-through' behavior of the switch
statement.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-01-21 10:28:35 +01:00
Keith Packard 954504ea14 riscv: Use current pseudo-instructions to access the FCSR register
Use fscsr and frcsr to store and read the FCSR register instead of
fssr and frsr.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-01-21 10:28:35 +01:00
Jeff Johnston 1afb22a120 Bump up release to 3.2.0 for yearly snapshot 2020-01-02 14:56:24 -05:00
Anthony Green b481c11e5a Optimize setjmp/longjmp for moxie.
We don't need to save/restore every register -- just those
we don't expect to be trashed by function calls.
2019-12-20 09:00:26 -05:00
Anthony Green 31227ba53d Fix setjmp/longjmp for the moxie port.
These functions needs to save and restore the stack frame, because
that's where the return address is stored.
2019-12-13 13:08:06 -05:00
Kwok Cheung Yeung d14714c690 Stash reent marker in upper bits of s1 on AMD GCN
s[0:3] contain a descriptor used to set up the initial value of the
stack, but only the lower 48 bits of s[0:1] are currently used.
The reent marker is currently set in s3, but by stashing it in the
upper 16 bits of s[0:1] instead, s3 can be freed up for other purposes.
2019-11-08 10:34:28 +01:00
Dimitar Dimitrov 0c7734673a Initial PRU port for libgloss and newlib
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2019-10-31 14:47:19 -04:00
Joel Sherrill 9e06ba1ac3 riscv/sys/fenv.h: Add missing extern for fe_dfl_env_p 2019-10-09 11:00:45 -05:00
Jeff Johnston cfc4955234 Add patch from Joel Sherrill for i386 and x86_64 fenv support 2019-10-08 16:59:04 -04:00
Christos Gentsos 175b215e05 Optimize epilogue sequence for architectures with POP interworking.
ARMv5 and above supports arm/thumb interworking using POP, so we can
improve the exit sequence in this case.
2019-10-07 14:38:14 +01:00
Joel Sherrill c711371384 riscv/include/fenv.h: Use shared fenv.h.
libc/include/fenv.h was a direct copy of this file.
2019-09-03 09:52:34 -05:00
Joel Sherrill 03f802846f Miscellaneous Makefile.in regenerated 2019-08-09 17:49:16 +02:00
Kito Cheng 654398db84 RISC-V: Fix header guard for sys/fenv.h 2019-08-02 09:34:39 +02:00
Martin Erik Werner 739e89cbe6 or1k: Avoid write outside setjmp buf & shrink buf
Update the offsets used to save registers into the stejmp jmp_buf
structure in order to:

* Avoid writing the supervision register outside the buffer and thus
  clobbering something on the stack. Previously the supervision register
  was written at offset 124 while the buffer was of length 124.

* Shrink the jmp_buf down to the size actually needed, by avoiding holes
  at the locations of omitted registers.
2019-06-27 12:51:54 +02:00
Martin Erik Werner 8b080534ca or1k: Correct longjmp return value
Invert equality check instruction to correct the return value handling
in longjmp.

The return value should be the value of the second argument to longjmp,
unless the argument value was 0 in which case it should be 1.

Previously, longjmp would set return value 1 if the second argument was
non-zero, and 0 if it was 0, which was incorrect.
2019-06-27 09:09:37 +02:00
Jeff Johnston eb429ad509 Fix __getreent stack calculations for AMD GCN
From: Andrew Stubbs <ams@codesourcery.com>

Fix a bug in which the high-part of 64-bit values are being corrupted, leading
to erroneous stack overflow errors. The problem was only that the mixed-size
calculations are being treated as signed when they should be unsigned.
2019-06-07 13:57:45 -04:00
Jim Wilson 5c86f0da5f RISC-V: Add size optimized memcpy, memmove, memset and strcmp.
This patch adds implementations of memcpy, memmove, memset and strcmp
optimized for size. The changes have been tested in
riscv/riscv-gnu-toolchain by riscv-dejagnu with
riscv-sim.exp/riscv-sim-nano.exp.
2019-05-22 17:36:57 -07:00
Jozef Lawrynowicz 1e6c561d48 Implement reduced code size "tiny" printf and puts
"tiny" printf is derived from _vfprintf_r in libc/stdio/nano-vfprintf.c.
"tiny" puts has been implemented so that it just calls write, without
any other processing.
Support for buffering, reentrancy and streams has been removed from
these functions to achieve reduced code size.

This reduced code size implementation of printf and puts can be enabled
in an application by passing "--wrap printf" and "--wrap puts" to the
GNU linker. This will replace references to "printf" and "puts" in user
code with "__wrap_printf" and "__wrap_puts" respectively.
If there is no implementation of these __wrap* functions in user code,
these "tiny" printf and puts implementations will be linked into the
final executable.

The wrapping mechanism is supposed to be invisible to the user:
- A GCC wrapper option such as "-mtiny-printf" will be added to alias
  these wrap commands.
- If the user is unaware of the "tiny" implementation, and chooses to
  implement their own __wrap_printf and __wrap_puts, their own
  implementation will be automatically chosen over the "tiny" printf and
  puts from the library.

Newlib must be configured with --enable-newlib-nano-formatted-io for
the "tiny" printf and puts functions to be built into the library.

Code size reduction examples:
printf("Hello World\n")
  baseline - msp430-elf-gcc gcc-8_3_0-release
     text    data     bss
   5638     214      26
  "tiny" puts enabled
    text    data     bss
     714      90      20

printf("Hello %d\n", a)
  baseline - msp430-elf-gcc gcc-8_3_0-release
    text    data     bss
   10916     614      28

  "tiny" printf enabled
    text    data     bss
    4632     280      20
2019-04-15 14:22:33 +02:00
Jozef Lawrynowicz 2af6ad9f05 Copy prerequisite file for "tiny" printf implementation
Use newlib/libc/stdio/nano-vfprintf.c as baseline for tiny-printf.c
2019-04-15 14:22:30 +02:00
Andrew Stubbs e8b23909e4 Add missing includes.
These missing includes were causing build warnings, but also a real bug in
which the "size" parameter to "write" was being passed in 32-bit, whereas it
ought to be 64-bit.  This led to intermittent bad behaviour.
2019-03-25 16:44:10 +01:00
Jozef Lawrynowicz b14a879d85 Remove matherr, and SVID and X/Open math library configurations
Default math library configuration is now IEEE
2019-01-23 10:46:24 +01:00
Jeff Johnston 1787e9d033 AMD GCN Port contributed by Andrew Stubbs <ams@codesourcery.com>
Add support for the AMD GCN GPU architecture.  This is primarily intended for
use with OpenMP and OpenACC offloading.  It can also be used for stand-alone
programs, but this is intended mostly for testing the compiler and is not
expected to be useful in general.

The GPU architecture is highly parallel, and therefore Newlib must be
configured to use dynamic re-entrancy, and thread-safe malloc.

The only I/O available is a via a shared-memory interface provided by libgomp
and the gcn-run tool included with GCC.  At this time this is limited to
stdout, argc/argv, and the return code.
2019-01-15 10:48:08 -05:00
Jeff Johnston 5726873100 Bump release to 3.1.0 for yearly snapshot 2018-12-31 23:40:11 -05:00
Wilco Dijkstra df7824d1a4 Fix issue with dst bias in memset
This patch fixes an issue in the previous memset loop change. If the
zva size is >= 256 and there are more than 64 bytes left in the
tail, we could enter the loop and thus need to rebias dst by 32 as
well.

Since no known CPUs use this size this can't be tested natively, so I've
tested it on a simulator initialized with a large zva size.

--
2018-11-08 16:45:19 +00:00
Wilco Dijkstra d80db60066 Adjust writeback in non-zero memset
This fixes an ineffiency in the non-zero memset.  Delaying the writeback
until the end of the loop is slightly faster on some cores - this shows
~5% performance gain on Cortex-A53 when doing large non-zero memsets.

Tested against the GLIBC testsuite.
2018-11-06 14:59:51 +00:00
Sebastian Huber da418955f5 Move common <sys/dirent.h> content to <dirent.h>
Move common content of the various <sys/dirent.h> and the latest FreeBSD
<dirent.h> to <dirent.h>.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2018-10-11 08:29:16 +02:00
Jon Beniston a9cfb33b6c Add --disable-newlib-fno-builtin to allow compilation without -fno-builtin for smaller and faster code. 2018-08-31 15:40:42 -04:00
Keith Packard 82dfae9ab0 Use __inhibit_loop_to_libcall in all memset/memcpy implementations
This macro selects a compiler option that disables recognition of
common memset/memcpy patterns and converting those to direct
memset/memcpy calls.

Signed-off-by: Keith Packard <keithp@keithp.com>
2018-08-29 16:05:37 +02:00
Siddhesh Poyarekar d02cc7a09d strcmp.S: Improve performance for misaligned strings
Replace the simple byte-wise compare in the misaligned case with a
dword compare with page boundary checks in place.  For simplicity I've
chosen a 4K page boundary so that we don't have to query the actual
page size on the system.

This results in up to 3x improvement in performance in the unaligned
case on falkor and about 2.5x improvement on mustang as measured using
bench-strcmp in glibc.
2018-07-13 13:27:54 +02:00
Siddhesh Poyarekar 2d9f35c2cc memcmp.S: optimize for medium to large sizes
This improved memcmp provides a fast path for compares up to 16 bytes
and then compares 16 bytes at a time, thus optimizing loads from both
sources.  The glibc memcmp microbenchmark retains performance (with an
error of ~1ns) for smaller compare sizes and reduces up to 31% of
execution time for compares up to 4K on the APM Mustang.  On Qualcomm
Falkor this improves to almost 48%, i.e. it is almost 2x improvement
for sizes of 2K and above.
2018-07-13 13:27:54 +02:00
Siddhesh Poyarekar f44eee8f1b Improve strncmp for mutually misaligned inputs
The mutually misaligned inputs on aarch64 are compared with a simple
byte copy, which is not very efficient.  Enhance the comparison
similar to strcmp by loading a double-word at a time.  The peak
performance improvement (i.e. 4k maxlen comparisons) due to this on
the strncmp microbenchmark in glibc is as follows:

falkor: 3.5x (up to 72% time reduction)
cortex-a73: 3.5x (up to 71% time reduction)
cortex-a53: 3.5x (up to 71% time reduction)

All mutually misaligned inputs from 16 bytes maxlen onwards show
upwards of 15% improvement and there is no measurable effect on the
performance of aligned/mutually aligned inputs.
2018-07-13 13:27:54 +02:00
Jeff Johnston cd31fbb2ae Add nvptx port.
- From: Cesar Philippidis <cesar@codesourcery.com>
  Date: Tue, 10 Apr 2018 14:43:42 -0700
  Subject: [PATCH] nvptx port

  This port adds support for Nvidia GPU's, which are primarily used as
  offload accelerators in OpenACC and OpenMP.
2018-04-13 15:42:37 -04:00
Sebastian Huber 1658a57715 epiphany: Additional setjmp() and longjmp() syms
At least with Binutils 2.30 and GCC 7.3 we need symbol definitions
without the leading underscore.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2018-01-31 08:17:19 +01:00