Commit Graph

568 Commits

Author SHA1 Message Date
Corinna Vinschen cc19109af9 Cygwin: don't export _feinitialise from newlib
Use the more official fesetenv(FE_DFL_ENV) from _dll_crt0, thus
allowing to drop the _feinitialise declaration from fenv.h.

Provide a no-op _feinitialise in Cygwin as exportable symbol for really
old applications when _feinitialise was called from mainCRTStartup in
crt0.o.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2021-04-13 12:55:34 +02:00
Corinna Vinschen 3b22d72255 fenv: drop Cygwin-specific implementation in favor of newlib code
Drop the Cygwin-specific fenv.cc and fenv.h file and use the equivalent
newlib functionality now, so we have at least one example of a user for
this new mechanism.

fenv.c: allow _feinitialise to be called from Cygwin startup code

fenv.h: add declarations for fegetprec and fesetprec for Cygwin only.
        Fix a comment.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2021-04-13 12:55:34 +02:00
Corinna Vinschen 05753071c0 fenv: Move shared x86 sys/fenv.h from x86_64 to shared_x86
drop matching symlink in i386

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2021-04-13 12:55:33 +02:00
Corinna Vinschen 79ac4237dc fenv: add missing declarations to x86 fenv.h
feenableexcept, fedisableexcept and fegetexcept were
accidentally missing in the x86 fenv.h

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2021-04-13 12:55:33 +02:00
Marcus Comstedt 26478769a6 RISC-V: Fix optimized strcmp on big endian 2021-02-25 12:14:18 +01:00
Eshan dhawan 55a6e49a08 Removed Soft float from MIPS
This Patch removes Soft Float code from MIPS.
Instead It adds the soft float code from RISCV

The code came from FreeBSD and assumes the FreeBSD softfp
implementation not the one with GCC. That was an overlooked and
fixed in the other fenv code already.

Signed-off-by: Eshan Dhawan <eshandhawan51@gmail.com>
2021-02-05 10:32:16 +01:00
Jeff Johnston 415fdd4279 Bump up newlib version to 4.1.0 2020-12-18 18:50:49 -05:00
Sebastian Huber 6cc47c4c33 arm: Fix memchr() for Armv8-R
The Cortex-R52 processor is an Armv8-R processor with a NEON unit.  This
fix prevents conflicting architecture profiles A/R errors issued by the
linker.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2020-12-14 16:10:30 -05:00
Jeff Johnston 14123c991b Bump newlib release to 4.0.0 2020-12-11 14:37:12 -05:00
Jojo R 8315a90822 Port of C-SKY for newlib
Contributor list:  

  - Lifang Xia <lifang_xia@c-sky.com>  
  - Jojo R <jiejie_rong@c-sky.com>
  - Xianmiao Qu <xianmiao_qu@c-sky.com>
  - Yunhai Shang <yunhai_shang@c-sky.com>
2020-09-23 15:08:59 -04:00
Eshan dhawan b7a6e02dc6 arm: Fix fenv support
The previous fenv support for ARM used the soft-float implementation of
FreeBSD.  Newlib uses the one from libgcc by default.  They are not
compatible.  Having an GCC incompatible soft-float fenv support in
Newlib makes no sense.  A long-term solution could be to provide a
libgcc compatible soft-float support.  This likely requires changes in
the GCC configuration.  For now, provide a stub implementation for
soft-float multilibs similar to RISC-V.

Move implementation to one file and delete now unused files.  Hide
implementation details.  Remove function parameter names from header
file to avoid name conflicts.

Provide VFP support if __SOFTFP__ is not defined like glibc.

Reviewed-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-29 06:58:17 +02:00
PkmX via Newlib 123b806523 riscv: fix integer wraparound in memcpy
This patch fixes a bug in RISC-V's memcpy implementation where an
integer wraparound occurs when src + size < 8 * sizeof(long), causing
the word-sized copy loop to be incorrectly entered.

Signed-off-by: Chih-Mao Chen <cmchen@andestech.com>
2020-07-27 10:14:34 +02:00
Eshan dhawan via Newlib 104caeb7b1 Removed #ifndef _ARM_PCS_VFP_ from sys/fenv.h for arm
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-06 13:18:28 +02:00
Eshan dhawan via Newlib 65918715a0 mips fenv support
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-03 10:41:45 +02:00
Eshan dhawan via Newlib 03bf9f431c SPARC fenv support
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-03 10:41:45 +02:00
Eshan dhawan via Newlib fd5e27d362 fenv aarch64 support
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-07-02 12:12:39 +02:00
Eshan dhawan via Newlib a97bdf100f fenv support arm
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-06-09 21:13:17 -04:00
Eshan dhawan via Newlib e6ce6f1430 hard float support for PowerPC taken from FreeBSD
Signed-off-by: Eshan dhawan <eshandhawan51@gmail.com>
2020-06-03 11:17:47 +02:00
Richard Earnshaw f973a7d8be arm: Finish moving newlib to unified syntax for Thumb1
Most code in newlib already uses unified syntax, but just a couple of
laggards remain.  This patch removes these and means the the entire
code base has now been converted.
2020-03-02 13:33:11 +00:00
Keith Packard 9042d0ce65 Use remove-advertising-clause script to edit BSD licenses
This edits licenses held by Berkeley and NetBSD, both of which
have removed the advertising requirement from their licenses.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-01-29 19:03:31 +01:00
Jeff Johnston 4e78f8ea16 Bump up newlib release to 3.3.0 2020-01-21 15:17:43 -05:00
Keith Packard 5377a84776 riscv: Map between ieeefp.h exception bits and RISC-V FCSR bits
If we had architecture-specific exception bits, we could just set them
to match the processor, but instead ieeefp.h is shared by all targets
so we need to map between the public values and the register contents.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-01-21 10:28:35 +01:00
Keith Packard 8e74c7119f riscv: Add 'break' statements to fpsetround switch
This makes the fpsetround function actually do something rather than
just return -1 due to the default 'fall-through' behavior of the switch
statement.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-01-21 10:28:35 +01:00
Keith Packard 954504ea14 riscv: Use current pseudo-instructions to access the FCSR register
Use fscsr and frcsr to store and read the FCSR register instead of
fssr and frsr.

Signed-off-by: Keith Packard <keithp@keithp.com>
2020-01-21 10:28:35 +01:00
Jeff Johnston 1afb22a120 Bump up release to 3.2.0 for yearly snapshot 2020-01-02 14:56:24 -05:00
Anthony Green b481c11e5a Optimize setjmp/longjmp for moxie.
We don't need to save/restore every register -- just those
we don't expect to be trashed by function calls.
2019-12-20 09:00:26 -05:00
Anthony Green 31227ba53d Fix setjmp/longjmp for the moxie port.
These functions needs to save and restore the stack frame, because
that's where the return address is stored.
2019-12-13 13:08:06 -05:00
Kwok Cheung Yeung d14714c690 Stash reent marker in upper bits of s1 on AMD GCN
s[0:3] contain a descriptor used to set up the initial value of the
stack, but only the lower 48 bits of s[0:1] are currently used.
The reent marker is currently set in s3, but by stashing it in the
upper 16 bits of s[0:1] instead, s3 can be freed up for other purposes.
2019-11-08 10:34:28 +01:00
Dimitar Dimitrov 0c7734673a Initial PRU port for libgloss and newlib
Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2019-10-31 14:47:19 -04:00
Joel Sherrill 9e06ba1ac3 riscv/sys/fenv.h: Add missing extern for fe_dfl_env_p 2019-10-09 11:00:45 -05:00
Jeff Johnston cfc4955234 Add patch from Joel Sherrill for i386 and x86_64 fenv support 2019-10-08 16:59:04 -04:00
Christos Gentsos 175b215e05 Optimize epilogue sequence for architectures with POP interworking.
ARMv5 and above supports arm/thumb interworking using POP, so we can
improve the exit sequence in this case.
2019-10-07 14:38:14 +01:00
Joel Sherrill c711371384 riscv/include/fenv.h: Use shared fenv.h.
libc/include/fenv.h was a direct copy of this file.
2019-09-03 09:52:34 -05:00
Joel Sherrill 03f802846f Miscellaneous Makefile.in regenerated 2019-08-09 17:49:16 +02:00
Kito Cheng 654398db84 RISC-V: Fix header guard for sys/fenv.h 2019-08-02 09:34:39 +02:00
Martin Erik Werner 739e89cbe6 or1k: Avoid write outside setjmp buf & shrink buf
Update the offsets used to save registers into the stejmp jmp_buf
structure in order to:

* Avoid writing the supervision register outside the buffer and thus
  clobbering something on the stack. Previously the supervision register
  was written at offset 124 while the buffer was of length 124.

* Shrink the jmp_buf down to the size actually needed, by avoiding holes
  at the locations of omitted registers.
2019-06-27 12:51:54 +02:00
Martin Erik Werner 8b080534ca or1k: Correct longjmp return value
Invert equality check instruction to correct the return value handling
in longjmp.

The return value should be the value of the second argument to longjmp,
unless the argument value was 0 in which case it should be 1.

Previously, longjmp would set return value 1 if the second argument was
non-zero, and 0 if it was 0, which was incorrect.
2019-06-27 09:09:37 +02:00
Jeff Johnston eb429ad509 Fix __getreent stack calculations for AMD GCN
From: Andrew Stubbs <ams@codesourcery.com>

Fix a bug in which the high-part of 64-bit values are being corrupted, leading
to erroneous stack overflow errors. The problem was only that the mixed-size
calculations are being treated as signed when they should be unsigned.
2019-06-07 13:57:45 -04:00
Jim Wilson 5c86f0da5f RISC-V: Add size optimized memcpy, memmove, memset and strcmp.
This patch adds implementations of memcpy, memmove, memset and strcmp
optimized for size. The changes have been tested in
riscv/riscv-gnu-toolchain by riscv-dejagnu with
riscv-sim.exp/riscv-sim-nano.exp.
2019-05-22 17:36:57 -07:00
Jozef Lawrynowicz 1e6c561d48 Implement reduced code size "tiny" printf and puts
"tiny" printf is derived from _vfprintf_r in libc/stdio/nano-vfprintf.c.
"tiny" puts has been implemented so that it just calls write, without
any other processing.
Support for buffering, reentrancy and streams has been removed from
these functions to achieve reduced code size.

This reduced code size implementation of printf and puts can be enabled
in an application by passing "--wrap printf" and "--wrap puts" to the
GNU linker. This will replace references to "printf" and "puts" in user
code with "__wrap_printf" and "__wrap_puts" respectively.
If there is no implementation of these __wrap* functions in user code,
these "tiny" printf and puts implementations will be linked into the
final executable.

The wrapping mechanism is supposed to be invisible to the user:
- A GCC wrapper option such as "-mtiny-printf" will be added to alias
  these wrap commands.
- If the user is unaware of the "tiny" implementation, and chooses to
  implement their own __wrap_printf and __wrap_puts, their own
  implementation will be automatically chosen over the "tiny" printf and
  puts from the library.

Newlib must be configured with --enable-newlib-nano-formatted-io for
the "tiny" printf and puts functions to be built into the library.

Code size reduction examples:
printf("Hello World\n")
  baseline - msp430-elf-gcc gcc-8_3_0-release
     text    data     bss
   5638     214      26
  "tiny" puts enabled
    text    data     bss
     714      90      20

printf("Hello %d\n", a)
  baseline - msp430-elf-gcc gcc-8_3_0-release
    text    data     bss
   10916     614      28

  "tiny" printf enabled
    text    data     bss
    4632     280      20
2019-04-15 14:22:33 +02:00
Jozef Lawrynowicz 2af6ad9f05 Copy prerequisite file for "tiny" printf implementation
Use newlib/libc/stdio/nano-vfprintf.c as baseline for tiny-printf.c
2019-04-15 14:22:30 +02:00
Andrew Stubbs e8b23909e4 Add missing includes.
These missing includes were causing build warnings, but also a real bug in
which the "size" parameter to "write" was being passed in 32-bit, whereas it
ought to be 64-bit.  This led to intermittent bad behaviour.
2019-03-25 16:44:10 +01:00
Jozef Lawrynowicz b14a879d85 Remove matherr, and SVID and X/Open math library configurations
Default math library configuration is now IEEE
2019-01-23 10:46:24 +01:00
Jeff Johnston 1787e9d033 AMD GCN Port contributed by Andrew Stubbs <ams@codesourcery.com>
Add support for the AMD GCN GPU architecture.  This is primarily intended for
use with OpenMP and OpenACC offloading.  It can also be used for stand-alone
programs, but this is intended mostly for testing the compiler and is not
expected to be useful in general.

The GPU architecture is highly parallel, and therefore Newlib must be
configured to use dynamic re-entrancy, and thread-safe malloc.

The only I/O available is a via a shared-memory interface provided by libgomp
and the gcn-run tool included with GCC.  At this time this is limited to
stdout, argc/argv, and the return code.
2019-01-15 10:48:08 -05:00
Jeff Johnston 5726873100 Bump release to 3.1.0 for yearly snapshot 2018-12-31 23:40:11 -05:00
Wilco Dijkstra df7824d1a4 Fix issue with dst bias in memset
This patch fixes an issue in the previous memset loop change. If the
zva size is >= 256 and there are more than 64 bytes left in the
tail, we could enter the loop and thus need to rebias dst by 32 as
well.

Since no known CPUs use this size this can't be tested natively, so I've
tested it on a simulator initialized with a large zva size.

--
2018-11-08 16:45:19 +00:00
Wilco Dijkstra d80db60066 Adjust writeback in non-zero memset
This fixes an ineffiency in the non-zero memset.  Delaying the writeback
until the end of the loop is slightly faster on some cores - this shows
~5% performance gain on Cortex-A53 when doing large non-zero memsets.

Tested against the GLIBC testsuite.
2018-11-06 14:59:51 +00:00
Sebastian Huber da418955f5 Move common <sys/dirent.h> content to <dirent.h>
Move common content of the various <sys/dirent.h> and the latest FreeBSD
<dirent.h> to <dirent.h>.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2018-10-11 08:29:16 +02:00
Jon Beniston a9cfb33b6c Add --disable-newlib-fno-builtin to allow compilation without -fno-builtin for smaller and faster code. 2018-08-31 15:40:42 -04:00
Keith Packard 82dfae9ab0 Use __inhibit_loop_to_libcall in all memset/memcpy implementations
This macro selects a compiler option that disables recognition of
common memset/memcpy patterns and converting those to direct
memset/memcpy calls.

Signed-off-by: Keith Packard <keithp@keithp.com>
2018-08-29 16:05:37 +02:00
Siddhesh Poyarekar d02cc7a09d strcmp.S: Improve performance for misaligned strings
Replace the simple byte-wise compare in the misaligned case with a
dword compare with page boundary checks in place.  For simplicity I've
chosen a 4K page boundary so that we don't have to query the actual
page size on the system.

This results in up to 3x improvement in performance in the unaligned
case on falkor and about 2.5x improvement on mustang as measured using
bench-strcmp in glibc.
2018-07-13 13:27:54 +02:00
Siddhesh Poyarekar 2d9f35c2cc memcmp.S: optimize for medium to large sizes
This improved memcmp provides a fast path for compares up to 16 bytes
and then compares 16 bytes at a time, thus optimizing loads from both
sources.  The glibc memcmp microbenchmark retains performance (with an
error of ~1ns) for smaller compare sizes and reduces up to 31% of
execution time for compares up to 4K on the APM Mustang.  On Qualcomm
Falkor this improves to almost 48%, i.e. it is almost 2x improvement
for sizes of 2K and above.
2018-07-13 13:27:54 +02:00
Siddhesh Poyarekar f44eee8f1b Improve strncmp for mutually misaligned inputs
The mutually misaligned inputs on aarch64 are compared with a simple
byte copy, which is not very efficient.  Enhance the comparison
similar to strcmp by loading a double-word at a time.  The peak
performance improvement (i.e. 4k maxlen comparisons) due to this on
the strncmp microbenchmark in glibc is as follows:

falkor: 3.5x (up to 72% time reduction)
cortex-a73: 3.5x (up to 71% time reduction)
cortex-a53: 3.5x (up to 71% time reduction)

All mutually misaligned inputs from 16 bytes maxlen onwards show
upwards of 15% improvement and there is no measurable effect on the
performance of aligned/mutually aligned inputs.
2018-07-13 13:27:54 +02:00
Jeff Johnston cd31fbb2ae Add nvptx port.
- From: Cesar Philippidis <cesar@codesourcery.com>
  Date: Tue, 10 Apr 2018 14:43:42 -0700
  Subject: [PATCH] nvptx port

  This port adds support for Nvidia GPU's, which are primarily used as
  offload accelerators in OpenACC and OpenMP.
2018-04-13 15:42:37 -04:00
Sebastian Huber 1658a57715 epiphany: Additional setjmp() and longjmp() syms
At least with Binutils 2.30 and GCC 7.3 we need symbol definitions
without the leading underscore.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2018-01-31 08:17:19 +01:00
Jeff Johnston fffd2770db Bump release to 3.0.0 for yearly snapshot
- major release required due to removal of K&R support
2018-01-18 13:07:45 -05:00
Yaakov Selkowitz 7192f84096 ansification: remove _HAVE_STDC
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:30 -06:00
Yaakov Selkowitz 70ee6b17df ansification: remove _EXFUN, _EXFUN_NOTHROW
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:29 -06:00
Yaakov Selkowitz 9087163804 ansification: remove _DEFUN
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:26 -06:00
Yaakov Selkowitz 67ee0cac4c ansification: remove _VOID
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:20 -06:00
Yaakov Selkowitz fff27f8429 ansification: remove _DEFUN_VOID
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:19 -06:00
Yaakov Selkowitz 670b01da7f ansification: remove _CAST_VOID
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:17 -06:00
Yaakov Selkowitz e6321aa6a6 ansification: remove _PTR
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:16 -06:00
Yaakov Selkowitz eea249da3b ansification: remove _PARAMS
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:13 -06:00
Yaakov Selkowitz 0bda30e1ff ansification: remove _CONST
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:08 -06:00
Yaakov Selkowitz 6783860a2e ansification: remove _AND
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2018-01-17 11:47:05 -06:00
Jon Turney c006fd459f makedoc: make errors visible
Discard QUICKREF sections, rather than writing them to stderr
Discard MATHREF sections, rather than discarding as an error
Pass NOTES sections through to texinfo, rather than discarding as an error
Don't redirect makedoc stderr to .ref file
Remove makedoc output on error
Remove .ref files from CLEANFILES
Regenerate Makefile.ins

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
2017-12-07 11:54:11 +00:00
Yaakov Selkowitz 1f1e477554 powerpc: remove TRAD_SYNOPSIS
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2017-12-01 03:41:50 -06:00
Yaakov Selkowitz ddd22ee069 nds32: remove TRAD_SYNOPSIS
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2017-12-01 03:41:50 -06:00
Yaakov Selkowitz 4e8c64b928 microblaze: remove TRAD_SYNOPSIS
Signed-off-by: Yaakov Selkowitz <yselkowi@redhat.com>
2017-12-01 03:41:50 -06:00
Kito Cheng 6864c08b94 Change license to FreeBSD License for RISC-V
- For prevent confuse about what BSD license variant we used, 2- or
   3-clause license, we change the license to FreeBSD license to make
   it unambiguously refers to the 2-clause license.
2017-08-21 11:08:54 +02:00
Kito Cheng 363dbb9e44 Add RISC-V port for newlib
Contributor list:
    - Andrew Waterman  <andrew@sifive.com>
    - Palmer Dabbelt  <palmer@dabbelt.com>
    - Kito Cheng  <kito.cheng@gmail.com>
    - Scott Beamer  <sbeamer@eecs.berkeley.edu>
2017-08-16 18:00:58 -04:00
Richard Earnshaw d6cac3e1da [arm] Fix strcpy for unified syntax on ARMv4t thumb.
ARMv4t does not support mov between two low registers.  Now we use
unified syntax mov instructions need converting to movs.
2017-07-21 11:23:27 +01:00
Ian Tessier via newlib 4bce7ecbe1 arm: Update strcpy.c to use UAL syntax.
With this change the arm platform can now be fully compiled with Clang.

Tested by comparing the output with GCC 4.8.2, and Clang 4.0, using a
variety of arches, big/little endianness, and arm/thumb mode to verify
the generated assembly output matches between GCC vs Clang with UAL, and
also GCC with UAL vs GCC with non-UAL, for all preprocessor code blocks.

The only difference found is an extra nop at the end of the function
when compiled with GCC using armv7-a/thumb/little-endian/-O2 compared to
Clang. The nop is not emitted when compiled in big-endian mode.
2017-07-20 16:18:29 +02:00
Wilco Dijkstra c86063bdc0 Optimized memcmp
This is an optimized memcmp for AArch64.  This is a complete rewrite
using a different algorithm.  The previous version split into cases
where both inputs were aligned, the inputs were mutually aligned and
unaligned using a byte loop.  The new version combines all these cases,
while small inputs of less than 8 bytes are handled separately.

This allows the main code to be sped up using unaligned loads since
there are now at least 8 bytes to be compared.  After the first 8 bytes,
align the first input.  This ensures each iteration does at most one
unaligned access and mutually aligned inputs behave as aligned.
After the main loop, process the last 8 bytes using unaligned accesses.

This improves performance of (mutually) aligned cases by 25% and
unaligned by >500% (yes >6 times faster) on large inputs.

ChangeLog:
2017-06-28  Wilco Dijkstra  <wdijkstr@arm.com>

        * newlib/libc/machine/aarch64/memcmp.S (memcmp):
        Rewrite of optimized memcmp.

GLIBC benchtests/bench-memcmp.c performance comparison for Cortex-A53:

Length    1, alignment  1/ 1:		153%
Length    1, alignment  1/ 1:		119%
Length    1, alignment  1/ 1:		154%
Length    2, alignment  2/ 2:		121%
Length    2, alignment  2/ 2:		140%
Length    2, alignment  2/ 2:		121%
Length    3, alignment  3/ 3:		105%
Length    3, alignment  3/ 3:		105%
Length    3, alignment  3/ 3:		105%
Length    4, alignment  4/ 4:		155%
Length    4, alignment  4/ 4:		154%
Length    4, alignment  4/ 4:		161%
Length    5, alignment  5/ 5:		173%
Length    5, alignment  5/ 5:		173%
Length    5, alignment  5/ 5:		173%
Length    6, alignment  6/ 6:		145%
Length    6, alignment  6/ 6:		145%
Length    6, alignment  6/ 6:		145%
Length    7, alignment  7/ 7:		125%
Length    7, alignment  7/ 7:		125%
Length    7, alignment  7/ 7:		125%
Length    8, alignment  8/ 8:		111%
Length    8, alignment  8/ 8:		130%
Length    8, alignment  8/ 8:		124%
Length    9, alignment  9/ 9:		160%
Length    9, alignment  9/ 9:		160%
Length    9, alignment  9/ 9:		150%
Length   10, alignment 10/10:		170%
Length   10, alignment 10/10:		137%
Length   10, alignment 10/10:		150%
Length   11, alignment 11/11:		160%
Length   11, alignment 11/11:		160%
Length   11, alignment 11/11:		160%
Length   12, alignment 12/12:		146%
Length   12, alignment 12/12:		168%
Length   12, alignment 12/12:		156%
Length   13, alignment 13/13:		167%
Length   13, alignment 13/13:		167%
Length   13, alignment 13/13:		173%
Length   14, alignment 14/14:		167%
Length   14, alignment 14/14:		168%
Length   14, alignment 14/14:		168%
Length   15, alignment 15/15:		168%
Length   15, alignment 15/15:		173%
Length   15, alignment 15/15:		173%
Length    1, alignment  0/ 0:		134%
Length    1, alignment  0/ 0:		127%
Length    1, alignment  0/ 0:		119%
Length    2, alignment  0/ 0:		94%
Length    2, alignment  0/ 0:		94%
Length    2, alignment  0/ 0:		106%
Length    3, alignment  0/ 0:		82%
Length    3, alignment  0/ 0:		87%
Length    3, alignment  0/ 0:		82%
Length    4, alignment  0/ 0:		115%
Length    4, alignment  0/ 0:		115%
Length    4, alignment  0/ 0:		122%
Length    5, alignment  0/ 0:		127%
Length    5, alignment  0/ 0:		119%
Length    5, alignment  0/ 0:		127%
Length    6, alignment  0/ 0:		103%
Length    6, alignment  0/ 0:		100%
Length    6, alignment  0/ 0:		100%
Length    7, alignment  0/ 0:		82%
Length    7, alignment  0/ 0:		91%
Length    7, alignment  0/ 0:		87%
Length    8, alignment  0/ 0:		111%
Length    8, alignment  0/ 0:		124%
Length    8, alignment  0/ 0:		124%
Length    9, alignment  0/ 0:		136%
Length    9, alignment  0/ 0:		136%
Length    9, alignment  0/ 0:		136%
Length   10, alignment  0/ 0:		136%
Length   10, alignment  0/ 0:		135%
Length   10, alignment  0/ 0:		136%
Length   11, alignment  0/ 0:		136%
Length   11, alignment  0/ 0:		136%
Length   11, alignment  0/ 0:		135%
Length   12, alignment  0/ 0:		136%
Length   12, alignment  0/ 0:		136%
Length   12, alignment  0/ 0:		136%
Length   13, alignment  0/ 0:		135%
Length   13, alignment  0/ 0:		136%
Length   13, alignment  0/ 0:		136%
Length   14, alignment  0/ 0:		136%
Length   14, alignment  0/ 0:		136%
Length   14, alignment  0/ 0:		136%
Length   15, alignment  0/ 0:		136%
Length   15, alignment  0/ 0:		136%
Length   15, alignment  0/ 0:		136%
Length    4, alignment  0/ 0:		115%
Length    4, alignment  0/ 0:		115%
Length    4, alignment  0/ 0:		115%
Length   32, alignment  0/ 0:		127%
Length   32, alignment  7/ 2:		395%
Length   32, alignment  0/ 0:		127%
Length   32, alignment  0/ 0:		127%
Length    8, alignment  0/ 0:		111%
Length    8, alignment  0/ 0:		124%
Length    8, alignment  0/ 0:		124%
Length   64, alignment  0/ 0:		128%
Length   64, alignment  6/ 4:		475%
Length   64, alignment  0/ 0:		131%
Length   64, alignment  0/ 0:		134%
Length   16, alignment  0/ 0:		128%
Length   16, alignment  0/ 0:		119%
Length   16, alignment  0/ 0:		128%
Length  128, alignment  0/ 0:		129%
Length  128, alignment  5/ 6:		475%
Length  128, alignment  0/ 0:		130%
Length  128, alignment  0/ 0:		129%
Length   32, alignment  0/ 0:		126%
Length   32, alignment  0/ 0:		126%
Length   32, alignment  0/ 0:		126%
Length  256, alignment  0/ 0:		127%
Length  256, alignment  4/ 8:		545%
Length  256, alignment  0/ 0:		126%
Length  256, alignment  0/ 0:		128%
Length   64, alignment  0/ 0:		171%
Length   64, alignment  0/ 0:		171%
Length   64, alignment  0/ 0:		174%
Length  512, alignment  0/ 0:		126%
Length  512, alignment  3/10:		585%
Length  512, alignment  0/ 0:		126%
Length  512, alignment  0/ 0:		127%
Length  128, alignment  0/ 0:		129%
Length  128, alignment  0/ 0:		128%
Length  128, alignment  0/ 0:		129%
Length 1024, alignment  0/ 0:		125%
Length 1024, alignment  2/12:		611%
Length 1024, alignment  0/ 0:		126%
Length 1024, alignment  0/ 0:		126%
Length  256, alignment  0/ 0:		128%
Length  256, alignment  0/ 0:		127%
Length  256, alignment  0/ 0:		128%
Length 2048, alignment  0/ 0:		125%
Length 2048, alignment  1/14:		625%
Length 2048, alignment  0/ 0:		125%
Length 2048, alignment  0/ 0:		125%
Length  512, alignment  0/ 0:		126%
Length  512, alignment  0/ 0:		127%
Length  512, alignment  0/ 0:		127%
Length 4096, alignment  0/ 0:		125%
Length 4096, alignment  0/16:		125%
Length 4096, alignment  0/ 0:		125%
Length 4096, alignment  0/ 0:		125%
Length 1024, alignment  0/ 0:		126%
Length 1024, alignment  0/ 0:		126%
Length 1024, alignment  0/ 0:		126%
Length 8192, alignment  0/ 0:		125%
Length 8192, alignment 63/18:		636%
Length 8192, alignment  0/ 0:		125%
Length 8192, alignment  0/ 0:		125%
Length   16, alignment  1/ 2:		317%
Length   16, alignment  1/ 2:		317%
Length   16, alignment  1/ 2:		317%
Length   32, alignment  2/ 4:		395%
Length   32, alignment  2/ 4:		395%
Length   32, alignment  2/ 4:		398%
Length   64, alignment  3/ 6:		475%
Length   64, alignment  3/ 6:		475%
Length   64, alignment  3/ 6:		477%
Length  128, alignment  4/ 8:		479%
Length  128, alignment  4/ 8:		479%
Length  128, alignment  4/ 8:		479%
Length  256, alignment  5/10:		543%
Length  256, alignment  5/10:		539%
Length  256, alignment  5/10:		543%
Length  512, alignment  6/12:		585%
Length  512, alignment  6/12:		585%
Length  512, alignment  6/12:		585%
Length 1024, alignment  7/14:		611%
Length 1024, alignment  7/14:		611%
Length 1024, alignment  7/14:		611%
2017-06-29 20:36:35 +02:00
Sebastian Pop 9938a64ca9 aarch64: optimize the unaligned case of memcmp
This brings to newlib a performance improvement that we developed in Bionic
libc.  That change has been submitted for review to Bionic libc:
https://android-review.googlesource.com/418279

A similar patch has been submitted for review in glibc:
https://sourceware.org/ml/libc-alpha/2017-06/msg01143.html

Patch written by Vikas Sinha and Sebastian Pop.

The performance was measured on the bionic-benchmarks on a hikey (aarch64 8xA53)
board. There was no performance change to the existing benchmark
and a performance improvement on the new benchmark for memcmp
on the unaligned side. The new benchmark has been submitted for
review at https://android-review.googlesource.com/414860

The overall performance improves by 18% for the small data set 8
and the performance improves by 450% for the large data set 64k.

The base is with the libc from /system/lib64. The bionic libc
with this patch is in /data.

hikey:/data # export LD_LIBRARY_PATH=/system/lib64
hikey:/data # ./bionic-benchmarks --benchmark_filter='BM_string_memcmp*'
Run on (8 X 2.4 MHz CPU s)
Benchmark                                Time           CPU Iterations
----------------------------------------------------------------------
BM_string_memcmp/8                      30 ns         30 ns   22955680    251.07MB/s
BM_string_memcmp/64                     57 ns         57 ns   12349184   1076.99MB/s
BM_string_memcmp/512                   305 ns        305 ns    2297163   1.56496GB/s
BM_string_memcmp/1024                  571 ns        571 ns    1225211   1.66912GB/s
BM_string_memcmp/8k                   4307 ns       4306 ns     162562   1.77177GB/s
BM_string_memcmp/16k                  8676 ns       8675 ns      80676   1.75887GB/s
BM_string_memcmp/32k                 19233 ns      19230 ns      36394   1.58695GB/s
BM_string_memcmp/64k                 36986 ns      36984 ns      18952   1.65029GB/s
BM_string_memcmp_aligned/8             199 ns        199 ns    3519166   38.3336MB/s
BM_string_memcmp_aligned/64            386 ns        386 ns    1810734   158.073MB/s
BM_string_memcmp_aligned/512          1735 ns       1734 ns     403981   281.525MB/s
BM_string_memcmp_aligned/1024         3200 ns       3200 ns     218838   305.151MB/s
BM_string_memcmp_aligned/8k          25084 ns      25080 ns      28180   311.507MB/s
BM_string_memcmp_aligned/16k         51730 ns      51729 ns      13521   302.057MB/s
BM_string_memcmp_aligned/32k        103228 ns     103228 ns       6782   302.727MB/s
BM_string_memcmp_aligned/64k        207117 ns     207087 ns       3450   301.806MB/s
BM_string_memcmp_unaligned/8           339 ns        339 ns    2070998   22.5302MB/s
BM_string_memcmp_unaligned/64         1392 ns       1392 ns     502796   43.8454MB/s
BM_string_memcmp_unaligned/512        9194 ns       9194 ns      76133   53.1104MB/s
BM_string_memcmp_unaligned/1024      18325 ns      18323 ns      38206   53.2963MB/s
BM_string_memcmp_unaligned/8k       148579 ns     148574 ns       4713   52.5831MB/s
BM_string_memcmp_unaligned/16k      298169 ns     298120 ns       2344   52.4118MB/s
BM_string_memcmp_unaligned/32k      598813 ns     598797 ns       1085    52.188MB/s
BM_string_memcmp_unaligned/64k     1196079 ns    1196083 ns        540   52.2539MB/s

hikey:/data # export LD_LIBRARY_PATH=/data
hikey:/data # ./bionic-benchmarks --benchmark_filter='BM_string_memcmp*'
Run on (8 X 2.4 MHz CPU s)
Benchmark                                Time           CPU Iterations
----------------------------------------------------------------------
BM_string_memcmp/8                      30 ns         30 ns   23209918   252.802MB/s
BM_string_memcmp/64                     57 ns         57 ns   12348447   1076.95MB/s
BM_string_memcmp/512                   305 ns        305 ns    2296878   1.56471GB/s
BM_string_memcmp/1024                  572 ns        571 ns    1224426    1.6689GB/s
BM_string_memcmp/8k                   4309 ns       4308 ns     162491   1.77109GB/s
BM_string_memcmp/16k                  9348 ns       9345 ns      74894   1.63285GB/s
BM_string_memcmp/32k                 18329 ns      18322 ns      38249    1.6656GB/s
BM_string_memcmp/64k                 36992 ns      36981 ns      18952   1.65045GB/s
BM_string_memcmp_aligned/8             199 ns        199 ns    3513925   38.3162MB/s
BM_string_memcmp_aligned/64            386 ns        386 ns    1814038   158.192MB/s
BM_string_memcmp_aligned/512          1735 ns       1735 ns     402279   281.502MB/s
BM_string_memcmp_aligned/1024         3204 ns       3202 ns     218761   304.941MB/s
BM_string_memcmp_aligned/8k          25577 ns      25569 ns      27406   305.548MB/s
BM_string_memcmp_aligned/16k         52143 ns      52123 ns      13522   299.769MB/s
BM_string_memcmp_aligned/32k        105169 ns     105127 ns       6637    297.26MB/s
BM_string_memcmp_aligned/64k        206508 ns     206383 ns       3417   302.835MB/s
BM_string_memcmp_unaligned/8           282 ns        282 ns    2482953    27.062MB/s
BM_string_memcmp_unaligned/64          542 ns        541 ns    1298317    112.77MB/s
BM_string_memcmp_unaligned/512        2152 ns       2152 ns     325267   226.915MB/s
BM_string_memcmp_unaligned/1024       4025 ns       4025 ns     173904   242.622MB/s
BM_string_memcmp_unaligned/8k        32276 ns      32271 ns      21818    242.09MB/s
BM_string_memcmp_unaligned/16k       65970 ns      65970 ns      10554   236.851MB/s
BM_string_memcmp_unaligned/32k      131241 ns     131242 ns       5129    238.11MB/s
BM_string_memcmp_unaligned/64k      266159 ns     266160 ns       2661   234.821MB/s
2017-06-26 10:22:40 +02:00
Prakhar Bahuguna 21ff2cf930 Fix minor issues in memchr NEON implementation 2017-06-07 12:16:15 +02:00
Sebastian Huber 2693c1db69 Move ARM access.c from machine to sys
The implementation of the POSIX access() function is nothing machine
specific like memcpy(), etc.  Move it back to the system domain.  This
avoids problems due to the include search order of the Newlib/GCC build
which picks up machine includes before system includes.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2017-05-25 12:34:53 -04:00
Prakhar Bahuguna c47c9bdc1b Optimise memchr for NEON-enabled processors 2017-04-06 18:19:20 +02:00
Catherine Moore 571c69656a Use .syntax unified instead of .syntax divided. 2017-03-30 17:18:12 +02:00
Kyrill Tkachov 52a6da816f arm: Fix addressing in optpld macro
In patch b219285f87 you have a syntax
error in the PLD instruction.  The syntax for the pld argument should be
in square brackets as it's a memory address like so: pld [r1].  With
your patch the newlib build fails for armv7-a targets.  This patch fixes
the build failures.

Tested by making sure the newlib build completes successfully.

2016-01-26  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * libc/machine/arm/strcpy.c (strcpy): Fix PLD assembly syntax.
    * libc/machine/arm/strlen-stub.c (strlen): Likewise.
2017-01-26 16:29:36 +01:00
Pat Pannuto 3ebc26958e arm: Remove RETURN macro
LTO can re-order top-level assembly blocks, which can cause this
macro definition to appear after its use (or not at all), causing
compilation failures. On modern toolchains (armv4t+), assembly
should write `bx lr` in all cases, and linkers will transparently
convert them to `mov pc, lr`, allowing us to simply remove the
macro.
  (source: https://groups.google.com/forum/#!topic/comp.sys.arm/3l7fVGX-Wug
   and verified empirically)

For the armv4.S file, preserve this macro to maximize backwards
compatibility.
2017-01-25 13:32:09 +01:00
Pat Pannuto b219285f87 arm: Remove optpld macro
LTO can re-order top-level assembly blocks, which can cause this
macro definition to appear after its use (or not at all), causing
compilation failures. As the macro has very few uses, simply removing
it by inlining is a simple fix.

n.b. one of the macro invocations in strlen-stub.c was already
guarded by the relevant #define, so it is simply converted directly
to a pld
2017-01-25 13:32:09 +01:00
Pat Pannuto e7332409cc Remove unneeded references to arm_asm.h
This should result in no functional changes, it simply removes references
to arm_asm.h that did not use anything from that file.
2017-01-25 13:32:09 +01:00
Jeff Johnston 61f181d6b8 Bump release to 2.5.0 for yearly snapshot. 2016-12-22 21:33:54 -05:00
Julian Brown bc4f996f56 Big-endian fix for memcpy-armv7m.S
In the case of memcpy-armv7m.S being built for a big-endian multilib
(including armv7 without a specific profile), realignment code made
assumptions about the byte ordering being little-endian.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2016-12-12 11:23:45 +01:00
Anton Kolesov 668033eb9f arc: Fix strcmp for big endian without barrel shifter
strcmp.S contained invalid guard for code that used barrel-shifter optional
instruction - it was checking for !ARC601 instead of whether barrel shifter
is present. While it is true that ARC601 doesn't have barrel shifter, so
does some other ARC EM configurations.

2016-07-21  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* libc/machine/arc/strcmp.S: Fix big endian without barrel shifter.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
2016-08-11 10:59:54 +02:00
Claudiu Zissulescu 7b1080d9aa arc: Use prefetch instead of prealloc.
Prealloc instruction may not be present in all HS variants. Hence, use
prefetch instead of prealloc.

newlib/
2016-04-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* libc/machine/arc/memset-archs.S: Use prefetch.
2016-08-11 10:59:53 +02:00
Claudiu Zissulescu 67c5af5b85 arc: Use unaligned loads/stores for memcopy.
newlib/
2016-04-26  Claudiu Zissulescu  <claziss@synopsys.com>

	* libc/machine/arc/memcpy-archs.S: Add and enable memcpy using
	unaligned loads/stores.
2016-08-11 10:59:53 +02:00
Jon Turney d7e47a557e Regenerate newlib Makefiles 2016-07-04 17:13:55 +01:00
Jon Turney 0b4cbd2fb8 Make newlib manpages (v3)
Add makedocbook, a tool to process makedoc markup and output DocBook XML
refentries.

Process all the source files which are processed with makedoc with
makedocbook as well

Add chapter-texi2docbook, a tool to automatically generate DocBook XML
chapter files from the chapter .texi files.  For generating man pages all we
care about is the content of the refentries, so all this needs to do is
convert the @include of the makedoc generated .def files to xi:include of
the makedocbook generated .xml files.

Add skeleton Docbook XML book files, lib[cm].in.xml which include these
generated chapters, which in turn include the generated files containing
refentries, which is processed with xsltproc to generate the lib[cm].xml

Add new make targets to generate and install man pages from lib[cm].xml
2016-07-04 14:17:10 +01:00
Jon Turney f145c2e261 Revert "Make newlib manpages via DocBook XML (v3)"
This reverts commit 041ea41068.
2016-06-25 17:07:43 +01:00
Jon Turney 041ea41068 Make newlib manpages via DocBook XML (v3)
Add makedocbook, a tool to process makedoc markup and output DocBook XML
refentries.

Process all the source files which are processed with makedoc with
makedocbook as well

Add chapter-texi2docbook, a tool to automatically generate DocBook XML
chapter files from the chapter .texi files.  For generating man pages all we
care about is the content of the refentries, so all this needs to do is
convert the @include of the makedoc generated .def files to xi:include of
the makedocbook generated .xml files.

Add skeleton Docbook XML book files, lib[cm].in.xml which include these
generated chapters, which in turn include the generated files containing
refentries, which is processed with xsltproc to generate the lib[cm].xml

Add new make targets to generate and install man pages from lib[cm].xml
2016-06-25 17:04:15 +01:00
Wilco Dijkstra e7b1ee2ea6 Add rawmemchr
Marcus Shawcroft wrote:
> This patch appears to have been munged by the mail system, can you
> repost as an attachment please.

Sure, I've attached the patch.

Wilco

Add a simple rawmemchr implementation. Use strlen for rawmemchr(s, '\0') as it is the
fastest way to search for '\0', and use memchr with an infinite size for other cases.
This is 3x faster for large sizes.

ChangeLog:
2016-04-22  Wilco Dijkstra  <wdijkstr@arm.com>

        * newlib/libc/machine/aarch64/Makefile.in: Add rawmemchr.S and
        rawmemchr-stub.c.
        * newlib/libc/machine/aarch64/Makefile.am: Likewise.
        * newlib/libc/machine/aarch64/rawmemchr.S (rawmemchr): Add rawmemchr.
        * newlib/libc/machine/aarch64/rawmemchr-stub.c (rawmemchr): Likewise.
2016-05-20 10:47:02 +02:00
Jeff Johnston 5c02bcc086 Fix strlen using Thumb-2 with -Os -marm
2016-04-18  Thomas Preud'homme  <thomas.preudhomme@arm.com>

        * libc/machine/arm/strlen-stub.c: Check capabilities of architecture
        to decide which Thumb implementation to use and fall back to C
        implementation for architecture not supporting Thumb mode.
        * libc/machine/arm/strlen.S: Likewise.
2016-05-11 17:18:48 -04:00
Sebastian Huber 76a2110b47 BSD compatibility for <machine/endian.h>
Introduce <machine/_endian.h> to let target based customization of
<machine/endian.h> via

 * _LITTLE_ENDIAN,
 * _BIG_ENDIAN,
 * _PDP_ENDIAN, and
 * _BYTE_ORDER.

defines.  Add definitions expected by FreeBSD to
<machine/endian.h> like

 * _QUAD_HIGHWORD,
 * _QUAD_LOWWORD,
 * __bswap16(),
 * __bswap32(),
 * __bswap64(),
 * __htonl(),
 * __htons(),
 * __ntohl(), and
 * __ntohs().

Also, if __BSD_VISIBLE

 * LITTLE_ENDIAN,
 * BIG_ENDIAN,
 * PDP_ENDIAN, and
 * BYTE_ORDER.

Targets that define __machine_host_to_from_network_defined in
<machine/_endian.h> must provide their own implementation of

 * __htonl(),
 * __htons(),
 * __ntohl(), and
 * __ntohs(),

otherwise a default implementation is provided by <machine/endian.h>.
In case of GCC defines to builtins are used.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2016-04-19 16:36:51 +02:00
Sebastian Huber 8a5af1a184 Use __machine_*_t_defined for internal types
Newlib defines defaults for internal types via <sys/_types.h> and uses
<machine/_types.h> to let targets define their own type if necessary.

Previously for example

	#ifndef __dev_t_defined
	typedef short __dev_t;
	#endif

However, the __*_t_defined pattern conflicts with the glibc type guard
pattern for user types, e.g. dev_t in this example.  Introduce a
__machine_*_t_defined pattern for internal types (defined by
<machine/_types.h>, used by <sys/_types.h>).  For example

	#ifndef __machine_dev_t_defined
	typedef short __dev_t;
	#endif

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2016-04-15 14:51:39 +02:00
Igor Venevtsev 5d3ad3b123 Add Intel MCU target
Intel MCU System V ABI are incompartible with i386 System V ABI:
    o Minimum instruction set is Intel Pentium ISA minus x87 instructions
    o No x87 or vector registers
    o First three args are passed in %eax, %edx and %ecx
    o Full specification available here:
      https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf

newlib/
    * configure.host: Add new ix86-*-elfiamcu target

newlib/libc/include/
    * setjmp.h: Change _JBLEN for Intel MCU target

newlib/libc/machine/i386/
    * memchr.S:  (memchr)  Target-specific size-optimized version
    * memcmp.S:  (memcmp)  Likewise
    * memcpy.S:  (memcpy)  Likewise
    * memmove.S: (memmove) Likewise
    * memset.S:  (memset)  Likewise
    * setjmp.S:  (setjmp)  Likewise
    * strchr.S:  (strchr)  Likewise
    * strlen.S:  (strlen)  Likewise

newlib/libc/stdlib/
    * srtold.c:  (__flt_rounds) Disable for Intel MCU
2016-04-04 16:32:07 +02:00
Jeff Johnston fbc4a0827b Bump up newlib version to 2.4.0 due to feature test refactoring 2016-03-29 17:33:42 -04:00
Joel Sherrill ecf453f963 Add simple versions of random() and srandom()
Prototypes also added for initstate() and setstate() but they
were not implemented in the shared newlib code.

	* newlib/libc/include/cygwin/stdlib.h: Prototypes added.
	* winsup/cygwin/include/cygwin/stdlib.h: Prototypes removed.
	* newlib/libc/stdlib/random.c: New file.
	* newlib/libc/machine/epiphany/machine/stdlib.h: Removed
	* newlib/libc/stdlib/Makefile.am: Added random.c.
	* newlib/libc/stdlib/stdlib.tex: Added random.def.
	* newlib/libc/stdlib/Makefile.in: Regenerated.
2016-03-28 22:39:50 -05:00
Joel Sherrill 13707ae933 epiphany/machine/stdlib.h: Disable epiphany unique random wrappers for RTEMS 2016-03-22 09:47:00 -05:00
Corinna Vinschen b9217601f8 Enable HW interrupt setup on x86/x86_64 systems by default
* configure.host: Define _I386MACH_DISABLE_HW_INTERRUPTS on rdos.
	Remove setting _I386MACH_ALLOW_HW_INTERRUPTS anywhere else.
	* libc/machine/i386/i386mach.h: Replace test for
	_I386MACH_ALLOW_HW_INTERRUPTS with test for
	!_I386MACH_DISABLE_HW_INTERRUPTS.
	* libc/machine/x86_64/x86_64mach.h: Ditto.
	* libc/sys/linux/machine/i386/i386mach.h: Ditto.
	* libm/machine/i386/i386mach.h: Ditto.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2016-02-26 18:52:46 +01:00
Steve Ellcey 4792146a0f Fix memcpy bug that reads past end of buffer.
* libc/machine/mips/memcpy.S (memcpy): Fix read past end of
	input.
2016-01-28 14:08:35 -08:00
Thomas Preud'homme 69f4c40291 Make macro checks ARMv8-M baseline proof
libgloss:

        * arm/Makefile.in: Add newlib/libc/machine/arm to the include path if
        newlib is present.
        * arm/arm.h: Include acle-compat.h.
        (THUMB_V7_V6M): Rename to ...
        (PREFER_THUMB): This.  Use ACLE macros __ARM_ARCH_ISA_ARM instead of
        __ARM_ARCH_6M__ to decide whether to define it.
        (THUMB1_ONLY): Define for Thumb-1 only targets.
        (THUMB_V7M_V6M): Rename to ...
        (THUMB_VXM): This.  Defined based on __ARM_ARCH_ISA_ARM, excluding
        ARMv7.
        * arm/crt0.S: Use THUMB1_ONLY rather than __ARM_ARCH_6M__,
        !__ARM_ARCH_ISA_ARM rather than THUMB_V7M_V6M for fp enabling, and
        PREFER_THUMB rather than THUMB_V7_V6M.  Rename other occurences of
        THUMB_V7M_V6M to THUMB_VXM.
        * arm/linux-crt0.c: Likewise.
        * arm/redboot-crt0.S: Likewise.
        * arm/swi.h: Likewise.
        * arm/trap.S: Likewise.

newlib:

        * libc/machine/arm/memcpy-stub.c: Use ACLE macros __ARM_ARCH_ISA_THUMB
        and __ARM_ARCH_ISA_ARM to check for Thumb-2 only targets rather than
        __ARM_ARCH and __ARM_ARCH_PROFILE.
        * libc/machine/arm/memcpy.S: Likewise.
        * libc/machine/arm/setjmp.S: Likewise for Thumb-1 only target and
        include acle-compat.h.
        * libc/machine/arm/strcmp.S: Likewise for Thumb-1 and Thumb-2 only
        target and include acle-compat.h.
        * libc/sys/arm/arm.h: Include acle-compat.h.
        (THUMB_V7_V6M): Rename to ...
        (PREFER_THUMB): This.  Use ACLE macro __ARM_ARCH_ISA_ARM instead of
        __ARM_ARCH_6M__ to decide whether to define it.
        (THUMB1_ONLY): Define for Thumb-1 only targets.
        (THUMB_V7M_V6M): Rename to ...
        (THUMB_VXM): This.  Defined based on __ARM_ARCH_ISA_ARM, excluding
        ARMv7.
        * libc/sys/arm/crt0.S: Use PREFER_THUMB rather than THUMB_V7_V6M and
        rename THUMB_V7M_V6M into THUMB_VXM.
        * libc/sys/arm/swi.h: Likewise.
2016-01-28 11:26:37 +01:00
Jeff Johnston ad7b3cde9c Regenerate files for newlib 2.3.0. 2015-12-21 21:32:11 -05:00
Anton Kolesov 06537f05d4 ARC: Use new definitions for optional ARC CPU features
GCC for ARC has been updated to provide consistent naming of preprocessor
definitions for different optional architecture features:

    * __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for
      -mbarrel-shifter
    * __ARC_LL64__ instead of __LL64__ for -mll64
    * __ARCEM__ instead of __EM__ for -mcpu=arcem
    * __ARCHS__ instead of __HS__ for -mcpu=archs
    * etc (not used in newlib)

This patch updates assembly routines for ARC to use new definitions instead
of a deprecated ones. To ensure compatibility with older compiler new
definitions are also defined in asm.h if needed, based on deprecated
preprocessor definitions.

*** newlib/ChangeLog ***
2015-12-15  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* libc/machine/arc/asm.h: Define new GCC definition for old compiler.
	* libc/machine/arc/memcmp-bs-norm.S: Use new GCC defines to detect
	  processor features.
	* libc/machine/arc/memcmp.S: Likewise.
	* libc/machine/arc/memcpy-archs.S: Likewise.
	* libc/machine/arc/memcpy-bs.S: Likewise.
	* libc/machine/arc/memcpy.S: Likewise.
	* libc/machine/arc/memset-archs.S: Likewise.
	* libc/machine/arc/memset-bs.S: Likewise.
	* libc/machine/arc/memset.S: Likewise.
	* libc/machine/arc/setjmp.S: Likewise.
	* libc/machine/arc/strchr-bs-norm.S: Likewise.
	* libc/machine/arc/strchr-bs.S: Likewise.
	* libc/machine/arc/strchr.S: Likewise.
	* libc/machine/arc/strcmp-archs.S: Likewise.
	* libc/machine/arc/strcmp.S: Likewise.
	* libc/machine/arc/strcpy-bs-arc600.S: Likewise.
	* libc/machine/arc/strcpy-bs.S: Likewise.
	* libc/machine/arc/strcpy.S: Likewise.
	* libc/machine/arc/strlen-bs-norm.S: Likewise.
	* libc/machine/arc/strlen-bs.S: Likewise.
	* libc/machine/arc/strlen.S: Likewise.
	* libc/machine/arc/strncpy-bs.S: Likewise.
	* libc/machine/arc/strncpy.S: Likewise.

Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
2015-12-17 22:48:16 +01:00
Marcus Shawcroft 8e62ab4ccc [ARM] Adjust strcmp-armv7.S selection logic.
Reformulate the strcmp-armv7.S selection logic around the architecture
features required by the implementation code rather (some) version of
the architecture that expose those features.
2015-11-23 15:22:26 +00:00
Marcus Shawcroft dc38827570 [ARM] Factor out the thumb2 -Os implementation.
The patch moves the inline ASM thumb2 -Os implementation out into its
own .S file.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

      Architectures:
        armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
        armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
        armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

      ISAs:
        thumb arm

      Optimization Levels:
        Os O2

      Excluding:
        armv6s-m -mthumb
        armv6-m -mthumb

        armv6zk -mthumb
        armv6z -mthumb
        armv6k -mthumb
        armv6j -mthumb
2015-11-23 15:21:47 +00:00
Corinna Vinschen fbace81684 Import correctly working strtold from David M. Gay.
* libc/stdlib/Makefile.am (GENERAL_SOURCES): Add strtodg.c and
	strtorx.c.
	* libc/stdlib/Makefile.in: Regenerate.
	* libc/stdlib/strtodg.c: New file implementing generic string to long
	double conversion.
	* libc/stdlib/strtorx.c: New file, implementing IEEE format string to
	long double conversion.
	* libc/stdlib/mprec.h (_strtodg_r): Declare.
	(_strtorx_r): Declare.
	* libc/stdlib/gdtoa.h (__UShort): Define.
	* libc/stdlib/strtold.c (__flt_rounds): Define for i386 and x86_64
	target.
	(FLT_ROUNDS): Define, as 0 on platforms missing a __flt_rounds
	function.
	(_strtold_r): Converted from strtold.  Call _strtorx_r on targets
	supporting distinct long doubles.
	(strtold): Just call _strtold_r.
	* libc/include/stdlib.h (_strtold_r): Declare.
	* libc/stdlib/ldtoa.c (_strtold): Comment out.  Explain why.
	* libc/stdio/vfscanf.c (__SVFSCANF_R): Call _strtold_r instead of
	_strtold.
	* libc/machine/powerpc/vfscanf.c (__svfscanf_r): Ditto.

	* common.din (strtold): Drop redirection to _strtold.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2015-11-20 18:14:58 +01:00
Marcus Shawcroft 9959058932 [ARM] Factor out the thumb1 -Os implementation.
The patch moves the inline ASM thumb1 -O2 implementation out into its
own .S file.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

      Architectures:
        armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
        armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
        armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

      ISAs:
        thumb arm

      Optimization Levels:
        Os O2

      Excluding:
        armv6s-m -mthumb
        armv6-m -mthumb

        armv6zk -mthumb
        armv6z -mthumb
        armv6k -mthumb
        armv6j -mthumb
2015-11-13 11:54:28 +00:00
Marcus Shawcroft bcd5e8e3f9 [ARM] Adding strlen.S
The patch adds strlen.S to contain the complementary preprocessor
logic to strlen-stub.c intended to provide #inclusion of alternative
.S implementations.

Initially we just include the existing strlen-armv7.S implementation.

We rewrite _ISA_ARMV7 in both strlen.S and strlen-stub.c to use the
underlying existing underlying defintion from arm_asm.h in order to
avoide including that file, this is in effect the first step towards a
move to ACLE predefines only.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

      Architectures:
        armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
        armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
        armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

      ISAs:
        thumb arm

      Optimization Levels:
        Os O2

      Excluding:
        armv6s-m -mthumb
        armv6-m -mthumb

        armv6zk -mthumb
        armv6z -mthumb
        armv6k -mthumb
        armv6j -mthumb
2015-11-13 11:54:28 +00:00
Marcus Shawcroft 42de6f5085 [ARM] Rename strlen to strlen-stub.c
In order to maintain consistency both within machine/arm and between
machine/arm and machine/aarch64, rename the 'c' stub to -stub.c.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

      Architectures:
        armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
        armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
        armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

      ISAs:
        thumb arm

      Optimization Levels:
       Os O2

      Excluding:
        armv6s-m -mthumb
        armv6-m -mthumb

        armv6zk -mthumb
        armv6z -mthumb
        armv6k -mthumb
        armv6j -mthumb
2015-11-13 11:54:23 +00:00
Marcus Shawcroft 2c8e31d654 [ARM] Reorganize strlen selection.
Remove automake and autoconf selection of strchr implementation in
favour of conditional compilation in strlen.c.
2015-11-13 11:52:01 +00:00
Marcus Shawcroft 52f5864096 [ARM] Refactor strlen.c #if nesting.
This patch flattens the condition code selection used in strlen in an
attempt to make the guarding condition for each alternative
implementation clearer and to structure the logic in a manner that
makes it easier to maintain complementary logic between the
alternative 'C' and assembler implementations.

Tested by building newlib and comparing libc.a binaries before and
after for all permutations of:

  Architectures:
    armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k
    armv6z armv6kz armv6t2 armv6-m armv6s-m armv7 armv7-a
    armv7ve armv7-r armv7-m armv7e-m armv8-a iwmmxt iwmmxt2

  ISAs:
    thumb arm

  Optimization Levels:
    Os O2

  Excluding:
    armv6s-m -mthumb
    armv6-m -mthumb

    armv6zk -mthumb
    armv6z -mthumb
    armv6k -mthumb
    armv6j -mthumb
2015-11-13 11:51:31 +00:00
Anton Kolesov c0a99f0293 Add support for ARC to newlib
newlib/ChangeLog:
2015-11-12  Anton Kolesov  <Anton.Kolesov@synopsys.com>

	* configure.host: Add ARC support.
	* libc/include/machine/setjmp.h: Likewise.
	* libc/machine/configure: Likewise.
	* libc/machine/configure.in: Likewise.
	* libc/machine/arc/Makefile.am: Likewise.
	* libc/machine/arc/Makefile.in: Likewise.
	* libc/machine/arc/aclocal.m4: Likewise.
	* libc/machine/arc/asm.h: Likewise.
	* libc/machine/arc/configure: Likewise.
	* libc/machine/arc/configure.in: Likewise.
	* libc/machine/arc/memcmp-bs-norm.S: Likewise.
	* libc/machine/arc/memcmp-stub.c: Likewise.
	* libc/machine/arc/memcmp.S: Likewise.
	* libc/machine/arc/memcpy-archs.S: Likewise.
	* libc/machine/arc/memcpy-bs.S: Likewise.
	* libc/machine/arc/memcpy-stub.c: Likewise.
	* libc/machine/arc/memcpy.S: Likewise.
	* libc/machine/arc/memset-archs.S: Likewise.
	* libc/machine/arc/memset-bs.S: Likewise.
	* libc/machine/arc/memset-stub.c: Likewise.
	* libc/machine/arc/memset.S: Likewise.
	* libc/machine/arc/setjmp.S: Likewise.
	* libc/machine/arc/strchr-bs-norm.S: Likewise.
	* libc/machine/arc/strchr-bs.S: Likewise.
	* libc/machine/arc/strchr-stub.c: Likewise.
	* libc/machine/arc/strchr.S: Likewise.
	* libc/machine/arc/strcmp-archs.S: Likewise.
	* libc/machine/arc/strcmp-stub.c: Likewise.
	* libc/machine/arc/strcmp.S: Likewise.
	* libc/machine/arc/strcpy-bs-arc600.S: Likewise.
	* libc/machine/arc/strcpy-bs.S: Likewise.
	* libc/machine/arc/strcpy-stub.c: Likewise.
	* libc/machine/arc/strcpy.S: Likewise.
	* libc/machine/arc/strlen-bs-norm.S: Likewise.
	* libc/machine/arc/strlen-bs.S: Likewise.
	* libc/machine/arc/strlen-stub.c: Likewise.
	* libc/machine/arc/strlen.S: Likewise.
	* libc/machine/arc/strncpy-bs.S: Likewise.
	* libc/machine/arc/strncpy-stub.c: Likewise.
	* libc/machine/arc/strncpy.S: Likewise.
2015-11-12 14:14:17 +01:00
Wilco Dijkstra 3c8636acf6 AArch64: Tune memcpy
* newlib/libc/machine/aarch64/memcpy.S (memcpy):
 	Further tuning for performance.
2015-11-12 13:38:39 +01:00
Joseph Myers e6459123e4 Avoid .eh_frame in ARM newlib.
ARM newlib has various strcmp implementations that use .cfi_*
directives to generate unwind information.

The effect of this is that the generated objects contain .eh_frame
sections.  However, ARM uses its own unwind info format, not
.eh_frame, which is generated by ARM-specific directives, not .cfi_*.
The .eh_frame sections are useless, but also not removed by strip and
may be loaded into memory at runtime.

This patch fixes this by using .cfi_sections .debug_frame (as in
glibc) so that the directives generate .debug_frame instead.
.debug_frame is useful for the debugger, can be removed by strip, and
is not loaded into memory at runtime.

	* libc/machine/arm/strcmp-arm-tiny.S: Use .cfi_sections
	.debug_frame.
	* libc/machine/arm/strcmp-armv4.S: Likewise.
	* libc/machine/arm/strcmp-armv4t.S: Likewise.
	* libc/machine/arm/strcmp-armv6.S: Likewise.
	* libc/machine/arm/strcmp-armv6m.S: Likewise.
	* libc/machine/arm/strcmp-armv7.S: Likewise.
	* libc/machine/arm/strcmp-armv7m.S: Likewise.
2015-11-12 12:09:24 +00:00
Marcus Shawcroft d18f1fc8a3 Reorganize memchr selection.
The patch cleans up the auto configury mechanism used to select
different implementations of memchr for various architecture versions.

The approach here is to remove the selection of memchr within automake
and instead use complimentary logic in memchr-stub.c and memchr.S to
choose between the gerneric memchr.c implementation or one of the
architecture specific implementations.

This patch also changes the selection criteria inline with the
previous proposal here:

https://sourceware.org/ml/newlib/2015/msg00752.html

but using the ACLE predefines.

Regressed for armv7-a armv5 armv8-a, correct selection of memcpy
implementation by manual inspection of a test program built for these
three architectures.
2015-11-06 16:11:32 +00:00
Marcus Shawcroft 72be1dead4 Reorganize memcpy selection.
This patch cleans up the auto configury mechanism used to select
different implementations of memcpy for various architecture versions.

The approach here is to remove the selection of memcpy within automake
and instead use complimentary logic in memcpy-stub.c and memcpy.S to
choose between the generic memcpy.c implemenation or one of the
architecture specific memcpy*.S implemenations.

Regressed for armv7-a armv5 armv8-a, correct selection of memcpy
implementation by manual inspection of a test program built for these
three architectures.

This revised patch flips the remaining preprocessor logic in
memcpy-stub.c to use ACLE defines as requested in the previous review
and removes the now disused HAVE_ARMV7A and HAVE_ARMV8A configure.in
support.
2015-11-06 15:40:31 +00:00
Marcus Shawcroft 0a4019eed2 [ARM] Select appropriate memcpy implementation for ARMv8-a.
The newlib configury logic that detects architecture version and
chooses an appropriate memcpy implementation does not consider
ARMv8-a.

This patch adds configury logic to detect ARMv8-a along with the
associated changes in Makefile.am and memcpy.
2015-11-03 11:04:55 +00:00
Jeff Johnston 0631279394 Move duplicated documentation rules to Makefile.shared
- Also, harmonize libm to use CHEWOUT_FILES like libc, rather than chobj.
  Update documentation appropriately.

        * HOWTO: Update.
        * Makefile.shared: Move documentation rules to here...
        * libc/argz/Makefile.am: ... from here ...
        * libc/ctype/Makefile.am: ... and here.
        * libc/errno/Makefile.am: Ditto.
        * libc/iconv/Makefile.am: Ditto.
        * libc/iconv/ccs/Makefile.am : Ditto.
        * libc/iconv/ces/Makefile.am: Ditto.
        * libc/iconv/lib/Makefile.am: Ditto.
        * libc/locale/Makefile.am: Ditto.
        * libc/misc/Makefile.am: Ditto.
        * libc/posix/Makefile.am: Ditto.
        * libc/reent/Makefile.am: Ditto.
        * libc/search/Makefile.am: Ditto.
        * libc/stdio/Makefile.am: Ditto.
        * libc/stdio64/Makefile.am: Ditto.
        * libc/stdlib/Makefile.am : Ditto.
        * libc/string/Makefile.am: Ditto.
        * libc/syscalls/Makefile.am: Ditto.
        * libc/time/Makefile.am : Ditto.
        * libc/unix/Makefile.am: Ditto.
        * libc/xdr/Makefile.am: Ditto.
        * libm/common/Makefile.am: Ditto.
        * libm/complex/Makefile.am: Ditto.
        * libm/math/Makefile.am: Ditto.
        * libm/mathfp/Makefile.am: Ditto.
2015-11-02 18:02:39 -05:00
Steve Ellcey 5045532322 Improve performance of MIPS memcpy.
* libc/machine/mips/memcpy.S (memcpy): Add word copies for small
	aligned data.
2015-11-02 13:30:19 -08:00
Jeff Johnston 948b5f0043 Add support for ft32 to newlib. 2015-09-04 14:37:37 -04:00
Hans-Peter Nilsson 82d7069a5e libc/machine/cris/sys/signal.h (kill): Declare. 2015-09-03 01:59:43 +02:00
Corinna Vinschen e6d9af11f1 strlen-armv7.S: Fix preprocessor check
Hi!

I've got the situation, that the function strlen() occurs twice in libc.a
(building newlib for ARM-V7a and Size-Optimized).

In newlib/libc/machine/arm/strlen.c there are the pre-processor stetements ...
#if defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
  (defined (__thumb__) && !defined (__thumb2__))
/*...*/
#else

#if !(defined(_ISA_ARM_7) || defined(__ARM_ARCH_6T2__))
/*...*/
#endif

and in newlib/libc/machine/arm/strlen-armv7.S the "exclude" begins with

/* NOTE: This ifdef MUST match the ones in arm/strlen.c
   We fallback to the one in arm/strlen.c for size optimised or
   for older architectures. */
#if defined(_ISA_ARM_7) || defined(__ARM_ARCH_6T2__) && \
    !(defined (__OPTIMIZE_SIZE__) || defined (PREFER_SIZE_OVER_SPEED) || \
      (defined (__thumb__) && !defined (__thumb2__)))

But this is not completely contrary to arm/strlen.c (see above)!

To fix the logical statement in arm/strlen-armv7.S there are parentheses needed

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2015-08-27 12:55:22 +02:00
Andre Vieira a732159809 Use machine header file for endianness configuration.
newlib/ChangeLog:
2015-07-28  Andre Vieira  <andre.simoesdiasvieira@arm.com>

   * libc/sys/arm/sys/param.h (BIG_ENDIAN, LITTLE_ENDIAN): Moved
   to machine/endian.h.
   * libc/machine/arm/machine/param.h (BYTE_ORDER): Idem.
   * libc/machine/arm/machine/endian.h: New.

From ca6efccda91bc6b620b7d96a466b0f1e2f02cfeb Mon Sep 17 00:00:00 2001
From: Andre Simoes Dias Vieira <andsim01@arm.com>
Date: Tue, 28 Jul 2015 12:16:20 +0100
Subject: [PATCH 2/2] Move endianness configuration to machine/endian.h
2015-08-20 10:52:34 +02:00
Wilco Dijkstra 127c38bd44 [AArch64] Rewrite optimized memset.
This is an optimized memset for AArch64.  Memset is split into 4 main
cases: small sets of up to 16 bytes, medium of 16..96 bytes which are
fully unrolled.  Large memsets of more than 96 bytes align the
destination and use an unrolled loop processing 64 bytes per
iteration.  Memsets of zero of more than 256 use the dc zva
instruction, and there are faster versions for the common ZVA sizes 64
or 128.  STP of Q registers is used to reduce codesize without loss of
performance.
2015-07-30 12:51:34 +01:00
Marcus Shawcroft c7806ef76a [AArch64] Reverting recent optimized memset(). 2015-07-15 13:34:58 +01:00
Wilco Dijkstra 3263f90ef7 [AArch64] Optimized memset.
This is an optimized memset for AArch64.  Memset is split into 4 main
cases: small sets of up to 16 bytes, medium of 16..96 bytes which are
fully unrolled.  Large memsets of more than 96 bytes align the
destination and use an unrolled loop processing 64 bytes per
iteration.  Memsets of zero of more than 256 use the dc zva
instruction, and there are faster versions for the common ZVA sizes 64
or 128.  STP of Q registers is used to reduce codesize without loss of
performance.
2015-07-13 13:17:16 +01:00
Wilco Dijkstra b295f6ba44 [AArch64] Optimized memcpy.
This is an optimized memcpy for AArch64.  Copies are split into 3 main
cases: small copies of up to 16 bytes, medium copies of 17..96 bytes
which are fully unrolled.  Large copies of more than 96 bytes align
the destination and use an unrolled loop processing 64 bytes per
iteration.  In order to share code with memmove, small and medium
copies read all data before writing, allowing any kind of overlap.  On
a random copy test memcpy is 40.8% faster on A57 and 28.4% on A53.
2015-07-13 13:09:02 +01:00
Wilco Dijkstra 9503c7f275 [AArch64] Optimized memmove.
This is an optimized memmove for AArch64.  All copies of up to 96
bytes and all backward copies are done by the new memcpy.  The only
remaining case is large forward copies which are done in the same way
as the memcpy loop, but copying from the end rather than the start.
2015-07-13 13:03:02 +01:00
Hale Wang 24e054c8c8 Update the assembler code to support old ARM architectures.
* libc/machine/arm/aeabi_memmove-arm.S (__aeabi_memmove): Update the
        assembler implementation.
        * libc/machine/arm/aeabi_memmove-thumb.S (__aeabi_memmove): Ditto.
        * libc/machine/arm/aeabi_memmove-thumb2.S (__aeabi_memmove): Ditto.
        * libc/machine/arm/aeabi_memset-arm.S (__aeabi_memset): Ditto.
        * libc/machine/arm/aeabi_memset-thumb.S (__aeabi_memset): Ditto.
        * libc/machine/arm/aeabi_memset-thumb2.S (__aeabi_memset): Ditto.

Signed-off-by: Corinna Vinschen <corinna@vinschen.de>
2015-06-01 12:49:37 +02:00
Nick Clifton cd0d459135 For the RX port, avoid using string instructions when __RX_DISALLOW_STRING_INSNS__ is defined.
* rx/crt0.S (_start): If string instructions are not allowed,
	avoid using SMOVF.

	* libc/machine/rx/memchr.S: Add non-string insn using version.
	* libc/machine/rx/memcpy.S: Likewise.
	* libc/machine/rx/memmove.S: Likewise.
	* libc/machine/rx/mempcpy.S: Likewise.
	* libc/machine/rx/strcat.S: Likewise.
	* libc/machine/rx/strcmp.S: Likewise.
	* libc/machine/rx/strcpy.S: Likewise.
	* libc/machine/rx/strlen.S: Likewise.
	* libc/machine/rx/strncat.S: Likewise.
	* libc/machine/rx/strncmp.S: Likewise.
	* libc/machine/rx/strncpy.S: Likewise.
2015-04-23 21:57:13 +02:00
Steve Ellcey bc860c9894 * libc/machine/mips/memset.S: Add support for mips32r6/mips64r6. 2015-03-03 19:49:00 +00:00
Steve Ellcey b8cd02f65a * libc/machine/mips/memcpy.S: Add support for mips32r6/mips64r6. 2015-03-03 17:46:27 +00:00
Steve Ellcey d2f9dbb3ee 2015-02-26 Steve Ellcey <sellcey@imgtec.com>
* libc/machine/mips/memcpy.S: Fix macro indentation and typos in
	comments.
2015-02-26 23:36:56 +00:00
Corinna Vinschen 72ba8b107a * libc/machine/arm/aeabi_memclr.c: New file to support
aeabi_memclr.
	* libc/machine/arm/aeabi_memset.c: New file to support
	aeabi_memset.
	* libc/machine/arm/aeabi_memset-soft.S: Ditto.
	* libc/machine/arm/aeabi_memset-arm.S: Ditto.
	* libc/machine/arm/aeabi_memset-thumb.S: Ditto.
	* libc/machine/arm/aeabi_memset-thumb2.S: Ditto.
	* libc/machine/arm/Makefile.am: Add dependencies.
	* libc/machine/arm/Makefile.in: Regenerated.
2015-02-17 09:26:54 +00:00
Corinna Vinschen 554f33c48d * libc/machine/arm/aeabi_memmove.c: New file to support
aeabi_memmove.
	* libc/machine/arm/aeabi_memmove-soft.S: Ditto.
	* libc/machine/arm/aeabi_memmove-arm.S: Ditto.
	* libc/machine/arm/aeabi_memmove-thumb.S: Ditto.
	* libc/machine/arm/aeabi_memmove-thumb2.S: Ditto.
	* libc/machine/arm/Makefile.am: Add dependencies.
	* libc/machine/arm/Makefile.in: Regenerated.
2015-02-17 09:06:51 +00:00
Nick Clifton b9e7cd9a84 * libc/include/complex.h (cabsl): Add prototype.
(cimagl): Add prototype.
	(creall): Add prototype.
	* libc/include/ieeefp.h: Include float.h.
	(EXT_EXPBITS, EXT_FRACHBITS, EXT_FRACLBITS)
	(EXT_EXP_INFNAN. EXT_EXP_BIAS, EXT_FRACBITS): Define.
	(struct ieee_ext, union ieee_ext_u): New types for long double
	support.
	* libc/include/math.h (finitel): Add prototype.
	(hypotl): Add prototype.
	(sqrtl): Add prototype.
	* libm/common/Makefile.am (lsrc): Add sl_finite.c.
	* libm/common/Makefile.in: Regenerate.
	* libm/common/fdlibm.h (__ieee754_hypotl): Add prototype.
	* libm/common/hypotl.c (hypotl): Add implementation for when long
	double is larger than double.
	* libm/common/sqrtl.c (sqrtl): Likewise.
	* libm/common/sl_finite.c: New file.  Adds implementation of the
	finitel function.
	* libm/complex/Makefile.am (lsrc): Define.
	(libcomplex_la_SOURCES): Add lsrc.
	(lib_a_SOURCES): Add lsrc.
	* libm/complex/Makefile.in: Regenerate.
	* libm/complex/cabs.c: Add documentation of cabsl function.
	* libm/complex/cimag.c: Add documentation of cimagl function.
	* libm/complex/creall.c: Add documentation of creall function.
	* libm/complex/cabsl.c: New file.  Adds implementation of the
	cabsl function.
	* libm/complex/cimagl.c: New file.  Adds implementation of the
	cimagl function.
	* libm/complex/creall.c: New file.  Adds implementation of the
	creall function.
	* libm/math/Makefile.am (lsrc): Define.
	(libmath_la_SOURCES): Add lsrc.
	(lib_a_SOURCES): Add lsrc.
	* libm/math/Makefile.in: Regenerate.
	* libm/math/el_hypot.c: New file.  Adds implementation of the
	__ieee754_hypotl function.
2015-02-06 16:14:04 +00:00
Corinna Vinschen 2ee3908b45 Complete action from 2001-12-18:
* libc/machine/i386/f_*: Remove duplicate files.
2015-01-23 10:16:00 +00:00
Eric Botcazou bf8f43ae8a * COPYING.LIBGLOSS: Add Controls and Data Services copyright.
* COPYING.NEWLIB: Likewise.
libgloss/
	* configure.in: Add Visium support.
	* configure: Regenerate.
	* visium/: New directory.
newlib/
	* configure.host: Add Visium support.
	* libc/machine/configure.in: Likewise.
	* libc/machine/configure: Regenerate.
	* libc/machine/visium/: New directory.
	* libc/include/machine/setjmp.h (_JBLEN): Define for Visium.
	* libc/include/machine/ieeefp.h (__IEEE_BIG_ENDIAN): Likewise.
	* libc/include/machine/time.h (_CLOCKS_PER_SEC_): Likewise.
2015-01-21 18:27:47 +00:00
Corinna Vinschen 086cd00d24 * libc/machine/aarch64/strlen.S (strlen): Improve performance. 2015-01-20 10:11:56 +00:00
Richard Earnshaw 6a35dbf342 * libc/machine/aarch64/strcpy.S (strcpy): Further performance
improvements.  Adjust to allow building as stpcpy.
	* libc/machine/aarch64/stpcpy.S: New file.
	* libc/machine/aarch64/stpcpy-stub.c: New file.
	* libc/machine/aarch64/Makefile.am (lib_a_SOURCES): Build stpcpy.
	* libc/machine/aarch64/Makefile.in: Regenerated.
2015-01-06 09:57:55 +00:00
Jeff Johnston 0615b4bb5f 2014-12-18 Jeff Johnston <jjohnstn@redhat.com>
* NEWS: Update with 2.2.0 info.
        * README: Ditto.
        * acinclude.m4: Change version number to 2.2.0.
        * libc/libc.texinfo: Ditto.
        * libm/libm.texinfo: Ditto.
        * configure: Regenerated.
        * Makefile.in: Regenerated.
        * doc/configure: Ditto.
        * libc/*/configure: Ditto.
        * libm/*/configure: Ditto.
        * libc/sys/linux/shared.ld: Add VERS_2.2
2014-12-18 20:30:11 +00:00
Richard Earnshaw 52edca9f86 * libc/machine/aarch64/strcpy.S: Improve handling of short strings. 2014-12-16 15:48:58 +00:00
Corinna Vinschen f5ce72dffc * newlib/libc/include/machine/setjmp.h: Add FPU support.
* newlib/libc/machine/nds32/setjmp.S: Add FPU support.
2014-12-15 13:32:17 +00:00
Jeff Johnston f58bc5991f 2014-12-12 Stefan Wallentowitz <stefan.wallentowitz@tum.de>
* configure.host: or1knd support, OpenRISC without delay slot
        * libc/include/machine/setjmp.h: Add or1knd
        * libc/machine/or1k/setjmp.S: Optional delay slot
2014-12-12 21:14:06 +00:00
Jeff Johnston 31cf15b180 2014-12-12 Stefan Wallentowitz <stefan.wallentowitz@tum.de>
* libc/machine/or1k/setjmp.S: Remove save/restore of r3-r8
2014-12-12 20:17:26 +00:00
Richard Earnshaw 8608e14a3b * libc/machine/aarch64/strchrnul.S (vrepmask): Use a call-clobbered
register.
2014-12-10 09:35:10 +00:00
Richard Earnshaw c53c2915a7 * libc/machine/aarch64/strrchr.S: New file.
* libc/machine/aarch64/strrchr-stub.c: New file.
	* libc/machine/aarch64/Makefile.am: Add them to build list.
	* libc/machine/aarch64/Makefile.in: Regenerated.
2014-12-08 15:21:42 +00:00