Commit Graph

53 Commits

Author SHA1 Message Date
Alan Modra 3aeffaadc7 update copyright dates 2005-03-03 11:58:10 +00:00
Jan Beulich b51b23bf82 gas/testsuite/
2005-02-09  Jan Beulich  <jbeulich@novell.com>

	* gas/i386/intelok.s: Remove comments disabling alternative forms of
	fbld, fbstp, and fldcw.
	* gas/i386/intelok.d: Expect two instances of fbld, fbstp, and fldcw.

include/opcode/
2005-02-09  Jan Beulich  <jbeulich@novell.com>

	PR gas/707
	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	fnstsw.
2005-02-09 08:05:43 +00:00
Jan Beulich c1ab3396dc gas/
2004-11-25 Jan Beulich <jbeulich@novell.com>

	* config/tc-i386.c (optimize_imm): Adjust immediates to only those
	permissible for the selected instruction suffix.
	(process_suffix): For DefaultSize instructions, suppressing the
	guessing of a 'q' suffix if the instruction doesn't support it is
	pointless, because only an 'l' suffix can be guessed in this place.

gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
	* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.

include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>

	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	to/from test registers are illegal in 64-bit mode. Add missing
	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	(previously one had to explicitly encode a rex64 prefix). Re-enable
	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2004-11-25 08:42:54 +00:00
Jan Beulich 4b8e88e31d gas/
2004-11-23 Jan Beulich <jbeulich@novell.com>

	* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
	indicate the MMX extensions added by both SSE and 3DNow!A.
	(Cpu3dnowA): Declare.
	(CpuUnknownFlags): Update.
	* config/tc-i386.c (cpu_sub_arch_name): Declare.
	(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
	neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
	3DNow!. Athlon additionally implies 3DNow!A. Several new
	entries (those starting with a dot are for sub-arch specification).
	(set_cpu_arch): Handle sub-arch specifications.
	(parse_insn): Distinguish between instructions not supported because
	of insufficient CPU features and because of 64-bit mode.
	* doc/c-i386.texi: Describe enhanced .arch directive.

include/opcode/
2004-11-23 Jan Beulich <jbeulich@novell.com>

	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	available only with SSE2. Change the MMX additions introduced by SSE
	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	instructions by their now designated identifier (since combining i686
	and 3DNow! does not really imply 3DNow!A).
2004-11-23 07:55:12 +00:00
H.J. Lu d356aef3c4 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Put back "movzb".
2004-11-05 23:14:30 +00:00
Jan Beulich 1fede1b1ba gas/
2004-11-04 Jan Beulich <jbeulich@novell.com>

	* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
	intel syntax and no register prefix, allow $ in symbol names when
	intel syntax.
	(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
	(intel_float_operand): Add fourth return value indicating math control
	operations. Make classification more precise.
	(md_assemble): Complain if memory operand of mov[sz]x has no size
	specified.
	(parse_insn): Translate word operands to floating point instructions
	operating on integers as well as control instructions to short ones
	as expected by AT&T syntax. Translate 'd' suffix to short one only for
	floating point instructions operating on non-integer operands.
	(match_template): Remove fldcw special case. Adjust q-suffix handling
	to permit it on fild/fistp/fisttp in AT&T mode.
	(process_suffix): Don't guess DefaultSize insns' suffix from
	stackop_size for certain floating point control instructions. Guess
	suffix for branch and [ls][gi]dt based on flag_code. Split error
	messages for Intel and AT&T syntax, and make the condition more strict
	for the former. Adjust suppressing of generation of operand size
	overrides.
	(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
	OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
	more error checking.
	* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
	SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.

gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
	* gas/i386/i386.exp: Execute new tests intelbad and intelok.
	* gas/i386/intelbad.[sl]: New test to check for various things not
	permitted in Intel mode.
	* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
	Adjust for change to segment register store.
	* gas/i386/intelok.[sd]: New test to check various Intel mode specific
	things get handled correctly.
	* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
	'high' and 'low' parts of an operand, which the parser previously
	accepted while neither telling that it's not supported nor that it
	ignored the remainder of the line following these supposed keywords.

include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>

	* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
	(indirEb): Remove.
	(Mp): Use f_mode rather than none at all.
	(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
	replaces what previously was x_mode; x_mode now means 128-bit SSE
	operands.
	(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
	mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
	pinsrw's second operand is Edqw.
	(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
	operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
	fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
	mode when an operand size override is present or always suffixing.
	More instructions will need to be added to this group.
	(putop): Handle new macro chars 'C' (short/long suffix selector),
	'I' (Intel mode override for following macro char), and 'J' (for
	adding the 'l' prefix to far branches in AT&T mode). When an
	alternative was specified in the template, honor macro character when
	specified for Intel mode.
	(OP_E): Handle new *_mode values. Correct pointer specifications for
	memory operands. Consolidate output of index register.
	(OP_G): Handle new *_mode values.
	(OP_I): Handle const_1_mode.
	(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
	respective opcode prefix bits have been consumed.
	(OP_EM, OP_EX): Provide some default handling for generating pointer
	specifications.
2004-11-04 09:16:08 +00:00
Michal Ludvig f048a4a16f Added new instructions for next version of VIA PadLock core. 2004-07-30 12:36:37 +00:00
H.J. Lu 7b313f6fc8 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2004-07-22 19:10:49 +00:00
Nick Clifton 9aec2c3c19 For DefaultSize instructions, don't guess a 'q' suffix if the instruction
doesn't support it.
2004-07-21 18:18:04 +00:00
Alan Modra 98767b49a0 include/opcode/
* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

opcodes/
	* i386-dis.c (x_mode): Comment.
	(two_source_ops): File scope.
	(float_mem): Correct fisttpll and fistpll.
	(float_mem_mode): New table.
	(dofloat): Use it.
	(OP_E): Correct intel mode PTR output.
	(ptr_reg): Use open_char and close_char.
	(PNI_Fixup): Handle possible suffix on sidt.  Use op1out etc. for
	operands.  Set two_source_ops.

gas/testsuite/
	* gas/i386/prescott.s: Remove fisttpd and fisttpq.
	* gas/i386/prescott.d: Update.
2004-06-23 15:06:53 +00:00
Michal Ludvig cbc2ab7c83 2004-03-12 Michal Ludvig <mludvig@suse.cz>
* i386.h (i386_optab): Added xstore as an alias for xstorerng.
2004-03-12 13:38:46 +00:00
Jakub Jelinek 1260d0e446 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
(INVLPG_Fixup): New function.
	(PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.

	* opcode/i386.h (i386_optab): Remove CpuNo64 from sysenter and
	sysexit.
2004-03-12 10:47:49 +00:00
Michal Ludvig 75f1011bbf 2004-03-12 Michal Ludvig <mludvig@suse.cz>
* gas/config/tc-i386.c (output_insn): Handle PadLock instructions.
	* gas/config/tc-i386.h (CpuPadLock): New define.
	(CpuUnknownFlags): Added CpuPadLock.
	* include/opcode/i386.h (i386_optab): Added xstore/xcrypt insns.
	* opcodes/i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
	(dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
	(padlock_table): New struct with PadLock instructions.
	(print_insn): Handle PADLOCK_SPECIAL.
2004-03-12 10:14:29 +00:00
H.J. Lu 203515ee13 gas/
2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* gas/config/tc-i386.c (md_assemble): Support Intel Precott New
	Instructions.

	* gas/config/tc-i386.h (CpuPNI): New.
	(CpuUnknownFlags): Add CpuPNI.

gas/testsuite/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Add prescott.

	* gas/i386/prescott.d: New file.
	* gas/i386/prescott.s: Likewise.

include/opcode/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel Precott New Instructions.

opcodes/

2003-06-23  H.J. Lu <hongjiu.lu@intel.com>

	* i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in
	Intel Precott New Instructions.
	(PREGRP27): New. Added for "addsubpd" and "addsubps".
	(PREGRP28): New. Added for "haddpd" and "haddps".
	(PREGRP29): New. Added for "hsubpd" and "hsubps".
	(PREGRP30): New. Added for "movsldup" and "movddup".
	(PREGRP31): New. Added for "movshdup" and "movhpd".
	(PREGRP32): New. Added for "lddqu".
	(dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry.
	Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for
	entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for
	entry 0xd0. Use PREGRP32 for entry 0xf0.
	(twobyte_has_modrm): Updated.
	(twobyte_uses_SSE_prefix): Likewise.
	(grps): Use PNI_Fixup in the "sidtQ" entry.
	(prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30,
	PREGRP31 and PREGRP32.
	(float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb.
	Use "fisttpll" in entry 1 in opcode 0xdd.
	Use "fisttp" in entry 1 in opcode 0xdf.
2003-06-23 20:15:33 +00:00
Alan Modra 23c3a85872 gas/ChangeLog
* config/tc-i386.c (process_suffix): Remove intel mode movsx and
	movzx fudges.
	(md_assemble): Instead, zap the suffix here.

include/opcode/ChangeLog
	* i386.h: Remove IgnoreSize from movsx and movzx.
2002-07-08 10:03:11 +00:00
Alan Modra d6e14e29f1 reorder cmpsd, movsd 2002-04-11 11:58:30 +00:00
Alan Modra 9ddd9fb225 * i386.h: Add intel mode cmpsd and movsd. 2002-04-11 10:21:58 +00:00
Jan Hubicka dda54ada03 * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. 2002-02-18 16:32:25 +00:00
Jan Hubicka 2b14b2d6da * i386.h (push,pop): Allow 16bit operands in 64bit mode.
(xchg): Fix.
	(in, out): Disable 64bit operands.
	(call, jmp): Avoid REX prefixes.
	(jcxz): Prohibit in 64bit mode
	(jrcxz, loop): Add 64bit variants.
	(movq): Fix patterns.
	(movmskps, pextrw, pinstrw): Add 64bit variants.
2002-02-11 11:56:20 +00:00
Alan Modra f513298e18 * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to
accept WordReg.
	* i386-dis.c (grps): Change "sldt", "str", and "smsw" entries
	to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand
	category instead of Ew.
2001-11-13 01:03:55 +00:00
Alan Modra 24a474a4aa Correct cvtps2dq, movdq2q, movq2dq, and movq problems. 2001-05-12 09:52:39 +00:00
Alan Modra 268fad77db Assorted fixes to pinsrw, pextrw, pmovmskb, movmskp, maskmovq. 2001-05-04 11:10:53 +00:00
Alan Modra e380bf39ff Small tweaks to sse2 instructions. 2001-03-24 06:29:15 +00:00
Alan Modra 46b107fb28 paddq and psubq support. 2001-03-22 02:27:53 +00:00
Alan Modra ca05a71296 Fix register name printed in warning message. 2001-03-19 11:28:20 +00:00
Nick Clifton c77e3e5481 Fix typos in ChangeLogs; add coff/external.h; fix copyright dates 2001-03-14 02:27:44 +00:00
Jan Hubicka 343329bac2 * i386.h (i386_optab): SSE integer converison instructions have
64bit versions on x86-64.
	* i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison
	instructions.
	(putop): Handle 'Y'
2001-02-12 16:42:49 +00:00
Alan Modra 77ab85cb32 Fix swapgs instruction. 2001-01-24 07:32:34 +00:00
Jan Hubicka ad3faf61ab * i386.c (md_assemble): Check cpu_flags even for nullary instructions.
* i386.h (i386_optab): Fix pusha and ret templates.

	* i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret
	templates.
2001-01-13 09:05:55 +00:00
Jan Hubicka d9d921952c * i386.h (pinsrw): Add.
(pshufw): Remove.
	(cvttpd2dq): Fix operands.
	(cvttps2dq): Likewise.
	(movq2q): Rename to movdq2q.
2001-01-10 14:31:46 +00:00
Alan Modra c0e5a443da Fix "movnti" 2001-01-10 00:24:43 +00:00
Jan Hubicka 8ab2401414 * tc-i386.c (md_assemble): Handle third byte of the opcode as prefix.
* i386.h (i386_optab): Make [sml]fence template to use immext field.
2001-01-05 12:30:12 +00:00
Jan Hubicka 234ad742b1 * tc-i386.h (CpuK6, CpuAthlon, CpuSledgehammer, CpuMMX, Cpu3dnow,
CpuUnknown): Renumber
	(CpuP4, CpuSSE2): New.
	(CpuUnknownFlags): Add CpuP4 and CpuSSE2

	* i386.h (i386_optab): Fix 64bit pushf template; Add instructions
	introduced by Pentium4
2001-01-03 15:36:26 +00:00
Jan Hubicka 00a8972f02 * configure.in: Add support for x86_64 and x86_64-*-linux-gnu*
* NEWS: Add x86_64.

	* i386.h (i386_optab): Add "rex*" instructions;
	add swapgs; disable jmp/call far direct instructions for
	64bit mode; add syscall and sysret; disable registers for 0xc6
	template.  Add 'q' suffixes to extendable instructions, disable
	obsoletted instructions, add new sign/zero extension ones.
	(i386_regtab): Add extended registers.
	(*Suf): Add No_qSuf.
	(q_Suf, wlq_Suf, bwlq_Suf): New.
2000-12-30 18:05:10 +00:00
Jan Hubicka 8a46ccd7e2 * tc-i386.h (i386_target_format): Define even for ELFs.
(QWORD_MNEM_SUFFIX): New macro.
	(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
	New macros
	(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
	(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
	ImmExt): Renumber.
	(Size64, No_qSuf, NoRex64, Rex64): New macros.
	(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
	(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
	InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
	SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
	(Reg, WordReg): Add Reg64.
	(Imm): Add Imm32S and Imm64.
	(EncImm): New.
	(Disp): Add Disp64 and Disp32S.
	(AnyMem): Add Disp32S.
	(RegRex, RegRex64): New macros.
	(rex_byte): New type.
	* tc-i386.c (set_16bit_code_flag): Kill.
	(fits_in_unsigned_long, fits_in_signed_long): New functions.
	(reloc): New parameter "signed"; support x86_64.
	(set_code_flag): New.
	(DEFAULT_ARCH): New macro; default to "i386".
	(default_arch): New static variable.
	(struct _i386_insn): New fields Operand_PCrel; rex.
	(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
	(flag_code): New enum and static variable.
	(use_rela_relocations): New static variable.
	(flag_code_names): New static variable.
	(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
	(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
	K6 and Athlon.
	(i386_align_code): Return plain "nop" for x86_64.
	(mode_from_disp_size): Support Disp32S.
	(smallest_imm_type): Support Imm32S and Imm64.
	(offset_in_range): Support size of 8.
	(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
	(md_pseudo_table): Add "code64"; use set_code_flat.
	(md_begin): Emit sane error message on hash failure.
	(tc_i386_fix_adjustable): Support x86_64 relocations.
	(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
	instructions supported on particular arch just partially,
	output of 64bit immediates, handling of Imm32S and Disp32S type.
	(i386_immedaite): Support x86_64 relocations; support 64bit constants.
	(i386_displacement): Likewise.
	(i386_index_check): Cleanup; support 64bit addresses.
	(md_apply_fix3): Support x86_64 relocation and rela.
	(md_longopts): Add "32" and "64".
	(md_parse_option): Add OPTION_32 and OPTION_64.
	(i386_target_format): Call even for ELFs; choose between
	elf64-x86-64 and elf32-i386.
	(i386_validate_fix): Refuse GOTOFF in 64bit mode.
	(tc_gen_reloc): Support rela relocations and x86_64.
	(intel_e09_1): Support QWORD.

	* i386.h (i386_optab): Replace "Imm" with "EncImm".
	(i386_regtab): Add flags field.
2000-12-20 13:24:13 +00:00
Jan Hubicka 24ef47fe10 * tc-i386.c (md_assemble): Refuse 's' and 'l' suffixes in the intel
mode; convert 'd' suffix to 's' or 'l'; remove all DWORD_MNEM_SUFFIX
	references.
	(intel_e09_1): Convert QWORD to 'l' suffix for FP operations; refuse
	otherwise.
	* tc-i386.h (DWORD_MNEM_SUFFIX): Kill.
	(No_dSuf): Kill.

	* i386.h (*_Suf): Remove No_dSuf.
	(d_suf, wld_Suf,sld_Suf, sldx_Suf, bwld_Suf, d_FP, sld_FP, sldx_FP)
	Remove.
	(i386_optab): Remove 'd' in the suffixes.
2000-12-11 14:01:46 +00:00
H.J. Lu e3c9eeaf79 2000-08-15 H.J. Lu <hjl@gnu.org>
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the
	IgnoreSize change.
2000-08-16 17:29:23 +00:00
Alan Modra 6458314f0d Allow d suffix on iret 2000-05-23 00:36:39 +00:00
Alan Modra 8c1c1f1a43 Fix fild. 2000-05-17 00:47:51 +00:00
Alan Modra e6342d0038 Fix cpu_flags for sys{enter,exit} fx{save,restore} 2000-05-13 14:01:54 +00:00
Alan Modra 9484bf7072 `.arch cpu_type' pseudo for x86. 2000-05-13 09:26:23 +00:00
Alan Modra 114d3d3070 Mostly cosmetic. Fixes to comments. Don't start as_bad and as_warn
messages with capital.  Don't malign Unixware, malign SysV386 instead.
2000-03-26 14:13:01 +00:00
Alan Modra e53d3a5d95 Extend the i386 gas testsuite to do some tests for intel_syntax. Fix all
the errors exposed by this addition.  These were intel mode
"fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al".
The failure with intel "out dx,al" was also present in att "out al,dx".
Extend testsuite to catch this case too.
2000-02-25 11:41:12 +00:00
Alan Modra df256a94d6 Correct intel_syntax fsub* and fdiv* handling. Oh, how I'd like to be rid
of UNIXWARE_COMPAT.
2000-02-24 12:40:45 +00:00
Alan Modra 1a80e0b5d2 Cosmetic changes to tc-i386.[ch] + extend x86 gas testsuite jmp and
call tests + tweak intel mode far call and jmp.
2000-01-15 12:06:03 +00:00
Alan Modra a3717e6ce0 x86 indirect jump/call syntax fixes. Disassembly fix for lcall. 1999-12-27 16:10:31 +00:00
Alan Modra a4972584a4 Allow spaces in i386 FP reg names, eg. %st ( 1 ). 1999-08-29 23:44:27 +00:00
Alan Modra e5af6ca113 Add AMD athlon support to x86 assembler and disassembler. 1999-08-21 12:40:35 +00:00
Alan Modra 0274eb115d Support for gcc to generate 16-bit i386 code. (.code16gcc) 1999-08-04 10:07:41 +00:00
Alan Modra 02309525c5 8
include/opcode/i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw
1999-07-13 07:41:47 +00:00