Nowadays, the code fetching command line options via semi-hosting are
unconditionally pulled in, so that the semi-hosting code is still
there even I compile with option --specs=nosys.specs.
gdb ./aarch64-none-elf/libgloss/aarch64/crt0.o
(gdb) disassemble _start
0x0000000000000050 <+80>: ldr x1, 0x128 <_cpu_init_hook+48>
0x0000000000000054 <+84>: mov w0, #0x15
0x0000000000000058 <+88>: hlt #0xf000
This patch fixes this problem by wrapping the code by ARM_RDI_MONITOR.
When semi-hosting is not used, set command line options to NULL.
On AArch64 we currently always link in crt0 regardless of if another
one is being provided by something else, like rdimon.a. This was never
an issue before as nosys was not supported on AArch64.
This updates the specs to supply a different crt0 when a semihosting
call is required.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
This fixed the compile for nosys and validation specs
but nosys won't run because of existing limitations to
aarch64's syscalls.c, it requires semihosting to get
commandline arguments and heap info without having a
fallback method as ARM does.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
This patch fixes the issue where nosys.specs is used to link.
e.g. The use of crt0 without any support for semihosting requested.
The AArch64 crt0 was missing an #ifdef for the initialise_monitor_handles
which was causing the link to fail. Sorry for missing this before.
Semihosting v2 changes are documented here:
https://developer.arm.com/docs/100863/latest/
The biggest change is the addition of an extensions mechanism
to add more extensions in the future.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
Semihosting v2 changes are documented here:
https://developer.arm.com/docs/100863/latest/
The biggest change is the addition of an extensions mechanism
to add more extensions in the future.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
This uses the new recursive build target in multi-build.in
The new spec files are:
For AArch32/ARM (m for mixed mode):
- rdimon-v2m.specs
- aprofile-validation-v2m.specs
- aprofile-ve-v2m.specs
These spec files will be using the new libraries generated
by multi-build.in.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
This uses the new recursive build target in multi-build.in
For AArch64 no new spec files are needed but the makefiles
are modified to keep them in sync with the ARM ones.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
e.g. from the same source file produce multiple libs by varying the
options passed to the compiler.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
When simulating arm code, the target program startup code (crt0) uses
semihosting invocations to get the command line from the simulator. The
simulator returns the command line and its size into the area passed in
parameter. (ARM 32-bit specifications :
http://infocenter.arm.com/help/topic/com.arm.doc.dui0058d/DUI0058.pdf
chapter "5.4.19 SYS_GET_CMDLINE").
The memory area pointed by the semihosting register argument is located
in .text section (usually not writtable (RX)).
If we run this code on a simulator that respects this rights properties
(qemu user-mode for instance), the command line will not be written to
the .text program memory, in particular the length of the string. The
program runs with an empty command line. This problem hasn't been seen
earlier probably because qemu user-mode is not so much used, but this can
happen with another simulator that refuse to write in a read-only segment.
With this modification, the command line can be correctly passed to the
target program.
Changes:
- libgloss/arm/crt0.S : Arguments passed to the AngelSWI_Reason_GetCmdLine
semihosting invocation are placed into .data section instead of .text
- libgloss/aarch64/crt0.S : Idem for aarch64 AngelSVC_Reason_GetCmdLine
semihosting.
ARM EABI toolchains can optionally use the "hf" suffix to identify
hardware floating point support. Use the "*-*-eabi*" pattern to match
these toolchains.
Original patch by Bryan Hundven for the Crosstool-NG project. Improved
by Alexey Neyman.
Signed-off-by: Carlos Santos <casantos@datacom.ind.br>
CC: Bryan Hundven <bryanhundven@gmail.com
CC: Alexey Neyman <stilor@att.net>
The changes in af272aca59 only works when
using gcc/g++ with -E or -save-temps, otherwise newlib's newlib.h gets
used even if -specs=nano.specs is specified. This is because the driver
only use cpp_options spec for the external cpp tool, not for the
integrated one.
This patch uses instead cpp_unique_options which is used in all cases:
it is used directly when the integrated preprocessor is used, and
indirectly by expansion of cpp_options otherwise.
Hi,
The changes in c028685518 to use
newlib-nano's include directory work for cc1 but not cc1plus. cc1plus
comes with its own cpp spec which does not have a name attached to it.
This patch uses the renaming trick on cpp_options instead of cpp, as
cpp_options is used both by cc1 and cc1plus.
Environ is defined in libgloss and libc:
- libgloss/or1k/syscalls.c
- libc/stdlib/environ.c
When linking we sometimes get errors:
or1k-elf-g++ test.o -mnewlib -mboard=or1ksim -lm -o test
/opt/shorne/software/or1k/lib/gcc/or1k-elf/5.3.0/../../../../or1k-elf/lib/libor1k.a(syscalls.o):(.data+0x0):
multiple definition of `environ'
/opt/shorne/software/or1k/lib/gcc/or1k-elf/5.3.0/../../../../or1k-elf/lib/libc.a(lib_a-environ.o):(.data+0x0):
first defined here
collect2: error: ld returned 1 exit status
This doesnt happen after the fix. Basic things build fine too.
There was an issue revealed in gdb testing where C++ virtual tables
were not getting properly initialized. This seems to be due to the
c++ global constructors moving from ctors to init_array.
This fix makes sure we call the proper method for initializing the
constructors in all places.
or1k uses reentrant calls by default, but there was no open_r defined
which caused failure in C++/C code such as:
int main() { std::cout << "test\n"; return 0; }
or
int main() {open(".", 0);}
After a binutils change "a while ago" (2015-12) to default to
--enable-initfini-array, i.e. to merge .ctors and .dtors into
.init_array and .fini_array, this is needed for cdtors to run at all.
Based on what goes on in arm/ and aarch64/. Tested for cris-elf by
running the gcc testsuite.
By the way, the configure test doesn't detect this change, so the
HAVE_INITFINI_ARRAY ifdeffery is somewhat redundant. Still, the
change is tested to be safe with older binutils too.
libgloss/
* cris/crt0.S, cris/lcrt0.c: Include newlib.h.
[HAVE_INITFINI_ARRAY] (_init): Define to __libc_init_array.
[HAVE_INITFINI_ARRAY] (_fini): Ditto __libc_fini_array.
HTML build fails with makeinfo 5.2 with the following error:
libgloss/doc/porting.texi:73: @menu seen before first @node
libgloss/doc/porting.texi:73: perhaps your @top node should be wrapped in
@ifnottex rather than @ifinfo?
Following the advice indeed solve the issue while still allowing pdf, dvi and
info builds to work.
ARCompact processors (ARC 600 and ARC 700) require three "nop"s after the
"flag 1" instruction. Later ARC processors do not have this requirement, so
it is possible to reduce size of "_exit_halt" for them.
libgloss/
2016-05-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc/crt0.S (_exit_halt): Insert nops only for ARCompact.
Initially crt0.S used a special function, declared as weak as a default
exception handler in interrupt vector table. To let user override individual
handlers, this function had multiple names - one for each IVT entry, which,
however, was terribly confusing for the debugger and user - because it
wasn't clear which symbol will be used as a function name in debugger.
Defining multiple separate functions - one for each handler, would resolve
the mess, but would increase code size of crt0.o.
To clean this up, this patch defines exception handlers as weak symbols as
well, but those are defined as just symbols, not functions, hence there
would be less confusion over what is what. At the same time, users still can
redefine exception handlers symbol by creating functions with respective
names.
libgloss/
2016-05-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc/crt0.S: Convert memory_error and friends to non-function
symbols.
crt0.S for ARC used to use instruction "asr.f lp_count, r3, 2" for all cores
except ARC601. However instructions which shift more than 1 bit are
optional, so this crt0.S didn't worked for all ARC cores.
Luckily this is a shift just by 2 bits on all occassions, so fix is trivial
- use two single-bit shifts.
libgloss/ChangeLog
2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com>
* arc/crt0.S: Fix support for processors without barrel-shifter.
Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
This is similar to commit 06537f05d4 to the
newlib for ARC.
GCC for ARC has been updated to provide consistent naming of preprocessor
definitions for different optional architecture features:
* __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for
-mbarrel-shifter
* __ARCEM__ instead of __EM__ for ARC EM cores
* __ARCHS__ instead of __HS__ for ARC HS cores
* etc (not used in libgloss)
This patch updates crt0.S for ARC to use new definitions instead of a
deprecated ones. To ensure compatibility with older compiler new definitions
are also defined in crt0.S if needed, based on presence of deprecated
preprocessor definitions.
libgloss/ChangeLog
2016-04-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
* arc/crt0.S: Use new GCC defines to detect processor features.
ARC aproach to this feature is similiar to ARM's one here.
2016-04-29 Anton Kolesov <anton.kolesov@synopsys.com>
* arc/nano.specs: New file.
* arc/Makefile.in: Support nano.specs.
* arc/nsim.specs: Likewise.
While running tests on internal systems, we identified an issue in the
startup code for newlib on AArch32 systems with Multiprocessor
Extensions to the architecture.
The issue is we were configuring page table flags to be Inner
cacheable/Outer non-cacheable, while for at least architectures with
Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no
write-allocate, and cacheable.
The attached patch fixes this, and no regression on arm-none-eabi
bare-metal tests.
Adopted suggestion given by Richard offline to avoid using jump.
libgloss/
* arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer
cacheable WB, and no allocate on WB for arch with multiprocessor
extension.
Change the type of the stack pointers to enable pointer calculations at byte
granularity, which is needed for the calculation of _or1k_stack_core[c] and
_or1k_exception_stack_core[c] with _or1k_stack_size and
_or1k_exception_stack_size. (util.c:53-54)
libgloss:
* arm/Makefile.in: Add newlib/libc/machine/arm to the include path if
newlib is present.
* arm/arm.h: Include acle-compat.h.
(THUMB_V7_V6M): Rename to ...
(PREFER_THUMB): This. Use ACLE macros __ARM_ARCH_ISA_ARM instead of
__ARM_ARCH_6M__ to decide whether to define it.
(THUMB1_ONLY): Define for Thumb-1 only targets.
(THUMB_V7M_V6M): Rename to ...
(THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding
ARMv7.
* arm/crt0.S: Use THUMB1_ONLY rather than __ARM_ARCH_6M__,
!__ARM_ARCH_ISA_ARM rather than THUMB_V7M_V6M for fp enabling, and
PREFER_THUMB rather than THUMB_V7_V6M. Rename other occurences of
THUMB_V7M_V6M to THUMB_VXM.
* arm/linux-crt0.c: Likewise.
* arm/redboot-crt0.S: Likewise.
* arm/swi.h: Likewise.
* arm/trap.S: Likewise.
newlib:
* libc/machine/arm/memcpy-stub.c: Use ACLE macros __ARM_ARCH_ISA_THUMB
and __ARM_ARCH_ISA_ARM to check for Thumb-2 only targets rather than
__ARM_ARCH and __ARM_ARCH_PROFILE.
* libc/machine/arm/memcpy.S: Likewise.
* libc/machine/arm/setjmp.S: Likewise for Thumb-1 only target and
include acle-compat.h.
* libc/machine/arm/strcmp.S: Likewise for Thumb-1 and Thumb-2 only
target and include acle-compat.h.
* libc/sys/arm/arm.h: Include acle-compat.h.
(THUMB_V7_V6M): Rename to ...
(PREFER_THUMB): This. Use ACLE macro __ARM_ARCH_ISA_ARM instead of
__ARM_ARCH_6M__ to decide whether to define it.
(THUMB1_ONLY): Define for Thumb-1 only targets.
(THUMB_V7M_V6M): Rename to ...
(THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding
ARMv7.
* libc/sys/arm/crt0.S: Use PREFER_THUMB rather than THUMB_V7_V6M and
rename THUMB_V7M_V6M into THUMB_VXM.
* libc/sys/arm/swi.h: Likewise.
The MSP430 debuggers support I/O on hardware through CIO, so
we can use a CIO-enabled library as the "nosys" library (in
addition to the libsim library, which talks to our simulator)
* configure.in: Don't build default libnosys for msp430
* configure: Regenerate.
* msp430/Makefile: Rename libcio to libnosys.
The file libgloss/rl78/write.c currently contains code which outputs
\r when \n is seen. The code will then output the \n as well.
This patch removes the bit of code that tests for \n and then outputs
\r.
I made this change to fix some failures in gdb.base/call-ar-st.exp. In
that test, I see two carriage returns followed by a newline. One CR is
output by the libgloss code. The other is output by the terminal driver.
The total list of failures fixed (using the default rl78 multilib) are:
FAIL: gdb.base/call-ar-st.exp: print print_double_array(double_array) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_char_array(char_array) (timeout)
FAIL: gdb.base/call-ar-st.exp: continue to tbreak2 (timeout)
FAIL: gdb.base/call-ar-st.exp: continuing to tbreak3 (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_double_array(array_d) (timeout)
FAIL: gdb.base/call-ar-st.exp: continuing to tbreak4 (timeout)
FAIL: gdb.base/call-ar-st.exp: print sum_array_print(10, *list1, *list2, *list3, *list4) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_small_structs (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_ten_doubles(123.456, 123.456, -0.12, -1.23, 343434.8, 89.098, 3.14, -5678.12345, -0.11111111, 216.97065) (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_small_structs from print_long_arg_list (timeout)
FAIL: gdb.base/call-ar-st.exp: print print_struct_rep(*struct1, *struct2, *struct3) (timeout)
FAIL: gdb.base/dprintf.exp: call: printf: 1st dprintf (timeout)
FAIL: gdb.base/dprintf.exp: call: printf: 2nd dprintf (timeout)
FAIL: gdb.base/interrupt.exp: process is alive (the program exited)
There are no regressions.
libgloss/ChangeLog:
* rl78/write.c (_write): Don't output CR when LF is encountered.
Allow exceptions to be nested, which is especially useful with urgent
interrupts while processing an exception.
The implementation counts up the nesting level with each call to an
exception. In the outer exception (level 1), the exception stack is
started. All nested exceptions just reserve the redzone (scratch
memory that may be used by compiler) and exception context on the
stack, but then process on the same scratch.
Restriction: Impure pointers are shared among all exceptions. This may
be solved by creating an impure data structure in the stack frame with
each nested exception.
* or1k/crt0.S: Add exception nesting
* or1k/exceptions-asm.S: ditto
* or1k/util.c: ditto
- With the gzll kernel we have two different loading options:
- If the image is loaded to the global memory, the bootstrapping
loads the kernel to local memory. Applications are loaded on
demand. The heap then starts right after bss.
- If the image is pre-loaded to the local memory it includes the
application binaries right after bss. The heap then starts after
the application objects.
- We can check if this is a gzll kernel as it has the string "gzll" at
0x2000. At 0x200c we then find the end of the application objects in
the image. If there is no global memory we set _or1k_heap_start to
this value.
* or1k/boards/optimsoc.S: Heap for gzll kernel
- Previously the heap started right after the bss section. This can now
be configured by changing the _or1k_heap_start symbol that defaults to
the old value (&end). In board_init_early, we can now set this to
another value.
* or1k/sbrk.c: Allow for different heap start
- Store the exception program counter (from EPCR) and exception status
register (from ESR) also during the exception. A runtime system may
replace them thereby to implement a thread switch.
* or1k/exception-asm.S: Store missing state
- We do not need a red zone here, as we do not operate on the current
stack, but always use the clear exception stack. Also reserve two
extra words for the context to store EPCR and ESR.
* or1k/crt0.S: Fix exception stack frame
* or1k/exception-asm.S: ditto
- During interrupt handling the PICSR, table pointers and current
interrupt line have been saved in incorrect registers and/or stored on
the stack.
- Save the pointer in r16/r18, PICSR in r20 and the current interrupt
line in r22. Those are callee-saved registers, so that the register
values will be preserved.
* or1k/interruts-asm.S: Change registers to callee-saved.
* msp430/msp430-sim.ld (.stack): Add an assertion to make sure
that the data area does not overrun the stack. PROVIDE a new
symbol __stack_size to allow the user to set the limit.
* msp430/msp430xl-sim.ld (.stack): Likewise.
* rl78/rl78-sim.ld (.stack): Likewise.
* rl78/rl78.ld (.stack): Likewise.
* rx/rx-sim.ld (.stack): Likewise.
* rx/rx.ld (.stack): Likewise.
* msp430/msp430.ld: Delete.
* msp430/msp430F5438A-l.ld: Delete.
* msp430/msp430F5438A-s.ld: Delete.
* msp430/crt_movedata.S: Delete.
* msp430/Makefile.in (SCRIPTS): Remove msp430.ld.
(CRT_OBJS): Add crt_move_highdata.o.
* msp430/memmodel.h (START_CRT_FUNC): New macro.
(END_CRT_FUNC): New macro.
(WEAK_DEF): New macro.
* msp430/crt0.S: Use new macros.
(move_highdata): New code to initialise the .data section if it is
held in high memory.
* msp430/msp430-sim.ld (.data): Add .either.data.
(.rodata2): Move some read-only data sections here.
(.text): Add .either.text.
(.rodata): Add .either.rodata.
(.bss): Add .either.bss.
* msp430/msp430xl-sim.ld (MEMORY): Add HIROM.
(.rodata2): Move some read-only data sections here.
(.upper.data): New section. Include notes about how to initialise
it.
This header was clearly copied from the common syscall.h and customized,
but the header comment is no longer accurate -- this isn't the general
file anymore.
* or1k/Makefile.in: Build and install board libraries
* or1k/board.h: New file
* or1k/boards/README: New file
* or1k/boards/atlys.S: New file
* or1k/boards/de0_nano.S: New file
* or1k/boards/ml501.S: New file
* or1k/boards/ml509.S: New file
* or1k/boards/optimsoc.S: New file
* or1k/boards/or1ksim-uart.S: New file
* or1k/boards/or1ksim.S: New file
* or1k/boards/ordb1a3pe1500.S: New file
* or1k/boards/ordb2a.S: New file
* or1k/boards/orpsocrefdesign.S: New file
* or1k/boards/tmpl.S: New file
* or1k/boards/tmpl.c: New file
* or1k/Makefile.in: Add libor1k
* or1k/README: New file
* or1k/caches-asm.S: New file
* or1k/exceptions-asm.S: New file
* or1k/exceptions.c: New file
* or1k/impure.c: New file
* or1k/include/or1k-nop.h: New file
* or1k/include/or1k-support.h: New file
* or1k/interrupts-asm.S: New file
* or1k/interrupts.c: New file
* or1k/mmu-asm.S: New file
* or1k/or1k-internals.h: New file
* or1k/or1k_uart.c: New file
* or1k/or1k_uart.h: New file
* or1k/outbyte.S: New file
* or1k/sbrk.c: New file
* or1k/sync-asm.S: New file
* or1k/syscalls.c: New file
* or1k/timer.c: New file
* or1k/util.c: New file
Remove FPU availability check, just use the pre-processor flags
to indicicate what the user wanted.
* mips/abiflags.S: New file.
* mips/regs.S (SR_MSA): Define macro.
* mips/mti32.ld: Place .MIPS.abiflags and wrap in marker symbols.
* mips/mti64.ld: Likewise.
* mips/mti64_64.ld: Likewise.
* mips/mti64_n32.ld: Likewise.
* mips/crt0.S: Remove .set noreorder throughout.
(zerobss): Open code the bltu macro instruction so that the
zero-loop does not have a NOP in the branch delay slot.
* msp430/crt0.S (high_bss): Add.
* msp430/msp430-sim.ld: Add error message if .upper sections are
detected.
* msp430/msp430xl-sim.ld (MEMORY): Adjust to better mimic real
life MCUs. Add support for upper and lower sections.
Alexander Fedotov-B55613
Yao Qi
Tamar Christina
Claudiu Zissulescu
Martin Young
Laurent ALFONSI
Jozef Lawrynowicz
Carlos Santos
Thomas Preud'homme
Thomas Preudhomme
Stafford Horne
Olof Kindgren
Hans-Peter Nilsson
Claudiu Zissulescu
Nick Clifton
Anton Kolesov
Yaakov Selkowitz
Jeff Johnston
David Hoover
Jiong Wang
Stefan Roesch
Corinna Vinschen
DJ Delorie
Kevin Buettner
Andre Simoes Dias Vieira
Mike Frysinger
Eric Botcazou
Anthony Green