Synopsys ARCv3 ISA includes 32-bit ARC HS5x targets and
64-bit ARC HS6x targets. Both CPU families are placed
in "arc64" subdirectories as it done for GCC port.
Target name arc64 is used for historical reasons and
Synopsys ARCv3 baremetal toolchains contain multilib
configurations both for 32-bit and 64-bit families.
arc32 target name is reserved for 32-bit ARC HS5x
targets in case of non-multilib 32-bit builds.
Note that libgloss libraries for ARCv3 are compatible with
libgloss for ARCv1/2. Thus, Makefile.inc for libgloss uses
sources from libgloss/arc directory except crtX.S files.
Co-authored-by: Shahab Vahedi <list@vahedi.org>
Co-authored-by: Claudiu Zissulescu <claziss@gmail.com>
Co-authored-by: Bruno Mauricio <brunoasmauricio@gmail.com>
Co-authored-by: Luis Silva <luis.m.silva99@hotmail.com>
Signed-off-by: Yuriy Kolerov <ykolerov@synopsys.com>
There's no semantic change, it's only to make the same code
compilable with MetaWare toolchian, which actually assumes
@x as a full name, not omitting @.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Replace __ARC_ALIGNED_ACCESS__ macro with the compiler defined
macro __ARC_UNALIGNED__ and improve file comments.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
The modifications added by the series "M-profile PACBTI-enablement"
(see 9d6b00511e50a54d2472d11f75f7c0f2b4a98b24) have introduced a couple
of .cfi_* instructions.
Like for e6459123e497409a9e3d845c39829a9602ba55a4, these instructions
create object files which contain .eh_frame sections. However, ARM uses
its own unwind info format, not .eh_frame, which is generated by
ARM-specific directives, not .cfi_*. The .eh_frame sections are useless,
but also not removed by strip and may be harmful with some linker
scripts.
Adding ".cfi_sections .debug_frame" (as in glibc) moves the generated
directives towards .debug_frame instead of .eh_frame. Making them easier
to handle.
* libc/machine/arm/aeabi_memmove-thumb2.S: Use .cfi_sections
.debug_frame.
* libc/machine/arm/aeabi_memset-thumb2.S: Likewise.
* libc/machine/arm/memchr.S: Likewise.
* libc/machine/arm/memcpy-armv7m.S: Likewise.
* libc/machine/arm/setjmp.S: Likewise.
* libc/machine/arm/strlen-armv7.S: Likewise.
* libc/machine/arm/strlen-thumb2-Os.S: Likewise.
The "longjmp" expects the "setjmp" to save the r58/r59 registers,
if there is any. With this change they are saved accordingly.
Checked for regression with running GCC's DejaGnu tests:
$ runtest execute.exp=pr56982.c dg-torture.exp=pr48542.c
Signed-off-by: Shahab Vahedi <shahab@synopsys.com>
Assembler for ARCv2 always extends the name provided by
.file directive to an absolute form.
On ARCv3 targets .file directive forces assembler to put
a provided string to DW_AT_name field as is without
extending to an absolute path. Then GDB cannot find
source files because of it.
The best way to fix this issue is just delete lines
with .file directive in .S files and let the compiler
to decide what DW_AT_name must contain. Particularly,
the compiler fills this filed by an absolute path to
a .S file because only absolute paths are used in
toolchain's build process.
Signed-off-by: Yuriy Kolerov <kolerov93@gmail.com>
ARC supports a restricted register file with 16 registers.
However, optimized routines support only a full register
file. Thus, fallback on default implementation in case
of 16-entry register file.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
When creating a split manual with one-node-per-page, the main index.html
ends up getting clobbered by the page for the index() function because
it uses "@node index" which, for html, also creates an index.html page.
To remedy this, add "Function " to every function node so now we output
"Function-index.html" and avoid clobbering. It also namespaces every
other function and helps make sure we don't clobber anything else.
Otherwise, there isn't really much rendering difference as @node text
is mostly internal. Node title text comes from @section instead.
... so that all of 'exit', '_exit', '_Exit' work. 'exit' thus becomes the
standard 'newlib/libc/stdlib/exit.c'. (Getting 'atexit' functional needs
further work elsewhere.)
See also commit 5841b2f6a4208682264d03e3edfa0a09881932a6
"nvptx: Implement '_exit' instead of 'exit'".
For the newlib part, warnings are all from lack of sync between
libc/machine/cris/sys/signal.h and libc/include/sys/signal.h. This
commit gets them sufficiently in sync again, functionality-wise and
declaration-wise. Still, nothing is declared that isn't supported at
the system level (i.e. in libgloss system calls and handled by the
CRIS simulator in the gdb project).
Use the same C preprocessor expressions to define FE_RMODE_MASK and
__RISCV_HARD_FLOAT.
The problem was noticed on GCC 10 which does not define __riscv_f.
Import memrchr.S for AArch64 from:
https://github.com/ARM-software/optimized-routines
commit 0cf84f26b6b8dcad8287fe30a4dcc1fdabd06560
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Thu Jul 27 17:14:57 2023 +0200
string: Fix corrupt GNU_PROPERTY_TYPE (5) size
For ELF32 the notes alignment is 4 and not 8.
Update AArch64 assembly string routines from:
https://github.com/ARM-software/optimized-routines
commit 0cf84f26b6b8dcad8287fe30a4dcc1fdabd06560
Author: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Thu Jul 27 17:14:57 2023 +0200
string: Fix corrupt GNU_PROPERTY_TYPE (5) size
For ELF32 the notes alignment is 4 and not 8.
Add license and copyright information to COPYING.NEWLIB as entry (56).
Zfinx/Zdinx are new extensions ratified in 2022, it similar to F/D extensions,
support hard float operation for single/double precision, but the difference
between Zfinx/Zdinx and F/D is Zfinx/Zdinx is operating under general purpose
registers rather than dedicated floating-point registers.
This patch improve the hard float support detection for RISC-V port, so
that Zfinx/Zdinx can have better/right performance.
Co-authored-by: Jesse Huang <jesse.huang@sifive.com>
Disable at least m68010 and m68020. These processors certainly do not
like unaligned accesses.
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Signed-off-by: Austin Morton <austinpmorton@gmail.com>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Rename s_nearbyint.c, s_fdim.c and s_scalbln.c to remove conflicts
Remove functions that are not needed from above files
Modify include paths
Add includes missing in cygwin build
Add missing types
Create Makefiles
Create header files to resolve dependencies between directories
Modify some instances of unsigned long to uint64_t for 32 bit platforms
Add HAVE_FPMATH_H
When compiling Newlib for arm targets with GCC 12.1 onward, the
passing of architecture extension information to the assembler is
automatic, making the use of .fpu and .arch_extension directives
in assembly files redundant.
With older versions of GCC, however, these directives must be
hard-coded into the `arm/setjmp.S' file to allow the assembly of
instructions concerning the storage and subsequent reloading of the
floating point registers to/from the jump buffer, respectively.
This patch conditionally adds the `.fpu vfpxd' and `.arch_extension
mve' directives based on compile-time preprocessor macros concerning
GCC version and target architectural features, such that both the
assembly and linking of setjmp.S succeeds for older versions of
Newlib.
We don't have floating-point exception or non-default rounding mode
support for the RISC-V soft-float environment, `feraiseexcept' and
`fesetround' do nothing unless the `__riscv_flen' macro has been set.
Therefore following ISO C language requirements[1] only define macros
for soft float that correspond to actually supported floating-point
environment features, removing failures from GCC testing such as:
FAIL: gcc.dg/torture/fp-int-convert-timode-3.c -O0 execution test
FAIL: gcc.dg/torture/fp-int-convert-timode-4.c -O0 execution test
References:
[1] "Programming languages -- C", ISO/IEC 9899:2023, working draft --
September 3, 2022, Section 7.6 "Floating-point environment <fenv.h>"
Fixes: 7040b2de0883 ("Add RISC-V port for libm")
Signed-off-by: Maciej W. Rozycki <macro@embecosm.com>
This is still not properly resolving <https://gcc.gnu.org/PR85463>
'[nvptx] "exit" in offloaded region doesn't terminate process', but is
one step into that direction, and allows for simplifying some GCC code.
... as implemented for GCN in 'newlib/libc/sys/amdgcn/*' files, but (for now)
still adding to the catch-all 'newlib/libc/machine/nvptx/misc.c' file.
This is necessary for the GCC/Fortran I/O system, for example.
Co-authored-by: Andrew Stubbs <ams@codesourcery.com>
The libgloss port has been reaching back into newlib internals for a
single header whose contents have been frozen for almost a decade.
To break this backwards libgloss->newlib dependency, move the acle
header to the srcroot include/ so everyone can use the same copy.
Add function prologue/epilogue to conditionally add BTI landing pads
and/or PAC code generation & authentication instructions depending on
compilation flags. Save the PAC value in the jump buffer so that
longjmp can only return to the authenticated location.
Add function prologue/epilogue to conditionally add BTI landing pads
and/or PAC code generation & authentication instructions depending on
compilation flags.
This patch enables PACBTI for all relevant variants of strlen:
* Newlib for armv8.1-m.main+pacbti
* Newlib for armv8.1-m.main+pacbti+mve
* Newlib-nano
Add function prologue/epilogue to conditionally add BTI landing pads
and/or PAC code generation & authentication instructions depending on
compilation flags.
This patch enables PACBTI for all relevant variants of strcmp:
* Newlib for armv8.1-m.main+pacbti
* Newlib for armv8.1-m.main+pacbti+mve
* Newlib-nano
Augment the arm_asm.h header file to simplify function prologues and
epilogues whilst adding support for PACBTI enablement via macros for
hand-written assembly functions. For PACBTI, both prologues/epilogues
as well as cfi-related directives are automatically amended
accordingly, depending on the compile-time mbranch-protection argument
values.
It defines the following preprocessor macros:
* HAVE_PAC_LEAF: Indicates whether pac-signing has been requested for
leaf functions.
* PAC_LEAF_PUSH_IP: Whether leaf functions should push the pac code
to the stack irrespective of whether the ip register is clobbered in
the function or not.
* STACK_ALIGN_ENFORCE: Whether a dummy register should be added to
the push list as necessary in the prologue to ensure stack
alignment preservation at the start of assembly function. The
epilogue behavior is likewise affected by this flag, ensuring any
pushed dummy registers also get popped on function return.
It also defines the following assembler macros:
* prologue: In addition to pushing any callee-saved registers onto
the stack, it generates any requested pacbti instructions.
Pushed registers are specified via the optional `first', `last',
`push_ip' and `push_lr' macro argument parameters.
when a single register number is provided, it pushes that
register. When two register numbers are provided, they specify a
rage to save. If push_ip and/or push_lr are non-zero, the
respective registers are also saved. Stack alignment is requested
via the `align` argument, which defaults to the value of
STACK_ALIGN_ENFORCE, unless manually overridden.
For example:
prologue push_ip=1 -> push {ip}
prologue push_ip=1, align8=1 -> push {r2, ip}
prologue push_ip=1, push_lr=1 -> push {ip, lr}
prologue 1 -> push {r1}
prologue 1, align8=1 -> push {r0, r1}
prologue 1 push_ip=1 -> push {r1, ip}
prologue 1 4 -> push {r1-r4}
prologue 1 4 push_ip=1 -> push {r1-r4, ip}
* epilogue: pops registers off the stack and emits pac key signing
instruction, if requested. The `first', `last', `push_ip',
`push_lr' and `align' function as per the prologue macro,
generating pop instead of push instructions.
Stack alignment is enforced via the following helper macro
call-chain:
{prologue|epilogue} ->_align8 -> _preprocess_reglist ->
_preprocess_reglist1 -> {_prologue|_epilogue}
Finally, the necessary cfi directives for adding debug information
to prologue and epilogue are generated via the following macros:
* cfisavelist - prologue macro helper function, generating
necessary .cfi_offset directives associated with push instruction.
Therefore, the net effect of calling `prologue 1 2 push_ip=1' is
to generate the following:
push {r1-r2, ip}
.cfi_adjust_cfa_offset 12
.cfi_offset 143, -4
.cfi_offset 2, -8
.cfi_offset 1, -12
* cfirestorelist - epilogue macro helper function, emitting
.cfi_restore instructions prior to resetting the cfa offset. As
such, calling `epilogue 1 2 push_ip=1' will produce:
pop {r1-r2, ip}
.cfi_register 143, 12
.cfi_restore 2
.cfi_restore 1
.cfi_def_cfa_offset 0
... so that all of 'exit', '_exit', '_Exit' work. 'exit' thus becomes the
standard 'newlib/libc/stdlib/exit.c' -- and functions registered via 'atexit'
are now called at return from 'main' or manual 'exit' invocation.
It seems there is a swapped logic in one of the subcases of
setjmp.S for MIPS: when the FPU registers are 64-bit within
a 32-bit aligned jmp_buf, the code realigns the pointers
before doing 64-bit writes, but the branch logic is swapped:
we must avoid the address adjustement when bit 2 is zero
(that is, the address is already 8-byte aligned).
This always triggers an address error when run, as tested
on a MIPS VR4300 with O64 ABI.
As per the arm Procedure Call Standard for the Arm Architecture
section 6.1.2 [1], VFP registers s16-s31 (d8-d15, q4-q7) must be
preserved across subroutine calls.
The current setjmp/longjmp implementations preserve only the core
registers, with the jump buffer size too small to store the required
co-processor registers.
In accordance with the C Library ABI for the Arm Architecture
section 6.11 [2], this patch sets _JBTYPE to long long adjusting
_JBLEN to 20.
It also emits vfp load/store instructions depending on architectural
support, predicated at compile time on ACLE feature-test macros.
[1] https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst
[2] https://github.com/ARM-software/abi-aa/blob/main/clibabi32/clibabi32.rst
Call __builtin_gcn_get_stack_limit and __builtin_gcn_first_call_this_thread_p
to reduce dependency on some register/layout assumptions by using the new
GCC mainline (GCC 13) builtins, if they are available. If not, the existing
code is used.
The first attempt to support the 64-bit mode had two bugs:
1. The saved general-purpose register 31 value was overwritten with the saved
link register value.
2. The link register was saved and restored using 32-bit instructions.
Use 64-bit store/load instructions to save/restore the link register. Make
sure that the general-purpose register 31 and the link register storage areas
do not overlap.
In a follow up patch, struct _reent is optionally replaced by dedicated
thread-local objects. In this case,_REENT is optionally defined to NULL. Add
the _REENT_IS_NULL() macro to disable this check on demand.
Add a _REENT_CLEANUP() macro to encapsulate access to the
__cleanup member of struct reent. This will help to replace the
struct member with a thread-local storage object in a follow up
patch.
Add a _REENT_STDERR() macro to encapsulate access to the _stderr
member of struct reent. This will help to replace the struct
member with a thread-local storage object in a follow up patch.
