operands is greater than 127.
2001-02-02 Patrick Macdonald <patrickm@redhat.com>
* cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short.
(CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES.
(CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS.
* fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS.
* m32r-desc.h: Regenerate.
* cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number
of operands (unsigned char or unsigned short).
(CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE.
(CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
(QWORD_MNEM_SUFFIX): New macro.
(CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags):
New macros
(CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber.
(IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix,
ImmExt): Renumber.
(Size64, No_qSuf, NoRex64, Rex64): New macros.
(Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
(Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32,
InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc,
SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber.
(Reg, WordReg): Add Reg64.
(Imm): Add Imm32S and Imm64.
(EncImm): New.
(Disp): Add Disp64 and Disp32S.
(AnyMem): Add Disp32S.
(RegRex, RegRex64): New macros.
(rex_byte): New type.
* tc-i386.c (set_16bit_code_flag): Kill.
(fits_in_unsigned_long, fits_in_signed_long): New functions.
(reloc): New parameter "signed"; support x86_64.
(set_code_flag): New.
(DEFAULT_ARCH): New macro; default to "i386".
(default_arch): New static variable.
(struct _i386_insn): New fields Operand_PCrel; rex.
(flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT";
(flag_code): New enum and static variable.
(use_rela_relocations): New static variable.
(flag_code_names): New static variable.
(cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64.
(cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to
K6 and Athlon.
(i386_align_code): Return plain "nop" for x86_64.
(mode_from_disp_size): Support Disp32S.
(smallest_imm_type): Support Imm32S and Imm64.
(offset_in_range): Support size of 8.
(set_cpu_arch): Do not clobber to Cpu64/CpuNo64.
(md_pseudo_table): Add "code64"; use set_code_flat.
(md_begin): Emit sane error message on hash failure.
(tc_i386_fix_adjustable): Support x86_64 relocations.
(md_assemble): Support QWORD_MNEM_SUFFIX, REX registers,
instructions supported on particular arch just partially,
output of 64bit immediates, handling of Imm32S and Disp32S type.
(i386_immedaite): Support x86_64 relocations; support 64bit constants.
(i386_displacement): Likewise.
(i386_index_check): Cleanup; support 64bit addresses.
(md_apply_fix3): Support x86_64 relocation and rela.
(md_longopts): Add "32" and "64".
(md_parse_option): Add OPTION_32 and OPTION_64.
(i386_target_format): Call even for ELFs; choose between
elf64-x86-64 and elf32-i386.
(i386_validate_fix): Refuse GOTOFF in 64bit mode.
(tc_gen_reloc): Support rela relocations and x86_64.
(intel_e09_1): Support QWORD.
* i386.h (i386_optab): Replace "Imm" with "EncImm".
(i386_regtab): Add flags field.
EM_* constants are assigned. Move EM_PJ from official section to
ad-hoc section.
(EM_CRIS): Correct comment to match official description.
(EM_MMIX): Ditto.
R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Change
numbers to the range from 160 to 167.
(R_SH_FIRST_INVALID_RELOC): Adjust.
(R_SH_FIRST_INVALID_RELOC_2, R_SH_LAST_INVALID_RELOC_2):
New relocs to fill in the gap.
bfd/
2000-08-14 Jim Wilson <wilson@cygnus.com>
* elf64-ia64.c (elf64_ia64_merge_private_bfd_data): Handle
EF_IA_64_REDUCEDFP, EF_IA_64_CONS_GP, and EF_IA_64_NOFUNCDESC_CONS_GP.
(elf64_ia64_print_private_bfd_data): Likewise. Also handle
EF_IA_64_ABSOLUTE.
gas/
2000-08-14 Jim Wilson <wilson@cygnus.com>
* config/tc-ia64.c (md_longopts): Add -mconstant-gp and -mauto-pic.
(md_parse_option): Add OPTION_MCONSTANT_GP and OPTION_MAUTO_PIC.
(md_begin): Change assignment to md.flag to OR in the new bit.
include/elf/
2000-08-14 Jim Wilson <wilson@cygnus.com>
* elf/ia64.h (EF_IA_64_REDUCEDFP, EF_IA_64_CONS_GP,
EF_IA_64_NOFUNCDESC_CONS_GP, EF_IA_64_ABSOLUTE): Define.
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* config/tc-i860.h: Rework completely for BFD_ASSEMBLER.
(i860_fix_info): New enum.
(MD_APPLY_FIX3): Define.
(WORKING_DOT_WORD): Define.
(TC_HANDLES_FX_DONE): Define.
(DIFF_EXPR_OK): Define.
(LISTING_HEADER): Define.
(TARGET_FORMAT): Select target format based on endian flag.
(TARGET_BYTES_BIG_ENDIAN): Default to little endian.
(target_big_endian): Add external declaration.
* config/tc-i860.c: All existing code reworked completely. Other
new code shown below.
(SYNTAX_SVR4): Define.
(target_warn_expand): New variable.
(md_shortopts): Declare and define (-Qy, -Qn, and -V options).
(md_longopts): Declare and define with new options (-EL, -EB,
and -mwarn-expand).
(md_show_usage): New function.
(md_operand): New function.
(obtain_reloc_for_imm16): New function.
(md_apply_fix3): New function.
(tc_gen_reloc): New function.
include:
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* opcode/i860.h: Small formatting adjustments.
opcode:
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* i860-dis.c (print_br_address): Change third argument from int
to long.
bfd:
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* elf32-i860.c (elf32_i860_howto_table): Updated some fields.
* opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* dis-asm.h (print_insn_i860): Add prototype.
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* include/elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* bfd/cpu-i860.c: Added comments.
* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
bfd_elf32_i860_little_vec.
(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
(ELF_MAXPAGESIZE): Changed to 4096.
* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
new target.
(bfd_target_vector): Added bfd_elf32_i860_little_vec.
* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
config for little endian elf32 i860.
(targ_defvec): Define for the new config above
as "bfd_elf32_i860_little_vec".
(targ_selvecs): Define for the new config above
as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
of new target vec.
* bfd/configure: Regenerated.
* opcodes/i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* opcodes/disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* include/dis-asm.h (print_insn_i860): Add prototype.
* opcodes/Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* opcodes/configure.in: New bits for bfd_i860_arch.
* opcodes/configure: Regenerated.
DJ Delorie
Nick Clifton
Phil Blundell
Jan Hubicka
H.J. Lu
Patrick Macdonald
Alan Modra
Jeff Johnston
Hans-Peter Nilsson
Jeff Law
Christopher Faylor
Richard Henderson
Jakub Jelinek
Jim Wilson
Alexandre Oliva
Jason Eckhardt
Denis Chertykov
Dave Brolley
Jason Merrill