Applied changes from commit 8d98f95:
* arm/crt0.S: Initialise __heap_limit when ARM_RDI_MONITOR is defined.
* arm/syscalls.c: define __heap_limit global symbol.
* arm/syscalls.c (_sbrk): Honour __heap_limit.
Applied changes from commit 8d98f95:
Fixed semihosting for ARM when heapinfo not provided by debugger
SP initialization changes:
1. set default value in semihosting case as well
2. moved existing SP & SL init code for processor modes in separate routine and made it as "hook"
3. init SP for processor modes in Thumb mode as well
Add new macro FN_RETURN, FN_EH_START and FN_EH_END.
The code in trap.S is to support the old APCS chunked stack variant,
which dates back to the Acorn days, so put it under #ifndef
__ARM_EABI__.
* libgloss/arm/trap.S: Use __ARM_EABI rather than PREFER_THUMB.
* newlib/libc/sys/arm/trap.S: Use __ARM_EABI rather than
__thumb2__.
The M class cores don't support Semihosting v2 mixed mode, but we were
accidentally using the new immediates for it. My last patch changed the
immediates which broke the build because doing a full multi-lib build
including M architectures now results in an assembler error instead of
silently doing the wrong thing.
This fixes the issue by changing the defines around such that According
to the specs any M class build uses the normal semihosting instructions.
Regtested on arm-none-eabi and no issues, using a build with m class
multilibs too.
The Semihosting v2 protocol requires us to output the Armv8-a HLT instruction
when in mixed mode (SEMIHOST_V2_MIXED_MODE), however it also requires this to
be done for Armv7-a and earlier architectures.
The HLT instruction is defined in the undefined encoding space for older
architectures but simulators such as QEMU already trap on it [1] for all
architectures and is a requirement for semihosting v2 [2].
Unfortunately the GAS restricts the use of HLT to Armv8-a which requires us to
use the instruction encodings we want directly in crt0.
This patch does this, I have not updated newlib/libc/* as that is quite out of
date already. A proper sync is needed in order to get things back in sync.
A different patch for this would be best.
[1] 19a6e31c9d
[2] https://developer.arm.com/docs/100863/latest/the-semihosting-interface
The _exit function currently passes -1 as a "sig" to the _kill function as an
invalid signal number so that _kill can distinguish between an abort and a
standard exit.
For boards using the SYS_EXIT_EXTENDED semi-hosting operation to return a
status code, this means that the "status" paramter to _exit is ignored and the
return code is always -1.
https://developer.arm.com/docs/100863/latest/semihosting-operations/sys_exit_extended-0x20
This patch puts shared code between _kill and _exit into a new function
_kill_shared that takes the semi-hosting "reason" to use (if semi-hosting is
available) as an argument.
For semi-hosting _kill_shared provides that "reason".
Without the "sig" argument being used to distinguish between a normal and
abnormal exit, the _exit function can provide the return code to be used if the
SYS_EXIT_EXTENDED operation is available.
Hence the exit code can be returned.
AngelSWI_Reason_ReportException does not return accoring to the ARM
documentation, so it is valid to mark _kill() as noreturn. This way,
the compiler does not warn about _exit() returning a value despite
being noreturn.
2018-10-01 Christophe Lyon <christophe.lyon@linaro.org>
* libgloss/arm/_exit.c (_exit): Declare _kill() as noreturn.
* libgloss/arm/_exit.c (_kill): Likewise. Remove the return
statements.
* newlib/libc/sys/arm/syscalls.c (_kill): Likewise..
The current SYS_EXIT has a bug that when making the call it always uses
the v2 calling convention. This is undefined behavior according to the
semihosting specification:
https://developer.arm.com/docs/100863/latest/semihosting-operations/sys_exit-0x18
This patch fixes it by making sure v1 passes the argument directly in the register instead
of in a block. And for v2 it does the same if the v2 extension isn't supported.
The sequence generated now is
12424: ebfffecd bl 11f60 <_has_ext_exit_extended>
12428: e3500000 cmp r0, #0
1242c: 11a0500d movne r5, sp
12430: 059d5000 ldreq r5, [sp]
12434: e1a00004 mov r0, r4
12438: e1a01005 mov r1, r5
1243c: ef00f000 svc 0x0000f000
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
Semihosting v2 changes are documented here:
https://developer.arm.com/docs/100863/latest/
The biggest change is the addition of an extensions mechanism
to add more extensions in the future.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
This uses the new recursive build target in multi-build.in
The new spec files are:
For AArch32/ARM (m for mixed mode):
- rdimon-v2m.specs
- aprofile-validation-v2m.specs
- aprofile-ve-v2m.specs
These spec files will be using the new libraries generated
by multi-build.in.
Signed-off-by: Tamar Christina <tamar.christina@arm.com>
When simulating arm code, the target program startup code (crt0) uses
semihosting invocations to get the command line from the simulator. The
simulator returns the command line and its size into the area passed in
parameter. (ARM 32-bit specifications :
http://infocenter.arm.com/help/topic/com.arm.doc.dui0058d/DUI0058.pdf
chapter "5.4.19 SYS_GET_CMDLINE").
The memory area pointed by the semihosting register argument is located
in .text section (usually not writtable (RX)).
If we run this code on a simulator that respects this rights properties
(qemu user-mode for instance), the command line will not be written to
the .text program memory, in particular the length of the string. The
program runs with an empty command line. This problem hasn't been seen
earlier probably because qemu user-mode is not so much used, but this can
happen with another simulator that refuse to write in a read-only segment.
With this modification, the command line can be correctly passed to the
target program.
Changes:
- libgloss/arm/crt0.S : Arguments passed to the AngelSWI_Reason_GetCmdLine
semihosting invocation are placed into .data section instead of .text
- libgloss/aarch64/crt0.S : Idem for aarch64 AngelSVC_Reason_GetCmdLine
semihosting.
ARM EABI toolchains can optionally use the "hf" suffix to identify
hardware floating point support. Use the "*-*-eabi*" pattern to match
these toolchains.
Original patch by Bryan Hundven for the Crosstool-NG project. Improved
by Alexey Neyman.
Signed-off-by: Carlos Santos <casantos@datacom.ind.br>
CC: Bryan Hundven <bryanhundven@gmail.com
CC: Alexey Neyman <stilor@att.net>
The changes in af272aca59 only works when
using gcc/g++ with -E or -save-temps, otherwise newlib's newlib.h gets
used even if -specs=nano.specs is specified. This is because the driver
only use cpp_options spec for the external cpp tool, not for the
integrated one.
This patch uses instead cpp_unique_options which is used in all cases:
it is used directly when the integrated preprocessor is used, and
indirectly by expansion of cpp_options otherwise.
Hi,
The changes in c028685518 to use
newlib-nano's include directory work for cc1 but not cc1plus. cc1plus
comes with its own cpp spec which does not have a name attached to it.
This patch uses the renaming trick on cpp_options instead of cpp, as
cpp_options is used both by cc1 and cc1plus.
While running tests on internal systems, we identified an issue in the
startup code for newlib on AArch32 systems with Multiprocessor
Extensions to the architecture.
The issue is we were configuring page table flags to be Inner
cacheable/Outer non-cacheable, while for at least architectures with
Multiprocessor Extension, we'd configure it to Inner/Outer write-back, no
write-allocate, and cacheable.
The attached patch fixes this, and no regression on arm-none-eabi
bare-metal tests.
Adopted suggestion given by Richard offline to avoid using jump.
libgloss/
* arm/cpu-init/rdimon-aem.S: Set TTBR0 to inner/outer
cacheable WB, and no allocate on WB for arch with multiprocessor
extension.
libgloss:
* arm/Makefile.in: Add newlib/libc/machine/arm to the include path if
newlib is present.
* arm/arm.h: Include acle-compat.h.
(THUMB_V7_V6M): Rename to ...
(PREFER_THUMB): This. Use ACLE macros __ARM_ARCH_ISA_ARM instead of
__ARM_ARCH_6M__ to decide whether to define it.
(THUMB1_ONLY): Define for Thumb-1 only targets.
(THUMB_V7M_V6M): Rename to ...
(THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding
ARMv7.
* arm/crt0.S: Use THUMB1_ONLY rather than __ARM_ARCH_6M__,
!__ARM_ARCH_ISA_ARM rather than THUMB_V7M_V6M for fp enabling, and
PREFER_THUMB rather than THUMB_V7_V6M. Rename other occurences of
THUMB_V7M_V6M to THUMB_VXM.
* arm/linux-crt0.c: Likewise.
* arm/redboot-crt0.S: Likewise.
* arm/swi.h: Likewise.
* arm/trap.S: Likewise.
newlib:
* libc/machine/arm/memcpy-stub.c: Use ACLE macros __ARM_ARCH_ISA_THUMB
and __ARM_ARCH_ISA_ARM to check for Thumb-2 only targets rather than
__ARM_ARCH and __ARM_ARCH_PROFILE.
* libc/machine/arm/memcpy.S: Likewise.
* libc/machine/arm/setjmp.S: Likewise for Thumb-1 only target and
include acle-compat.h.
* libc/machine/arm/strcmp.S: Likewise for Thumb-1 and Thumb-2 only
target and include acle-compat.h.
* libc/sys/arm/arm.h: Include acle-compat.h.
(THUMB_V7_V6M): Rename to ...
(PREFER_THUMB): This. Use ACLE macro __ARM_ARCH_ISA_ARM instead of
__ARM_ARCH_6M__ to decide whether to define it.
(THUMB1_ONLY): Define for Thumb-1 only targets.
(THUMB_V7M_V6M): Rename to ...
(THUMB_VXM): This. Defined based on __ARM_ARCH_ISA_ARM, excluding
ARMv7.
* libc/sys/arm/crt0.S: Use PREFER_THUMB rather than THUMB_V7_V6M and
rename THUMB_V7M_V6M into THUMB_VXM.
* libc/sys/arm/swi.h: Likewise.
This header was clearly copied from the common syscall.h and customized,
but the header comment is no longer accurate -- this isn't the general
file anymore.
* arm/configure.in: Revert previous fix and change host_makefile_frag
to calculate the absolute location of srcdir/../config/default.mh.
* arm/configure: Regenerated.
* arm/cpu-init/rdimon-aem.S: Disable for M class cores.
* arm/crt0.S: Don't call _rdimon_hw_init_hook for non-A class cores.
* arm/cpu-init/Makefile.in (CPU_INIT_OBJS): Use CFLAGS.
Thomas Klein <th.r.klein@web.de>
* arm/crt0.S: Manually set the target architecture
when compiling for Thumb1 on EABI targets.
Avoid v6-only Thumb-1 MOV instruction.
Alexander Fedotov
Christophe Lyon
Tamar Christina
Matthew Malcomson
Jaap de Wolff
Yaakov Selkowitz
Laurent ALFONSI
Carlos Santos
Thomas Preud'homme
Thomas Preudhomme
David Hoover
Jiong Wang
Andre Simoes Dias Vieira
Mike Frysinger
Corinna Vinschen
Jeff Johnston
Marcus Shawcroft
Richard Earnshaw
Nick Clifton