PR binutils/15068
* tic6x-dis.c: Add support for displaying 16-bit insns. * tic6xc-insn-formats.h (FLD): Add use of bitfield array. Add 16-bit opcodes. * tic6xc-opcode-table.h: Add 16-bit insns. * tic6x.h: Add support for 16-bit insns. * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array. * gas/tic6x/insns16-d-unit.s: New test. * gas/tic6x/insns16-d-unit.d: Expected disassembly. * gas/tic6x/insns16-ddec.s: New test. * gas/tic6x/insns16-ddec.d: Expected disassembly. * gas/tic6x/insns16-dinc.s: New test. * gas/tic6x/insns16-dinc.d: Expected disassembly. * gas/tic6x/insns16-dind.s: New test. * gas/tic6x/insns16-dind.d: Expected disassembly. * gas/tic6x/insns16-doff4.s: New test. * gas/tic6x/insns16-doff4.d: Expected disassembly. * gas/tic6x/insns16-l-unit.s: New test. * gas/tic6x/insns16-l-unit.d: Expected disassembly. * gas/tic6x/insns16-lsd-unit.s: New test. * gas/tic6x/insns16-lsd-unit.d: Expected disassembly. * gas/tic6x/insns16-m-unit.s: New test. * gas/tic6x/insns16-m-unit.d: Expected disassembly. * gas/tic6x/insns16-s-unit-pcrel.s: New test. * gas/tic6x/insns16-s-unit-pcrel.d: Expected disassembly. * gas/tic6x/insns16-s-unit: New test. * gas/tic6x/insns16-s-unit.d: Expected disassembly.
This commit is contained in:
Nick Clifton
parent
409c27f834
commit
f115039df1
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@ -1,3 +1,11 @@
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2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
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PR binutils/15068
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* tic6xc-insn-formats.h (FLD): Add use of bitfield array.
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Add 16-bit opcodes.
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* tic6xc-opcode-table.h: Add 16-bit insns.
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* tic6x.h: Add support for 16-bit insns.
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2013-03-21 Michael Schewe <michael.schewe@gmx.net>
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* h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
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@ -1,6 +1,5 @@
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/* TI C6X instruction format information.
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Copyright 2010
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Free Software Foundation, Inc.
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Copyright 2010-2013 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -20,7 +19,19 @@
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/* Define the FMT macro before including this file; it takes a name
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and the fields from tic6x_insn_format (defined in tic6x.h). */
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#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), (pos), (width) }
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/* Expansion fields values for 16 bits insn. */
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#define SAT(a) (((a) & 1) << TIC6X_COMPACT_SAT_POS)
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#define BR(a) (((a) & 1) << TIC6X_COMPACT_BR_POS)
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#define DSZ(a) (((a) & 7) << TIC6X_COMPACT_DSZ_POS)
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/* Composite fields for 16 bits insn. */
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#define BFLD(low_pos, width, pos) { (low_pos), (width), (pos) }
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#define BFLD1(a) 1, { a }
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#define BFLD2(a, b) 2, { a, b }
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#define BFLD3(a, b, c) 3, { a, b, c }
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#define BFLD4(a, b, c, d) 4, { a, b, c, d }
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#define COMPFLD(name, bitfields) { CONCAT2(tic6x_field_,name), bitfields }
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/**/
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#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), BFLD1(BFLD(pos, width, 0)) }
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#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1)
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#define CFLDS2(a, b) 5, { CFLDS, a, b }
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#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c }
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@ -36,6 +47,21 @@
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#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e }
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#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f }
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#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g }
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/* 16 bits insn */
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#define FLDS1(a) 1, { a }
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#define FLDS2(a, b) 2, { a, b }
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#define FLDS3(a, b, c) 3, { a, b, c }
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#define FLDS4(a, b, c, d) 4, { a, b, c, d }
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#define FLDS5(a, b, c, d, e) 5, { a, b, c, d, e }
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#define SFLDS FLD(s, 0, 1)
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#define SFLDS1(a) 2, { SFLDS, a }
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#define SFLDS2(a, b) 3, { SFLDS, a, b }
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#define SFLDS3(a, b, c) 4, { SFLDS, a, b, c }
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#define SFLDS4(a, b, c, d) 5, { SFLDS, a, b, c, d }
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#define SFLDS5(a, b, c, d, e) 6, { SFLDS, a, b, c, d, e }
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#define SFLDS6(a, b, c, d, e, f) 7, { SFLDS, a, b, c, d, e, f }
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#define SFLDS7(a, b, c, d, e, f, g) 8, { SFLDS, a, b, c, d, e, f, g }
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/**/
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/* These are in the order from SPRUFE8, appendices C-H. */
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@ -68,6 +94,194 @@ FMT(d_adda_long, 32, 0x1000000c, 0xf000000c,
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/* Appendix C 16-bit formats will go here. */
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/* C-8 */
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FMT(d_doff4_dsz_0xx, 16, DSZ(0) | 0x0004, DSZ(0x4) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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FMT(d_doff4_dsz_100, 16, DSZ(4) | 0x0004, DSZ(0x7) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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FMT(d_doff4_dsz_000, 16, DSZ(0) | 0x0004, DSZ(0x7) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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FMT(d_doff4_dsz_x01, 16, DSZ(1) | 0x0004, DSZ(0x3) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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FMT(d_doff4_dsz_01x, 16, DSZ(2) | 0x0004, DSZ(0x6) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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FMT(d_doff4_dsz_111, 16, DSZ(7) | 0x0004, DSZ(0x7) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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FMT(d_doff4_dsz_x11, 16, DSZ(3) | 0x0004, DSZ(0x3) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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FMT(d_doff4_dsz_010, 16, DSZ(2) | 0x0004, DSZ(0x7) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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FMT(d_doff4_dsz_110, 16, DSZ(6) | 0x0004, DSZ(0x7) | 0x0406,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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/* C-9 */
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FMT(d_doff4dw, 16, DSZ(4) | 0x0004, DSZ(0x4) | 0x0406,
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SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2), FLD(sz, 9, 1), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
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/* C-10 */
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FMT(d_dind_dsz_0xx, 16, DSZ(0) | 0x0404, DSZ(0x4) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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FMT(d_dind_dsz_x01, 16, DSZ(1) | 0x0404, DSZ(0x3) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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FMT(d_dind_dsz_x11, 16, DSZ(3) | 0x0404, DSZ(0x3) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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FMT(d_dind_dsz_01x, 16, DSZ(2) | 0x0404, DSZ(0x6) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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FMT(d_dind_dsz_000, 16, DSZ(0) | 0x0404, DSZ(0x7) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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FMT(d_dind_dsz_010, 16, DSZ(2) | 0x0404, DSZ(0x7) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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FMT(d_dind_dsz_100, 16, DSZ(4) | 0x0404, DSZ(0x7) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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FMT(d_dind_dsz_110, 16, DSZ(6) | 0x0404, DSZ(0x7) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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FMT(d_dind_dsz_111, 16, DSZ(7) | 0x0404, DSZ(0x7) | 0x0c06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(src1, 13, 3)))
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/* C-11 */
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FMT(d_dinddw, 16, DSZ(4) | 0x0404, DSZ(0x4) | 0x0c06,
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SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
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FLD(sz, 9, 1), FLD(t, 12, 1), FLD(src1, 13, 3)))
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/* C-12 */
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FMT(d_dinc_dsz_x01, 16, DSZ(1) | 0x0c04, DSZ(0x3) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_dinc_dsz_0xx, 16, DSZ(0) | 0x0c04, DSZ(0x4) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_dinc_dsz_01x, 16, DSZ(2) | 0x0c04, DSZ(0x6) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_dinc_dsz_x11,16, DSZ(3) | 0x0c04, DSZ(0x3) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_dinc_dsz_000, 16, DSZ(0) | 0x0c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_dinc_dsz_010, 16, DSZ(2) | 0x0c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_dinc_dsz_100, 16, DSZ(4) | 0x0c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_dinc_dsz_110, 16, DSZ(6) | 0x0c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_dinc_dsz_111, 16, DSZ(7) | 0x0c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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/* C-13*/
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FMT(d_dincdw, 16, DSZ(4) | 0x0c04, DSZ(0x4) | 0xcc06,
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SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
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FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1)))
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/* C-14 */
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FMT(d_ddec_dsz_01x, 16, DSZ(2) | 0x4c04, DSZ(0x6) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_ddec_dsz_0xx, 16, DSZ(0) | 0x4c04, DSZ(0x4) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_ddec_dsz_x01, 16, DSZ(1) | 0x4c04, DSZ(0x3) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_ddec_dsz_x11, 16, DSZ(3) | 0x4c04, DSZ(0x3) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_ddec_dsz_000, 16, DSZ(0) | 0x4c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_ddec_dsz_010, 16, DSZ(2) | 0x4c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_ddec_dsz_100, 16, DSZ(4) | 0x4c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_ddec_dsz_110, 16, DSZ(6) | 0x4c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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FMT(d_ddec_dsz_111, 16, DSZ(7) | 0x4c04, DSZ(0x7) | 0xcc06,
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SFLDS6(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(ptr, 7, 2), FLD(sz, 9, 1),
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FLD(t, 12, 1), FLD(cst, 13, 1)))
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/* C-15 */
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FMT(d_ddecdw, 16, DSZ(4) | 0x4c04, DSZ(0x4) | 0xcc06,
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SFLDS7(FLD(op, 3, 1), FLD(na, 4, 1), FLD(srcdst, 5, 2), FLD(ptr, 7, 2),
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FLD(sz, 9, 1), FLD(t, 12, 1), FLD(cst, 13, 1)))
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/* C-16 */
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FMT(d_dstk, 16, 0x8c04, 0x8c06,
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SFLDS4(FLD(op, 3, 1), FLD(srcdst, 4, 3), FLD(t, 12, 1),
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COMPFLD(cst, BFLD2(BFLD(7, 3, 2), BFLD(13, 2, 0)))))
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/* C-17 */
|
||||
FMT(d_dx2op, 16, 0x0036, 0x047e,
|
||||
SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1), FLD(srcdst, 13, 3)))
|
||||
|
||||
/* C-18 */
|
||||
FMT(d_dx5, 16, 0x0436, 0x047e,
|
||||
SFLDS2(FLD(dst, 7, 3),
|
||||
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
|
||||
|
||||
/* C-19 */
|
||||
FMT(d_dx5p, 16, 0x0c76, 0x1c7e,
|
||||
SFLDS2(FLD(op, 7, 1),
|
||||
COMPFLD(cst, BFLD2(BFLD(8, 2, 3), BFLD(13, 3, 0)))))
|
||||
|
||||
/* C-20 */
|
||||
FMT(d_dx1, 16, 0x1876, 0x1c7e,
|
||||
SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
|
||||
|
||||
/* C-21 */
|
||||
FMT(d_dpp, 16, 0x0077, 0x087f,
|
||||
SFLDS5(FLD(srcdst, 7, 4), FLD(t, 12, 1), FLD(cst, 13, 1), FLD(op, 14, 1),
|
||||
FLD(dw, 15, 1)))
|
||||
|
||||
/* Appendix D 32-bit formats. */
|
||||
|
||||
FMT(l_1_or_2_src, 32, 0x18, 0x1c,
|
||||
|
|
@ -82,6 +296,44 @@ FMT(l_unary, 32, 0x358, 0xffc,
|
|||
|
||||
/* Appendix D 16-bit formats will go here. */
|
||||
|
||||
/* D-4 */
|
||||
FMT(l_l3_sat_0, 16, SAT(0) | 0x0000, SAT(1) | 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
|
||||
FLD(src1, 13, 3)))
|
||||
|
||||
FMT(l_l3_sat_1, 16, SAT(1) | 0x0000, SAT(1) | 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
|
||||
FLD(src1, 13, 3)))
|
||||
|
||||
/* D-5 - combine cst3 and n fields into a single field cst */
|
||||
FMT(l_l3i, 16, 0x0400, 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(sn, 11, 1), FLD(x, 12, 1),
|
||||
COMPFLD(cst, BFLD2(BFLD(13, 3, 0), BFLD(11, 1, 3)))))
|
||||
|
||||
/* D-6 Mtbd ? */
|
||||
|
||||
/* D-7 */
|
||||
FMT(l_l2c, 16, 0x0408, 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 1), FLD(src2, 7, 3), FLD(x, 12, 1), FLD(src1, 13, 3),
|
||||
COMPFLD(op, BFLD2(BFLD(5, 2, 0), BFLD(11, 1, 2)))))
|
||||
|
||||
/* D-8 */
|
||||
FMT(l_lx5, 16, 0x0426, 0x047e,
|
||||
SFLDS2(FLD(dst, 7, 3),
|
||||
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
|
||||
|
||||
/* D-9 */
|
||||
FMT(l_lx3c, 16, 0x0026, 0x147e,
|
||||
SFLDS3(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 3)))
|
||||
|
||||
/* D-10 */
|
||||
FMT(l_lx1c, 16, 0x1026, 0x147e,
|
||||
SFLDS4(FLD(src2, 7, 3), FLD(dst, 11, 1), FLD(cst, 13, 1), FLD(op, 14, 2)))
|
||||
|
||||
/* D-11 */
|
||||
FMT(l_lx1, 16, 0x1866, 0x1c7e,
|
||||
SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
|
||||
|
||||
/* Appendix E 32-bit formats. */
|
||||
|
||||
FMT(m_compound, 32, 0x30, 0x83c,
|
||||
|
|
@ -101,6 +353,12 @@ FMT(m_mpy, 32, 0x0, 0x7c,
|
|||
FLD(src2, 18, 5), FLD(dst, 23, 5)))
|
||||
|
||||
/* Appendix E 16-bit formats will go here. */
|
||||
FMT(m_m3_sat_0, 16, SAT(0) | 0x001e, SAT(1) | 0x001e,
|
||||
SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2),
|
||||
FLD(x, 12, 1), FLD(src1, 13, 3)))
|
||||
FMT(m_m3_sat_1, 16, SAT(1) | 0x001e, SAT(1) | 0x001e,
|
||||
SFLDS5(FLD(op, 5, 2), FLD(src2, 7, 3), FLD(dst, 10, 2),
|
||||
FLD(x, 12, 1), FLD(src1, 13, 3)))
|
||||
|
||||
/* Appendix F 32-bit formats. */
|
||||
|
||||
|
|
@ -148,7 +406,113 @@ FMT(s_bpos, 32, 0x20, 0x1ffc,
|
|||
|
||||
/* Appendix F 16-bit formats will go here. */
|
||||
|
||||
/* F-17 Sbs7 Instruction Format */
|
||||
FMT(s_sbs7, 16, BR(1) | 0x000a, BR(1) | 0x003e,
|
||||
SFLDS2(FLD(cst, 6, 7), FLD(n, 13, 3)))
|
||||
|
||||
/* F-18 Sbu8 Instruction Format */
|
||||
FMT(s_sbu8, 16, BR(1) | 0xc00a, BR(1) | 0xc03e,
|
||||
SFLDS1(FLD(cst, 6, 8)))
|
||||
|
||||
/* F-19 Scs10 Instruction Format */
|
||||
FMT(s_scs10, 16, BR(1) | 0x001a, BR(1) | 0x003e,
|
||||
SFLDS1(FLD(cst, 6, 10)))
|
||||
|
||||
/* F-20 Sbs7c Instruction Format */
|
||||
FMT(s_sbs7c, 16, BR(1) | 0x002a, BR(1) | 0x002e,
|
||||
SFLDS3(FLD(z, 4, 1), FLD(cst, 6, 7), FLD(n, 13, 3)))
|
||||
|
||||
/* F-21 Sbu8c Instruction Format */
|
||||
FMT(s_sbu8c, 16, BR(1) | 0xc02a, BR(1) | 0xc02e,
|
||||
SFLDS2(FLD(z, 4, 1), FLD(cst, 6, 8)))
|
||||
|
||||
/* F-22 S3 Instruction Format */
|
||||
FMT(s_s3, 16, BR(0) | 0x000a, BR(1) | 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
|
||||
FLD(src1, 13, 3)))
|
||||
|
||||
FMT(s_s3_sat_x, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(0) | 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
|
||||
FLD(src1, 13, 3)))
|
||||
|
||||
FMT(s_s3_sat_0, 16, BR(0) | SAT(0) | 0x000a, BR(1) | SAT(1) | 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
|
||||
FLD(src1, 13, 3)))
|
||||
|
||||
FMT(s_s3_sat_1, 16, BR(0) | SAT(1) | 0x000a, BR(1) | SAT(1) | 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
|
||||
FLD(src1, 13, 3)))
|
||||
|
||||
/* F-23 S3i Instruction Format */
|
||||
FMT(s_s3i, 16, BR(0) | 0x040a, BR(1) | 0x040e,
|
||||
SFLDS5(FLD(dst, 4, 3), FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
|
||||
FLD(cst, 13, 3)))
|
||||
|
||||
/* F-24 Smvk8 Instruction Format */
|
||||
FMT(s_smvk8, 16, 0x0012, 0x001e,
|
||||
SFLDS2(FLD(dst, 7, 3),
|
||||
COMPFLD(cst, BFLD4(BFLD(10, 1, 7), BFLD(5, 2, 5), BFLD(11, 2, 3), BFLD(13, 3, 0)))))
|
||||
|
||||
/* F-25 Ssh5 Instruction Format */
|
||||
FMT(s_ssh5_sat_x, 16, SAT(0) | 0x0402, SAT(0) | 0x041e,
|
||||
SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
|
||||
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
|
||||
FMT(s_ssh5_sat_0, 16, SAT(0) | 0x0402, SAT(1) | 0x041e,
|
||||
SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
|
||||
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
|
||||
FMT(s_ssh5_sat_1, 16, SAT(1) | 0x0402, SAT(1) | 0x041e,
|
||||
SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
|
||||
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
|
||||
|
||||
/* F-26 S2sh Instruction Format */
|
||||
FMT(s_s2sh, 16, 0x0462, 0x047e,
|
||||
SFLDS3(FLD(srcdst, 7, 3), FLD(op, 11, 2), FLD(src1, 13, 3)))
|
||||
|
||||
/* F-27 Sc5 Instruction Format */
|
||||
FMT(s_sc5, 16, 0x0002, 0x041e,
|
||||
SFLDS3(FLD(op, 5, 2), FLD(srcdst, 7, 3),
|
||||
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
|
||||
|
||||
/* F-28 S2ext Instruction Format */
|
||||
FMT(s_s2ext, 16, 0x0062, 0x047e,
|
||||
SFLDS3(FLD(src, 7, 3), FLD(op, 11, 2), FLD(dst, 13, 3)))
|
||||
|
||||
/* F-29 Sx2op Instruction Format */
|
||||
FMT(s_sx2op, 16, 0x002e, 0x047e,
|
||||
SFLDS4(FLD(src2, 7, 3), FLD(op, 11, 1), FLD(x, 12, 1),
|
||||
FLD(srcdst, 13, 3)))
|
||||
|
||||
/* F-30 Sx5 Instruction Format */
|
||||
FMT(s_sx5, 16, 0x042e, 0x047e,
|
||||
SFLDS2(FLD(dst, 7, 3),
|
||||
COMPFLD(cst, BFLD2(BFLD(11, 2, 3), BFLD(13, 3, 0)))))
|
||||
|
||||
/* F-31 Sx1 Instruction Format */
|
||||
FMT(s_sx1, 16, 0x186e, 0x1c7e,
|
||||
SFLDS2(FLD(srcdst, 7, 3), FLD(op, 13, 3)))
|
||||
|
||||
/* F-32 Sx1b Instruction Format */
|
||||
FMT(s_sx1b, 16, 0x006e, 0x187e,
|
||||
SFLDS2(FLD(src2, 7, 4), FLD(n, 13, 3)))
|
||||
|
||||
/* Appendix G 16-bit formats will go here. */
|
||||
FMT(lsdmvto, 16, 0x0006, 0x0066,
|
||||
SFLDS4(FLD(unit, 3, 2),
|
||||
FLD(x, 12, 1), FLD(dst, 13, 3),
|
||||
COMPFLD(src2, BFLD2(BFLD(10, 2, 3), BFLD(7, 3, 0)))))
|
||||
|
||||
FMT(lsdmvfr, 16, 0x0046, 0x0066,
|
||||
SFLDS4(FLD(unit, 3, 2), FLD(src2, 7, 3), FLD(x, 12, 1),
|
||||
COMPFLD(dst, BFLD2(BFLD(10, 2, 3), BFLD(13, 3, 0)))))
|
||||
|
||||
/* G-3 */
|
||||
FMT(lsdx1c, 16, 0x0866, 0x1c66,
|
||||
SFLDS4(FLD(unit, 3, 2), FLD(dst, 7, 3), FLD(cst, 13, 1),
|
||||
FLD(cc, 14, 2)))
|
||||
|
||||
/* G-4 */
|
||||
FMT(lsdx1, 16, 0x1866, 0x1c66,
|
||||
SFLDS3(FLD(unit, 3, 2), FLD(srcdst, 7, 3), FLD(op, 13, 3)))
|
||||
|
||||
/* Appendix H 32-bit formats. */
|
||||
|
||||
|
|
@ -180,6 +544,38 @@ FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc,
|
|||
|
||||
/* Appendix H 16-bit formats will go here. */
|
||||
|
||||
/* H-5 */
|
||||
FMT(nfu_uspl, 16, 0x0c66, 0xbc7e,
|
||||
FLDS2(FLD(op, 0, 1), COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3)))))
|
||||
|
||||
/* H-6 */
|
||||
/* make up some fields to pretend to have s and z fields s for this format
|
||||
so as to fit in other predicated compact instruction to avoid special-
|
||||
casing this instruction in tic6x-dis.c
|
||||
use op field as a predicate adress register selector (s field)
|
||||
use the first zeroed bit as a z value as this insn only supports [a0]
|
||||
and [b0] predicate forms.
|
||||
*/
|
||||
FMT(nfu_uspldr, 16, 0x8c66, 0xbc7e,
|
||||
FLDS4(FLD(op, 0, 1), FLD(s, 0, 1), FLD(z, 3, 1),
|
||||
COMPFLD(ii, BFLD2(BFLD(7, 3, 0), BFLD(14, 1, 3)))))
|
||||
|
||||
/* H-7 */
|
||||
FMT(nfu_uspk, 16, 0x1c66, 0x3c7e,
|
||||
FLDS1(COMPFLD(fstgfcyc, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
|
||||
|
||||
/* H-8a */
|
||||
FMT(nfu_uspma, 16, 0x2c66, 0x3c7e,
|
||||
FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
|
||||
|
||||
/* H-8b */
|
||||
FMT(nfu_uspmb, 16, 0x3c66, 0x3c7e,
|
||||
FLDS1(COMPFLD(mask, BFLD3(BFLD(0, 1, 0), BFLD(7, 3, 1), BFLD(14, 2, 4)))))
|
||||
|
||||
/* H-9 */
|
||||
FMT(nfu_unop, 16, 0x0c6e, 0x1fff,
|
||||
FLDS1(FLD(n, 13, 3)))
|
||||
|
||||
#undef FLD
|
||||
#undef CFLDS
|
||||
#undef CFLDS2
|
||||
|
|
@ -196,3 +592,25 @@ FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc,
|
|||
#undef NFLDS5
|
||||
#undef NFLDS6
|
||||
#undef NFLDS7
|
||||
#undef SFLDS
|
||||
#undef SFLDS1
|
||||
#undef SFLDS2
|
||||
#undef SFLDS3
|
||||
#undef SFLDS4
|
||||
#undef SFLDS5
|
||||
#undef SFLDS6
|
||||
#undef SFLDS7
|
||||
#undef BFLD
|
||||
#undef BFLD1
|
||||
#undef BFLD2
|
||||
#undef BFLD3
|
||||
#undef BFLD4
|
||||
#undef FLDS1
|
||||
#undef FLDS2
|
||||
#undef FLDS3
|
||||
#undef FLDS4
|
||||
#undef FLDS5
|
||||
#undef COMPFLD
|
||||
#undef DSZ
|
||||
#undef BR
|
||||
#undef SAT
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -27,18 +27,25 @@
|
|||
typedef enum
|
||||
{
|
||||
tic6x_field_baseR,
|
||||
tic6x_field_cc,
|
||||
tic6x_field_creg,
|
||||
tic6x_field_cst,
|
||||
tic6x_field_csta,
|
||||
tic6x_field_cstb,
|
||||
tic6x_field_dst,
|
||||
tic6x_field_dstms,
|
||||
tic6x_field_dw,
|
||||
tic6x_field_fstgfcyc,
|
||||
tic6x_field_h,
|
||||
tic6x_field_ii,
|
||||
tic6x_field_mask,
|
||||
tic6x_field_mode,
|
||||
tic6x_field_n,
|
||||
tic6x_field_na,
|
||||
tic6x_field_offsetR,
|
||||
tic6x_field_op,
|
||||
tic6x_field_p,
|
||||
tic6x_field_ptr,
|
||||
tic6x_field_r,
|
||||
tic6x_field_s,
|
||||
tic6x_field_sc,
|
||||
|
|
@ -46,6 +53,11 @@ typedef enum
|
|||
tic6x_field_src1,
|
||||
tic6x_field_src2,
|
||||
tic6x_field_srcdst,
|
||||
tic6x_field_srcms,
|
||||
tic6x_field_sn,
|
||||
tic6x_field_sz,
|
||||
tic6x_field_unit,
|
||||
tic6x_field_t,
|
||||
tic6x_field_x,
|
||||
tic6x_field_y,
|
||||
tic6x_field_z
|
||||
|
|
@ -53,14 +65,24 @@ typedef enum
|
|||
|
||||
typedef struct
|
||||
{
|
||||
/* The name used to reference the field. */
|
||||
tic6x_insn_field_id field_id;
|
||||
|
||||
/* The least-significant bit position in the field. */
|
||||
unsigned short low_pos;
|
||||
unsigned short low_pos;
|
||||
|
||||
/* The number of bits in the field. */
|
||||
unsigned short width;
|
||||
/* The position of the bitfield in the field. */
|
||||
unsigned short pos;
|
||||
} tic6x_bitfield;
|
||||
|
||||
/* Maximum number of subfields in composite field. */
|
||||
#define TIC6X_MAX_BITFIELDS 4
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* The name used to reference the field. */
|
||||
tic6x_insn_field_id field_id;
|
||||
unsigned int num_bitfields;
|
||||
tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS];
|
||||
} tic6x_insn_field;
|
||||
|
||||
/* Maximum number of variable fields in an instruction format. */
|
||||
|
|
@ -119,6 +141,13 @@ typedef struct
|
|||
unsigned int max_val;
|
||||
} tic6x_fixed_field;
|
||||
|
||||
/* Pseudo opcode fields position for compact instructions
|
||||
If 16 bits instruction detected, the opcode is enriched
|
||||
[DSZ/3][BR][SAT][opcode] */
|
||||
#define TIC6X_COMPACT_SAT_POS 16
|
||||
#define TIC6X_COMPACT_BR_POS 17
|
||||
#define TIC6X_COMPACT_DSZ_POS 18
|
||||
|
||||
/* Bit-masks for defining instructions present on some subset of
|
||||
processors; each indicates an instruction present on that processor
|
||||
and those that are supersets of it. The options passed to the
|
||||
|
|
@ -188,6 +217,29 @@ typedef struct
|
|||
values here. */
|
||||
#define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15)
|
||||
#define TIC6X_FLAG_PREFER(n) ((n) << 15)
|
||||
|
||||
/* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */
|
||||
#define TIC6X_FLAG_INSN16_SPRED 0x00100000
|
||||
/* 16 bits opcode ignores RS bit of fetch packet header */
|
||||
#define TIC6X_FLAG_INSN16_NORS 0x00200000
|
||||
/* 16 bits opcode only on side B */
|
||||
#define TIC6X_FLAG_INSN16_BSIDE 0x00400000
|
||||
/* 16 bits opcode ptr reg is b15 */
|
||||
#define TIC6X_FLAG_INSN16_B15PTR 0x00800000
|
||||
/* 16 bits opcode memory access modes */
|
||||
#define TIC6X_INSN16_MEM_MODE(n) ((n) << 16)
|
||||
#define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16)
|
||||
#define TIC6X_MEM_MODE_NEGATIVE 0
|
||||
#define TIC6X_MEM_MODE_POSITIVE 1
|
||||
#define TIC6X_MEM_MODE_REG_NEGATIVE 4
|
||||
#define TIC6X_MEM_MODE_REG_POSITIVE 5
|
||||
#define TIC6X_MEM_MODE_PREDECR 8
|
||||
#define TIC6X_MEM_MODE_PREINCR 9
|
||||
#define TIC6X_MEM_MODE_POSTDECR 10
|
||||
#define TIC6X_MEM_MODE_POSTINCR 11
|
||||
|
||||
#define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode)
|
||||
|
||||
#define TIC6X_NUM_PREFER 2
|
||||
|
||||
/* Maximum number of fixed fields for a particular opcode. */
|
||||
|
|
@ -230,6 +282,13 @@ typedef enum
|
|||
/* A register, from the same side as the functional unit
|
||||
selected. */
|
||||
tic6x_operand_reg,
|
||||
/* A register, from the same side as the functional unit
|
||||
selected that ignore RS header bit */
|
||||
tic6x_operand_reg_nors,
|
||||
/* A register, from the b side */
|
||||
tic6x_operand_reg_bside,
|
||||
/* A register, from the b side and from the low register set */
|
||||
tic6x_operand_reg_bside_nors,
|
||||
/* A register, that is from the other side if a cross path is
|
||||
used. */
|
||||
tic6x_operand_xreg,
|
||||
|
|
@ -241,6 +300,14 @@ typedef enum
|
|||
path is not used, and the other side if a cross path is
|
||||
used. */
|
||||
tic6x_operand_areg,
|
||||
/* The B15 register */
|
||||
tic6x_operand_b15reg,
|
||||
/* A register coded as an offset from either A16 or B16 depending
|
||||
on the value of the t bit. */
|
||||
tic6x_operand_treg,
|
||||
/* A register (A0 or B0), from the same side as the
|
||||
functional unit selected. */
|
||||
tic6x_operand_zreg,
|
||||
/* A return address register (A3 or B3), from the same side as the
|
||||
functional unit selected. */
|
||||
tic6x_operand_retreg,
|
||||
|
|
@ -252,10 +319,15 @@ typedef enum
|
|||
tic6x_operand_xregpair,
|
||||
/* A register pair, from the side of the data path selected. */
|
||||
tic6x_operand_dregpair,
|
||||
/* A register pair coded as an offset from either A16 or B16 depending
|
||||
on the value of the t bit. */
|
||||
tic6x_operand_tregpair,
|
||||
/* The literal string "irp" (case-insensitive). */
|
||||
tic6x_operand_irp,
|
||||
/* The literal string "nrp" (case-insensitive). */
|
||||
tic6x_operand_nrp,
|
||||
/* The literal string "ilc" (case-insensitive). */
|
||||
tic6x_operand_ilc,
|
||||
/* A control register. */
|
||||
tic6x_operand_ctrl,
|
||||
/* A memory reference (base and offset registers from the side of
|
||||
|
|
@ -277,7 +349,16 @@ typedef enum
|
|||
tic6x_operand_mem_deref,
|
||||
/* A functional unit name or a list thereof (for SPMASK and
|
||||
SPMASKR). */
|
||||
tic6x_operand_func_unit
|
||||
tic6x_operand_func_unit,
|
||||
/* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits
|
||||
instruction formats - spru732j.pdf Appendix F.4 */
|
||||
tic6x_operand_hw_const_minus_1,
|
||||
tic6x_operand_hw_const_0,
|
||||
tic6x_operand_hw_const_1,
|
||||
tic6x_operand_hw_const_5,
|
||||
tic6x_operand_hw_const_16,
|
||||
tic6x_operand_hw_const_24,
|
||||
tic6x_operand_hw_const_31
|
||||
} tic6x_operand_form;
|
||||
|
||||
/* Whether something is, or can be, read or written. */
|
||||
|
|
@ -375,6 +456,8 @@ typedef enum
|
|||
/* Likewise, but counting in half-words if in a header-based fetch
|
||||
packet. */
|
||||
tic6x_coding_pcrel_half,
|
||||
/* Store an unsigned PC-relative value used in compact insn */
|
||||
tic6x_coding_pcrel_half_unsigned,
|
||||
/* Encode the register number (even number for a register pair) in
|
||||
the field. When applied to a memory reference, encode the base
|
||||
register. */
|
||||
|
|
@ -388,6 +471,8 @@ typedef enum
|
|||
/* Store 0 for register B14, 1 for register B15. When applied to
|
||||
a memory reference, encode the base register. */
|
||||
tic6x_coding_areg,
|
||||
/* Compact instruction offset base register */
|
||||
tic6x_coding_reg_ptr,
|
||||
/* Store the low part of a control register address. */
|
||||
tic6x_coding_crlo,
|
||||
/* Store the high part of a control register address. */
|
||||
|
|
@ -435,7 +520,16 @@ typedef enum
|
|||
destination for load) is on side B, 0 for side A. */
|
||||
tic6x_coding_data_fu,
|
||||
/* Store 1 if the cross path is being used, 0 otherwise. */
|
||||
tic6x_coding_xpath
|
||||
tic6x_coding_xpath,
|
||||
/* L3i constant coding */
|
||||
tic6x_coding_scst_l3i,
|
||||
/* S3i constant coding */
|
||||
tic6x_coding_cst_s3i,
|
||||
/* mem offset minus 1 */
|
||||
tic6x_coding_mem_offset_minus_one,
|
||||
/* non aligned mem offset minus 1 */
|
||||
tic6x_coding_mem_offset_minus_one_noscale,
|
||||
tic6x_coding_rside
|
||||
} tic6x_coding_method;
|
||||
|
||||
/* How to generate the value of a particular field. */
|
||||
|
|
@ -530,7 +624,7 @@ typedef struct
|
|||
unsigned short isa_variants;
|
||||
|
||||
/* Flags for this instruction. */
|
||||
unsigned short flags;
|
||||
unsigned int flags;
|
||||
|
||||
/* Number of fixed fields, or fields with restricted value ranges,
|
||||
for this instruction. */
|
||||
|
|
@ -570,9 +664,15 @@ typedef enum
|
|||
CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
|
||||
#define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
|
||||
CONCAT4(tic6x_opcode_,name,_,e),
|
||||
#define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \
|
||||
CONCAT6(tic6x_opcode_,name,_,func_unit,_,format),
|
||||
#define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \
|
||||
CONCAT6(tic6x_opcode_,name,_,func_unit,_,e),
|
||||
#include "tic6x-opcode-table.h"
|
||||
#undef INSN
|
||||
#undef INSNE
|
||||
#undef INSNU
|
||||
#undef INSNUE
|
||||
tic6x_opcode_max
|
||||
} tic6x_opcode_id;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue