2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
* opcode/crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. Remove redundant instruction types. (struct argument): X_op - new field. (struct cst4_entry): Remove. (no_op_insn): Declare.
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Tomer Levi
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@ -1,3 +1,11 @@
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2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
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* opcode/crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
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Remove redundant instruction types.
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(struct argument): X_op - new field.
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(struct cst4_entry): Remove.
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(no_op_insn): Declare.
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2004-11-04 Paul Brook <paul@codesourcery.com>
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* bfdlink.h (bfd_link_info): Add default_imported_symver.
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@ -130,7 +130,7 @@ typedef enum
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/* N-bit absolute address. */
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abs16, abs32,
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/* Register relative. */
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rbase, rbase_cst4,
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rbase, rbase_dispu4,
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rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
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/* Register index. */
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rindex_disps6, rindex_disps22,
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@ -162,19 +162,13 @@ operand_type;
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#define LD_STOR_INS_INC 8
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#define STOR_IMM_INS 9
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#define CSTBIT_INS 10
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#define SYS_INS 11
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#define JMP_INS 12
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#define MUL_INS 13
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#define DIV_INS 14
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#define COP_BRANCH_INS 15
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#define COP_REG_INS 16
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#define COPS_REG_INS 17
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#define DCR_BRANCH_INS 18
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#define MMC_INS 19
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#define MMU_INS 20
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#define COP_BRANCH_INS 11
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#define COP_REG_INS 12
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#define COPS_REG_INS 13
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#define DCR_BRANCH_INS 14
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/* Maximum value supported for instruction types. */
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#define CRX_INS_MAX (1 << 5)
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#define CRX_INS_MAX (1 << 4)
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/* Mask to record an instruction type. */
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#define CRX_INS_MASK (CRX_INS_MAX - 1)
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/* Return instruction type, given instruction's attributes. */
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@ -184,42 +178,40 @@ operand_type;
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#define REG_LIST CRX_INS_MAX
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/* The operands in binary and assembly are placed in reverse order.
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load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
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#define REVERSE_MATCH (1 << 6)
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#define REVERSE_MATCH (1 << 5)
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/* Kind of displacement map used DISPU[BWD]4. */
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#define DISPUB4 (1 << 7)
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#define DISPUW4 (1 << 8)
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#define DISPUD4 (1 << 9)
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#define DISPUB4 (1 << 6)
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#define DISPUW4 (1 << 7)
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#define DISPUD4 (1 << 8)
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#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4)
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/* Printing formats, where the instruction prefix isn't consecutive. */
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#define FMT_1 (1 << 10) /* 0xF0F00000 */
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#define FMT_2 (1 << 11) /* 0xFFF0FF00 */
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#define FMT_3 (1 << 12) /* 0xFFF00F00 */
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#define FMT_4 (1 << 13) /* 0xFFF0F000 */
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#define FMT_5 (1 << 14) /* 0xFFF0FFF0 */
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#define FMT_1 (1 << 9) /* 0xF0F00000 */
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#define FMT_2 (1 << 10) /* 0xFFF0FF00 */
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#define FMT_3 (1 << 11) /* 0xFFF00F00 */
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#define FMT_4 (1 << 12) /* 0xFFF0F000 */
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#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */
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#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
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/* Indicates whether this instruction can be relaxed. */
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#define RELAXABLE (1 << 15)
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#define RELAXABLE (1 << 14)
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/* Indicates that instruction uses user registers (and not
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general-purpose registers) as operands. */
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#define USER_REG (1 << 16)
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#define USER_REG (1 << 15)
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/* Indicates that instruction can perfom a cst4 mapping. */
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#define CST4MAP (1 << 17)
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#define CST4MAP (1 << 16)
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/* Instruction shouldn't allow 'sp' usage. */
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#define NO_SP (1 << 18)
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#define NO_SP (1 << 17)
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/* Instruction shouldn't allow to push a register which is used as a rptr. */
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#define NO_RPTR (1 << 19)
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#define NO_RPTR (1 << 18)
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/* Maximum operands per instruction. */
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#define MAX_OPERANDS 5
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/* Maximum words per instruction. */
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#define MAX_WORDS 3
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/* Maximum register name length. */
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#define MAX_REGNAME_LEN 10
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/* Maximum instruction length. */
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@ -229,19 +221,23 @@ operand_type;
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/* Values defined for the flags field of a struct operand_entry. */
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/* Operand must be an unsigned number. */
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#define OPERAND_UNSIGNED (1 << 0)
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#define OP_UNSIGNED (1 << 0)
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/* Operand must be a signed number. */
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#define OPERAND_SIGNED (1 << 1)
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/* A cst4 operand. */
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#define OPERAND_CST4 (1 << 2)
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#define OP_SIGNED (1 << 1)
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/* A special arithmetic 4-bit constant operand. */
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#define OP_CST4 (1 << 2)
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/* A special load/stor 4-bit unsigned displacement operand. */
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#define OP_DISPU4 (1 << 3)
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/* Operand must be an even number. */
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#define OPERAND_EVEN (1 << 3)
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#define OP_EVEN (1 << 4)
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/* Operand is shifted right. */
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#define OPERAND_SHIFT (1 << 4)
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#define OP_SHIFT (1 << 5)
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/* Operand is shifted right and decremented. */
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#define OPERAND_SHIFT_DEC (1 << 5)
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#define OP_SHIFT_DEC (1 << 6)
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/* Operand has reserved escape sequences. */
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#define OPERAND_ESC (1 << 6)
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#define OP_ESC (1 << 7)
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/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */
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#define OP_UPPER_64KB (1 << 8)
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/* Single operand description. */
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@ -284,15 +280,15 @@ typedef struct
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/* Coprocessor register. */
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copreg cr;
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/* Constant/immediate/absolute value. */
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unsigned long int constant;
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long constant;
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/* Scaled index mode. */
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unsigned int scale;
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/* Argument type. */
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argtype type;
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/* Size of the argument (in bits) required to represent. */
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int size;
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/* Indicates whether a constant is positive or negative. */
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int signflag;
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/* The type of the expression. */
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unsigned char X_op;
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}
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argument;
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@ -363,15 +359,6 @@ reg_entry;
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/* Structure to hold a cst4 operand mapping. */
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typedef struct
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{
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/* The binary value which is written to the object file. */
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int binary;
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/* The value which is mapped. */
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int value;
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}
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cst4_entry;
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/* CRX opcode table. */
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extern const inst crx_instruction[];
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extern const int crx_num_opcodes;
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@ -396,9 +383,12 @@ extern const int crx_num_traps;
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#define NUMTRAPS crx_num_traps
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/* cst4 operand mapping. */
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extern const cst4_entry cst4_map[];
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extern const long cst4_map[];
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extern const int cst4_maps;
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/* Table of instructions with no operands. */
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extern const char* no_op_insn[];
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/* Current instruction we're assembling. */
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extern const inst *instruction;
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