include/opcode/
* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. opcodes/ * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500". * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New. (PPCVEC2, PPCTMR, E6500): New short names. (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt, mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx, lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl, lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl, lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC optional operands on sync instruction for E6500 target. bfd/ * archures.c: Add bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entryies for bfd_mach_ppc_e5500 and bfd_mach_ppc_e6500. gas/ * config/tc-ppc.c (md_show_usage): Document -me5500 and -me6500. (ppc_handle_align): Add termination nop opcode for e500mc family. * doc/as.texinfo: Document options -me5500 and -me6500. * doc/c-ppc.texi: Likewise. gas/testsuite/ * gas/ppc/e500mc64_nop.s: New test case for e500mc family termination nops. * gas/ppc/e500mc64_nop.d: Likewise. * gas/ppc/e5500_nop.s: Likewise. * gas/ppc/e5500_nop.d: Likewise. * gas/ppc/e6500_nop.s: Likewise. * gas/ppc/e6500_nop.d: Likewise. * gas/ppc/e6500.s: New. * gas/ppc/e6500.d: Likewise. * gas/ppc/ppc.exp: Run e6500, e500mc64_nop, e5500_nop, and e6500_nop.
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2012-03-10 Edmar Wienskoski <edmar@freescale.com>
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* ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
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2012-02-27 Alan Modra <amodra@gmail.com>
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* crx.h (cst4_map): Update declaration.
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/* ppc.h -- Header file for PowerPC opcode table
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Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
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2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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@ -174,6 +174,15 @@ extern const int powerpc_num_opcodes;
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/* Opcode which is supported by the e500 family */
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#define PPC_OPCODE_E500 0x100000000ull
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/* Opcode is supported by Extended Altivec Vector Unit */
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#define PPC_OPCODE_ALTIVEC2 0x200000000ull
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/* Opcode is supported by Power E6500 */
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#define PPC_OPCODE_E6500 0x400000000ull
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/* Opcode is supported by Thread management APU */
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#define PPC_OPCODE_TMR 0x800000000ull
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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