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2013-06-08 Catherine Moore <clm@codesourcery.com> * config/tc-mips.c (is_opcode_valid): Build ASE mask. (is_opcode_valid_16): Pass ase value to opcode_is_member. (append_insn): Change INSN_xxxx to ASE_xxxx. include/ 2013-06-08 Catherine Moore <clm@codesourcery.com> * opcode/mips.h (mips_opcode): Add ase field. (INSN_ASE_MASK): Delete. (INSN_DSP): Rename to ASE_DSP. Provide new value. (INSN_DSPR2): Rename to ASE_DSPR2. Provide new value. (INSN_MCU): Rename to ASE_MCU. Provide new value. (INSN_MDMX): Rename to ASE_MDMX. Provide new value. (INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value. (INSN_MT): Rename to ASE_MT. Provide new value. (INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value. (INSN_VIRT): Rename to ASE_VIRT. Provide new value. (INSN_VIRT64): Rename to ASE_VIRT64. Provide new value. (opcode_is_member): Add ase argument. Check ase. opcodes/ 2013-06-08 Catherine Moore <clm@codesourcery.com> Richard Sandiford <rdsandiford@googlemail.com> * micromips-opc.c (D32, D33, MC): Update definitions. (micromips_opcodes): Initialize ase field. * mips-dis.c (mips_arch_choice): Add ase field. (mips_arch_choices): Initialize ase field. (set_default_mips_dis_options): Declare and setup mips_ase. * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64, MT32, MC): Update definitions. (mips_builtin_opcodes): Initialize ase field.
This commit is contained in:
Richard Sandiford
parent
2f78d07f49
commit
ebf488e1ab
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@ -1,3 +1,18 @@
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2013-06-08 Catherine Moore <clm@codesourcery.com>
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* opcode/mips.h (mips_opcode): Add ase field.
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(INSN_ASE_MASK): Delete.
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(INSN_DSP): Rename to ASE_DSP. Provide new value.
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(INSN_DSPR2): Rename to ASE_DSPR2. Provide new value.
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(INSN_MCU): Rename to ASE_MCU. Provide new value.
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(INSN_MDMX): Rename to ASE_MDMX. Provide new value.
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(INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value.
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(INSN_MT): Rename to ASE_MT. Provide new value.
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(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value.
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(INSN_VIRT): Rename to ASE_VIRT. Provide new value.
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(INSN_VIRT64): Rename to ASE_VIRT64. Provide new value.
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(opcode_is_member): Add ase argument. Check ase.
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2013-05-06 Paul Brook <paul@codesourcery.com>
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include/elf/
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@ -357,6 +357,9 @@ struct mips_opcode
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/* A collection of bits describing the instruction sets of which this
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instruction or macro is a member. */
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unsigned long membership;
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/* A collection of bits describing the ASE of which this instruction
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or macro is a member. */
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unsigned long ase;
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/* A collection of bits describing the instruction sets of which this
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instruction or macro is not a member. */
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unsigned long exclusions;
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@ -733,20 +736,9 @@ static const unsigned int mips_isa_table[] =
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/* Masks used for MIPS-defined ASEs. */
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#define INSN_ASE_MASK 0x3c00f0d0
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/* DSP ASE */
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#define INSN_DSP 0x00001000
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#define INSN_DSP64 0x00002000
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/* MIPS R5900 instruction */
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#define INSN_5900 0x00004000
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/* Virtualization ASE */
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#define INSN_VIRT 0x00000080
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#define INSN_VIRT64 0x00000040
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/* MIPS-3D ASE */
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#define INSN_MIPS3D 0x00008000
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/* MIPS R4650 instruction. */
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#define INSN_4650 0x00010000
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/* LSI R4010 instruction. */
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@ -768,14 +760,6 @@ static const unsigned int mips_isa_table[] =
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/* NEC VR5500 instruction. */
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#define INSN_5500 0x02000000
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/* MDMX ASE */
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#define INSN_MDMX 0x04000000
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/* MT ASE */
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#define INSN_MT 0x08000000
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/* SmartMIPS ASE */
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#define INSN_SMARTMIPS 0x10000000
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/* DSP R2 ASE */
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#define INSN_DSPR2 0x20000000
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/* ST Microelectronics Loongson 2E. */
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#define INSN_LOONGSON_2E 0x40000000
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/* ST Microelectronics Loongson 2F. */
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@ -783,10 +767,26 @@ static const unsigned int mips_isa_table[] =
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/* Loongson 3A. */
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#define INSN_LOONGSON_3A 0x00000400
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/* RMI Xlr instruction */
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#define INSN_XLR 0x00000020
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#define INSN_XLR 0x00000020
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/* DSP ASE */
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#define ASE_DSP 0x00000001
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#define ASE_DSP64 0x00000002
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/* DSP R2 ASE */
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#define ASE_DSPR2 0x00000004
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/* MCU (MicroController) ASE */
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#define INSN_MCU 0x00000010
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#define ASE_MCU 0x00000010
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/* MDMX ASE */
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#define ASE_MDMX 0x00000020
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/* MIPS-3D ASE */
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#define ASE_MIPS3D 0x00000040
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/* MT ASE */
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#define ASE_MT 0x00000080
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/* SmartMIPS ASE */
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#define ASE_SMARTMIPS 0x00000100
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/* Virtualization ASE */
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#define ASE_VIRT 0x00000200
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#define ASE_VIRT64 0x00000400
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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@ -923,7 +923,7 @@ cpu_is_member (int cpu, unsigned int mask)
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if instruction INSN is available to the given ISA and CPU. */
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static inline bfd_boolean
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opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
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opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
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{
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if (!cpu_is_member (cpu, insn->exclusions))
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{
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@ -935,7 +935,7 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
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return TRUE;
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/* Test for ASE compatibility. */
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if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
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if ((ase & insn->ase) != 0)
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return TRUE;
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/* Test for processor-specific extensions. */
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