Add support for v850E2 and v850E2V3
This commit is contained in:
Nick Clifton
parent
cb6bfcff1a
commit
e3d36b30b4
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@ -3730,14 +3730,8 @@ case "${target}" in
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v810-*-*)
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noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
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;;
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v850-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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;;
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v850e-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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;;
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v850ea-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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v850*-*-*)
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noconfigdirs="$noconfigdirs ${libgcj}"
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;;
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vax-*-vms)
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noconfigdirs="$noconfigdirs bfd binutils gdb ld target-newlib opcodes target-libgloss ${libgcj}"
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10
configure.ac
10
configure.ac
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@ -967,14 +967,8 @@ case "${target}" in
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v810-*-*)
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noconfigdirs="$noconfigdirs bfd binutils gas gcc gdb ld target-libstdc++-v3 opcodes target-libgloss ${libgcj}"
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;;
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v850-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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;;
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v850e-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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;;
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v850ea-*-*)
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noconfigdirs="$noconfigdirs target-libgloss ${libgcj}"
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v850*-*-*)
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noconfigdirs="$noconfigdirs ${libgcj}"
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;;
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vax-*-vms)
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noconfigdirs="$noconfigdirs bfd binutils gdb ld target-newlib opcodes target-libgloss ${libgcj}"
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@ -1,3 +1,9 @@
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2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
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Ina Pandit <ina.pandit@kpitcummins.com>
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* v850.h: Add support for V850E2 and V850E2V3.
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(v850_reloc_type): Update the newly added relocations
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2010-07-20 Alan Modra <amodra@gmail.com>
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* internal.h (ELF_TBSS_SPECIAL): New macro, extracted from..
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@ -40,6 +40,11 @@
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/* v850e1 code. */
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#define E_V850E1_ARCH 0x20000000
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/* v850e2 code. */
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#define E_V850E2_ARCH 0x30000000
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/* v850e2v3 code. */
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#define E_V850E2V3_ARCH 0x40000000
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/* Flags for the st_other field. */
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#define V850_OTHER_SDA 0x10 /* Symbol had SDA relocations. */
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@ -81,6 +86,29 @@ START_RELOC_NUMBERS (v850_reloc_type)
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RELOC_NUMBER (R_V850_ALIGN, 27)
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RELOC_NUMBER (R_V850_REL32, 28)
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RELOC_NUMBER (R_V850_LO16_SPLIT_OFFSET, 29) /* For ld.bu */
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RELOC_NUMBER (R_V850_16_PCREL, 30) /* For loop */
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RELOC_NUMBER (R_V850_17_PCREL, 31) /* For br */
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RELOC_NUMBER (R_V850_23, 32) /* For 23bit ld.[w,h,hu,b,bu],st.[w,h,b] */
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RELOC_NUMBER (R_V850_32_PCREL, 33) /* For jr32, jarl32 */
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RELOC_NUMBER (R_V850_32_ABS, 34) /* For jmp32 */
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RELOC_NUMBER (R_V850_16_SPLIT_OFFSET, 35) /* For ld.bu */
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RELOC_NUMBER (R_V850_16_S1, 36) /* For ld.w, ld.h st.w st.h */
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RELOC_NUMBER (R_V850_LO16_S1, 37) /* For ld.w, ld.h st.w st.h */
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RELOC_NUMBER (R_V850_CALLT_15_16_OFFSET, 38) /* For ld.w, ld.h, ld.hu, st.w, st.h */
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RELOC_NUMBER (R_V850_32_GOTPCREL, 39) /* GLOBAL_OFFSET_TABLE from pc */
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RELOC_NUMBER (R_V850_16_GOT, 40) /* GOT ENTRY from gp */
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RELOC_NUMBER (R_V850_32_GOT, 41)
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RELOC_NUMBER (R_V850_22_PLT, 42) /* For jr */
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RELOC_NUMBER (R_V850_32_PLT, 43) /* For jr32 */
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RELOC_NUMBER (R_V850_COPY, 44)
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RELOC_NUMBER (R_V850_GLOB_DAT, 45)
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RELOC_NUMBER (R_V850_JMP_SLOT, 46)
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RELOC_NUMBER (R_V850_RELATIVE, 47)
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RELOC_NUMBER (R_V850_16_GOTOFF, 48) /* From gp */
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RELOC_NUMBER (R_V850_32_GOTOFF, 49)
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RELOC_NUMBER (R_V850_CODE, 50)
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RELOC_NUMBER (R_V850_DATA, 51) /* For loop */
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END_RELOC_NUMBERS (R_V850_max)
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@ -1,3 +1,21 @@
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2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
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Ina Pandit <ina.pandit@kpitcummins.com>
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* v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
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PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
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PROCESSOR_V850E2_ALL.
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Remove PROCESSOR_V850EA support.
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(v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
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V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
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V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
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V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
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V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
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V850_OPERAND_PERCENT.
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Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
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V850_NOT_R0.
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Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
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and V850E_PUSH_POP
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2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
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* mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
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@ -55,12 +55,18 @@ struct v850_opcode
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};
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/* Values for the processors field in the v850_opcode structure. */
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#define PROCESSOR_MASK 0x1f
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#define PROCESSOR_OPTION_EXTENSION (1 << 5) /* Enable extension opcodes. */
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#define PROCESSOR_OPTION_ALIAS (1 << 6) /* Enable alias opcodes. */
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#define PROCESSOR_V850 (1 << 0) /* Just the V850. */
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#define PROCESSOR_ALL -1 /* Any processor. */
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#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
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#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */
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#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */
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#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */
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#define PROCESSOR_ALL PROCESSOR_MASK /* Any processor. */
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#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
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#define PROCESSOR_NOT_V850 (PROCESSOR_ALL & (~ PROCESSOR_V850)) /* Any processor except the V850. */
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#define PROCESSOR_V850E1 (1 << 2) /* Just the V850E1. */
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#define PROCESSOR_V850E2 (1 << 3) /* Just the V850E2. */
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#define PROCESSOR_V850E2V3 (1 << 4) /* Just the V850E2V3. */
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#define PROCESSOR_V850E2_ALL (PROCESSOR_V850E2 | PROCESSOR_V850E2V3) /* V850E2 & V850E2V3. */
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#define SET_PROCESSOR_MASK(mask,set) ((mask) = ((mask) & ~PROCESSOR_MASK) | (set))
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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@ -74,7 +80,8 @@ extern const int v850_num_opcodes;
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struct v850_operand
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{
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/* The number of bits in the operand. */
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/* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
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/* If this value is -1 then the operand's bits are in a discontinous
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distribution in the instruction. */
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int bits;
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/* (bits >= 0): How far the operand is left shifted in the instruction. */
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@ -120,6 +127,8 @@ struct v850_operand
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/* One bit syntax flags. */
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int flags;
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int default_reloc;
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};
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/* Elements in the table are retrieved by indexing with values from
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@ -129,39 +138,70 @@ extern const struct v850_operand v850_operands[];
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/* Values defined for the flags field of a struct v850_operand. */
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/* This operand names a general purpose register */
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/* This operand names a general purpose register. */
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#define V850_OPERAND_REG 0x01
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/* This operand names a system register */
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#define V850_OPERAND_SRG 0x02
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/* This operand names a condition code used in the setf instruction */
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#define V850_OPERAND_CC 0x04
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/* This operand takes signed values */
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#define V850_OPERAND_SIGNED 0x08
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/* This operand is the ep register. */
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#define V850_OPERAND_EP 0x10
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#define V850_OPERAND_EP 0x02
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/* This operand is a PC displacement */
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#define V850_OPERAND_DISP 0x20
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/* This operand names a system register. */
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#define V850_OPERAND_SRG 0x04
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/* This is a relaxable operand. Only used for D9->D22 branch relaxing
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right now. We may need others in the future (or maybe handle them like
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promoted operands on the mn10300?) */
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#define V850_OPERAND_RELAX 0x40
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/* Prologue eilogue type instruction, V850E specific. */
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#define V850E_OPERAND_REG_LIST 0x08
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/* The register specified must not be r0 */
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#define V850_NOT_R0 0x80
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/* This operand names a condition code used in the setf instruction. */
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#define V850_OPERAND_CC 0x10
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/* push/pop type instruction, V850E specific. */
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#define V850E_PUSH_POP 0x100
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#define V850_OPERAND_FLOAT_CC 0x20
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/* This operand names a vector purpose register. */
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#define V850_OPERAND_VREG 0x40
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/* 16 bit immediate follows instruction, V850E specific. */
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#define V850E_IMMEDIATE16 0x200
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#define V850E_IMMEDIATE16 0x80
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/* hi16 bit immediate follows instruction, V850E specific. */
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#define V850E_IMMEDIATE16HI 0x100
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/* 23 bit immediate follows instruction, V850E specific. */
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#define V850E_IMMEDIATE23 0x200
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/* 32 bit immediate follows instruction, V850E specific. */
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#define V850E_IMMEDIATE32 0x400
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/* This is a relaxable operand. Only used for D9->D22 branch relaxing
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right now. We may need others in the future (or maybe handle them like
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promoted operands on the mn10300?). */
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#define V850_OPERAND_RELAX 0x800
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/* This operand takes signed values. */
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#define V850_OPERAND_SIGNED 0x1000
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/* This operand is a displacement. */
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#define V850_OPERAND_DISP 0x2000
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/* This operand is a PC displacement. */
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#define V850_PCREL 0x4000
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/* The register specified must be even number. */
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#define V850_REG_EVEN 0x8000
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/* The register specified must not be r0. */
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#define V850_NOT_R0 0x20000
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/* The register specified must not be 0. */
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#define V850_NOT_IMM0 0x40000
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/* The condition code must not be SA CONDITION. */
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#define V850_NOT_SA 0x80000
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/* The operand has '!' prefix. */
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#define V850_OPERAND_BANG 0x100000
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/* The operand has '%' prefix. */
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#define V850_OPERAND_PERCENT 0x200000
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extern int v850_msg_is_out_of_range (const char * msg);
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#endif /* V850_H */
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