elf/
Merge from mainline. 2002-04-24 Elena Zannoni <ezannoni@redhat.com> * dwarf2.h: Add DW_AT_GNU_vector. opcode/ Merge from mainline 2002-04-11 Alan Modra <amodra@bigpond.net.au> * i386.h: Add intel mode cmpsd and movsd. Put them before SSE2 insns, so that rep prefix works.
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@ -1,3 +1,9 @@
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2002-04-2 Alan Modra <amodra@bigpond.net.au>
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Merge from mainline.
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2002-04-24 Elena Zannoni <ezannoni@redhat.com>
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* dwarf2.h: Add DW_AT_GNU_vector.
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2002-02-13 Matt Fredette <fredette@netbsd.org>
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* m68k.h (EF_M68000): Define.
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@ -328,6 +328,7 @@ enum dwarf_attribute
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DW_AT_src_coords = 0x2104,
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DW_AT_body_begin = 0x2105,
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DW_AT_body_end = 0x2106,
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DW_AT_GNU_vector = 0x2107,
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/* VMS Extensions. */
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DW_AT_VMS_rtnbeg_pd_address = 0x2201
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};
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@ -1,3 +1,10 @@
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2002-04-27 Alan Modra <amodra@bigpond.net.au>
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Merge from mainline
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2002-04-11 Alan Modra <amodra@bigpond.net.au>
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* i386.h: Add intel mode cmpsd and movsd.
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Put them before SSE2 insns, so that rep prefix works.
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2002-02-25 Alan Modra <amodra@bigpond.net.au>
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* ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.
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@ -1231,6 +1231,9 @@ static const template i386_optab[] = {
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{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
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{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
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{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
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/* Intel mode string compare. */
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{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
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{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
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{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
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{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
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{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
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@ -1249,6 +1252,9 @@ static const template i386_optab[] = {
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{"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
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{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
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{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
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/* Intel mode string move. */
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{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
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{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
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{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
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{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
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{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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