Merge from mainline.
	2002-04-24  Elena Zannoni  <ezannoni@redhat.com>
	* dwarf2.h: Add DW_AT_GNU_vector.
opcode/
	Merge from mainline
	2002-04-11  Alan Modra  <amodra@bigpond.net.au>
	* i386.h: Add intel mode cmpsd and movsd.
	Put them before SSE2 insns, so that rep prefix works.
This commit is contained in:
Alan Modra 2002-04-27 12:43:32 +00:00
parent 061386e024
commit e2fa15a3ea
4 changed files with 20 additions and 0 deletions

View File

@ -1,3 +1,9 @@
2002-04-2 Alan Modra <amodra@bigpond.net.au>
Merge from mainline.
2002-04-24 Elena Zannoni <ezannoni@redhat.com>
* dwarf2.h: Add DW_AT_GNU_vector.
2002-02-13 Matt Fredette <fredette@netbsd.org>
* m68k.h (EF_M68000): Define.

View File

@ -328,6 +328,7 @@ enum dwarf_attribute
DW_AT_src_coords = 0x2104,
DW_AT_body_begin = 0x2105,
DW_AT_body_end = 0x2106,
DW_AT_GNU_vector = 0x2107,
/* VMS Extensions. */
DW_AT_VMS_rtnbeg_pd_address = 0x2201
};

View File

@ -1,3 +1,10 @@
2002-04-27 Alan Modra <amodra@bigpond.net.au>
Merge from mainline
2002-04-11 Alan Modra <amodra@bigpond.net.au>
* i386.h: Add intel mode cmpsd and movsd.
Put them before SSE2 insns, so that rep prefix works.
2002-02-25 Alan Modra <amodra@bigpond.net.au>
* ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.

View File

@ -1231,6 +1231,9 @@ static const template i386_optab[] = {
{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
/* Intel mode string compare. */
{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
@ -1249,6 +1252,9 @@ static const template i386_optab[] = {
{"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
/* Intel mode string move. */
{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },