fhandler_proc.cc(format_proc_cpuinfo): use feature test print macro
Add feature test print macro that makes feature, bit, and flag text comparison and checking easier. Handle as common former Intel only feature flags also supported on AMD. Change order and some flag names to agree with current Linux.
This commit is contained in:
Brian Inglis
Ken Brown
parent
169b9e093f
commit
dcb5d25fde
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@ -609,6 +609,8 @@ format_proc_stat (void *, char *&destbuf)
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}
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#define print(x) { bufptr = stpcpy (bufptr, (x)); }
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/* feature test bit position (0-32) and conditional print */
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#define ftcprint(feat,bitno,msg) if ((feat) & (1 << (bitno))) { print (" " msg); }
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static inline uint32_t
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get_msb (uint32_t in)
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@ -969,278 +971,170 @@ format_proc_cpuinfo (void *, char *&destbuf)
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(features1 & (1 << 0)) ? "yes" : "no",
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level);
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print ("flags\t\t:");
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if (features1 & (1 << 0))
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print (" fpu");
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if (features1 & (1 << 1))
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print (" vme");
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if (features1 & (1 << 2))
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print (" de");
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if (features1 & (1 << 3))
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print (" pse");
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if (features1 & (1 << 4))
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print (" tsc");
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if (features1 & (1 << 5))
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print (" msr");
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if (features1 & (1 << 6))
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print (" pae");
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if (features1 & (1 << 7))
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print (" mce");
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if (features1 & (1 << 8))
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print (" cx8");
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if (features1 & (1 << 9))
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print (" apic");
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if (features1 & (1 << 11))
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print (" sep");
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if (features1 & (1 << 12))
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print (" mtrr");
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if (features1 & (1 << 13))
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print (" pge");
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if (features1 & (1 << 14))
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print (" mca");
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if (features1 & (1 << 15))
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print (" cmov");
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if (features1 & (1 << 16))
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print (" pat");
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if (features1 & (1 << 17))
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print (" pse36");
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if (features1 & (1 << 18))
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print (" pn");
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if (features1 & (1 << 19))
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print (" clflush");
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if (is_intel && features1 & (1 << 21))
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print (" dts");
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if (is_intel && features1 & (1 << 22))
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print (" acpi");
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if (features1 & (1 << 23))
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print (" mmx");
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if (features1 & (1 << 24))
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print (" fxsr");
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if (features1 & (1 << 25))
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print (" sse");
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if (features1 & (1 << 26))
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print (" sse2");
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if (is_intel && (features1 & (1 << 27)))
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print (" ss");
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if (features1 & (1 << 28))
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print (" ht");
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if (is_intel)
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{
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if (features1 & (1 << 29))
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print (" tm");
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if (features1 & (1 << 30))
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print (" ia64");
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if (features1 & (1 << 31))
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print (" pbe");
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}
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/* cpuid 0x00000001 edx */
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ftcprint (features1, 0, "fpu"); /* x87 floating point */
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ftcprint (features1, 1, "vme"); /* VM enhancements */
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ftcprint (features1, 2, "de"); /* debugging extensions */
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ftcprint (features1, 3, "pse"); /* page size extensions */
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ftcprint (features1, 4, "tsc"); /* rdtsc/p */
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ftcprint (features1, 5, "msr"); /* rd/wrmsr */
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ftcprint (features1, 6, "pae"); /* phy addr extensions */
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ftcprint (features1, 7, "mce"); /* Machine check exception */
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ftcprint (features1, 8, "cx8"); /* cmpxchg8b */
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ftcprint (features1, 9, "apic"); /* APIC enabled */
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ftcprint (features1, 11, "sep"); /* sysenter/sysexit */
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ftcprint (features1, 12, "mtrr"); /* memory type range registers */
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ftcprint (features1, 13, "pge"); /* page global extension */
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ftcprint (features1, 14, "mca"); /* machine check architecture */
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ftcprint (features1, 15, "cmov"); /* conditional move */
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ftcprint (features1, 16, "pat"); /* page attribute table */
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ftcprint (features1, 17, "pse36");/* 36 bit page size extensions */
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ftcprint (features1, 18, "pn"); /* processor serial number */
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ftcprint (features1, 19, "clflush"); /* clflush instruction */
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ftcprint (features1, 21, "dts"); /* debug store */
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ftcprint (features1, 22, "acpi"); /* ACPI via MSR */
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ftcprint (features1, 23, "mmx"); /* multimedia extensions */
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ftcprint (features1, 24, "fxsr"); /* fxsave/fxrstor */
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ftcprint (features1, 25, "sse"); /* xmm */
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ftcprint (features1, 26, "sse2"); /* xmm2 */
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ftcprint (features1, 27, "ss"); /* CPU self snoop */
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ftcprint (features1, 28, "ht"); /* hyper threading */
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ftcprint (features1, 29, "tm"); /* acc automatic clock control */
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ftcprint (features1, 30, "ia64"); /* IA 64 processor */
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ftcprint (features1, 31, "pbe"); /* pending break enable */
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/* AMD cpuid 0x80000001 edx */
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if (is_amd && maxe >= 0x80000001)
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{
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cpuid (&unused, &unused, &unused, &features1, 0x80000001);
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if (features1 & (1 << 11))
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print (" syscall");
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if (features1 & (1 << 19)) /* Huh? Not in AMD64 specs. */
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print (" mp");
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if (features1 & (1 << 20))
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print (" nx");
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if (features1 & (1 << 22))
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print (" mmxext");
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if (features1 & (1 << 25))
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print (" fxsr_opt");
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if (features1 & (1 << 26))
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print (" pdpe1gb");
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if (features1 & (1 << 27))
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print (" rdtscp");
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if (features1 & (1 << 29))
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print (" lm");
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if (features1 & (1 << 30)) /* 31th bit is on. */
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print (" 3dnowext");
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if (features1 & (1 << 31)) /* 32th bit (highest) is on. */
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print (" 3dnow");
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ftcprint (features1, 11, "syscall"); /* syscall/sysret */
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ftcprint (features1, 19, "mp"); /* MP capable */
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ftcprint (features1, 20, "nx"); /* no-execute protection */
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ftcprint (features1, 22, "mmxext"); /* MMX extensions */
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ftcprint (features1, 25, "fxsr_opt"); /* fxsave/fxrstor optims */
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ftcprint (features1, 26, "pdpe1gb"); /* GB large pages */
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ftcprint (features1, 27, "rdtscp"); /* rdtscp */
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ftcprint (features1, 29, "lm"); /* long mode (x86 64) */
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ftcprint (features1, 30, "3dnowext"); /* 3DNow extensions */
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ftcprint (features1, 31, "3dnow"); /* 3DNow */
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}
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if (features2 & (1 << 0))
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print (" pni");
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if (is_intel)
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{
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if (features2 & (1 << 2))
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print (" dtes64");
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if (features2 & (1 << 3))
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print (" monitor");
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if (features2 & (1 << 4))
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print (" ds_cpl");
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if (features2 & (1 << 5))
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print (" vmx");
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if (features2 & (1 << 6))
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print (" smx");
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if (features2 & (1 << 7))
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print (" est");
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if (features2 & (1 << 8))
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print (" tm2");
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if (features2 & (1 << 9))
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print (" ssse3");
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if (features2 & (1 << 10))
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print (" cid");
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if (features2 & (1 << 12))
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print (" fma");
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}
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if (features2 & (1 << 13))
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print (" cx16");
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if (is_intel)
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{
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if (features2 & (1 << 14))
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print (" xtpr");
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if (features2 & (1 << 15))
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print (" pdcm");
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if (features2 & (1 << 18))
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print (" dca");
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if (features2 & (1 << 19))
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print (" sse4_1");
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if (features2 & (1 << 20))
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print (" sse4_2");
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if (features2 & (1 << 21))
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print (" x2apic");
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if (features2 & (1 << 22))
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print (" movbe");
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if (features2 & (1 << 23))
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print (" popcnt");
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if (features2 & (1 << 25))
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print (" aes");
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if (features2 & (1 << 26))
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print (" xsave");
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if (features2 & (1 << 27))
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print (" osxsave");
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if (features2 & (1 << 28))
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print (" avx");
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if (features2 & (1 << 29))
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print (" f16c");
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if (features2 & (1 << 30))
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print (" rdrand");
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if (features2 & (1 << 31))
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print (" hypervisor");
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}
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/* cpuid 0x00000001 ecx */
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ftcprint (features2, 0, "pni"); /* xmm3 sse3 */
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ftcprint (features2, 1, "pclmuldq"); /* pclmulqdq instruction */
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ftcprint (features2, 2, "dtes64"); /* 64-bit debug store */
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ftcprint (features2, 3, "monitor"); /* monitor/mwait support */
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ftcprint (features2, 4, "ds_cpl"); /* CPL-qual debug store */
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ftcprint (features2, 5, "vmx"); /* hardware virtualization */
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ftcprint (features2, 6, "smx"); /* safer mode extensions */
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ftcprint (features2, 7, "est"); /* enhanced speedstep */
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ftcprint (features2, 8, "tm2"); /* thermal monitor 2 */
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ftcprint (features2, 9, "ssse3"); /* supplemental sse3 */
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ftcprint (features2, 10, "cid"); /* context id */
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ftcprint (features2, 11, "sdbg"); /* silicon debug */
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ftcprint (features2, 12, "fma"); /* fused multiply add */
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ftcprint (features2, 13, "cx16"); /* cmpxchg16b instruction */
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ftcprint (features2, 14, "xtpr"); /* send task priority messages */
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ftcprint (features2, 15, "pdcm"); /* perf/debug capabilities MSR */
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ftcprint (features2, 17, "pcid"); /* process context identifiers */
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ftcprint (features2, 18, "dca"); /* direct cache access */
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ftcprint (features2, 19, "sse4_1"); /* xmm 4_1 sse 4.1 */
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ftcprint (features2, 20, "sse4_2"); /* xmm 4_2 sse 4.2 */
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ftcprint (features2, 21, "x2apic"); /* x2 APIC */
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ftcprint (features2, 22, "movbe"); /* movbe instruction */
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ftcprint (features2, 23, "popcnt"); /* popcnt instruction */
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ftcprint (features2, 25, "aes"); /* AES instructions */
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ftcprint (features2, 26, "xsave"); /* xsave/xrstor/xsetbv/xgetbv */
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ftcprint (features2, 27, "osxsave"); /* not output on Linux */
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ftcprint (features2, 28, "avx"); /* advanced vector extensions */
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ftcprint (features2, 29, "f16c"); /* 16 bit FP conversions */
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ftcprint (features2, 30, "rdrand"); /* RNG rdrand instruction */
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ftcprint (features2, 31, "hypervisor"); /* hypervisor guest */
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/* cpuid 0x80000001 ecx */
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if (maxe >= 0x80000001)
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{
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cpuid (&unused, &unused, &features1, &unused, 0x80000001);
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if (features1 & (1 << 0))
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print (" lahf_lm");
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if (features1 & (1 << 1))
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print (" cmp_legacy");
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ftcprint (features1, 0, "lahf_lm"); /* l/sahf long mode */
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ftcprint (features1, 1, "cmp_legacy"); /* HT not valid */
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if (is_amd)
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{
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if (features1 & (1 << 2))
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print (" svm");
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if (features1 & (1 << 3))
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print (" extapic");
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if (features1 & (1 << 4))
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print (" cr8_legacy");
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if (features1 & (1 << 5))
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print (" abm");
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if (features1 & (1 << 6))
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print (" sse4a");
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if (features1 & (1 << 7))
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print (" misalignsse");
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if (features1 & (1 << 8))
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print (" 3dnowprefetch");
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if (features1 & (1 << 9))
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print (" osvw");
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ftcprint (features1, 2, "svm"); /* secure VM */
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ftcprint (features1, 3, "extapic"); /* ext APIC space */
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ftcprint (features1, 4, "cr8_legacy"); /* CR8 32 bit mode */
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ftcprint (features1, 5, "abm"); /* adv bit manip lzcnt */
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ftcprint (features1, 6, "sse4a"); /* sse 4a */
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ftcprint (features1, 7, "misalignsse"); /* misaligned SSE ok */
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ftcprint (features1, 8, "3dnowprefetch"); /* 3DNow prefetch */
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ftcprint (features1, 9, "osvw"); /* OS vis workaround */
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}
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if (features1 & (1 << 10))
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print (" ibs");
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ftcprint (features1, 10, "ibs"); /* instr based sampling */
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if (is_amd)
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{
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if (features1 & (1 << 11))
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print (" sse5");
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if (features1 & (1 << 12))
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print (" skinit");
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if (features1 & (1 << 13))
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print (" wdt");
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if (features1 & (1 << 15))
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print (" lwp");
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if (features1 & (1 << 16))
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print (" fma4");
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if (features1 & (1 << 17))
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print (" tce");
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if (features1 & (1 << 19))
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print (" nodeid_msr");
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if (features1 & (1 << 21))
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print (" tbm");
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if (features1 & (1 << 22))
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print (" topoext");
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if (features1 & (1 << 23))
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print (" perfctr_core");
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if (features1 & (1 << 24))
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print (" perfctr_nb");
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if (features1 & (1 << 28))
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print (" perfctr_l2");
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ftcprint (features1, 11, "xop"); /* sse 5 extended AVX */
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ftcprint (features1, 12, "skinit"); /* skinit/stgi */
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ftcprint (features1, 13, "wdt"); /* watchdog timer */
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ftcprint (features1, 15, "lwp"); /* light weight prof */
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ftcprint (features1, 16, "fma4"); /* 4 operand MAC */
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ftcprint (features1, 17, "tce"); /* translat cache ext */
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ftcprint (features1, 19, "nodeid_msr"); /* nodeid MSR */
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ftcprint (features1, 21, "tbm"); /* trailing bit manip */
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ftcprint (features1, 22, "topoext"); /* topology ext */
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ftcprint (features1, 23, "perfctr_core"); /* core perf ctr ext */
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ftcprint (features1, 24, "perfctr_nb"); /* NB perf ctr ext */
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ftcprint (features1, 28, "perfctr_llc"); /* ll cache perf ctr */
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ftcprint (features1, 29, "mwaitx"); /* monitor/mwaitx ext */
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}
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}
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if (is_intel) /* features scattered in various CPUID levels. */
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/* features scattered in various CPUID levels. */
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/* thermal & power cpuid 0x00000006 eax ecx */
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if (maxf >= 0x06)
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{
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cpuid (&features1, &unused, &features2, &unused, 0x06);
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if (features1 & (1 << 1))
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print (" ida");
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if (features1 & (1 << 2))
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print (" arat");
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if (features2 & (1 << 3))
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print (" epb");
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ftcprint (features2, 3, "epb"); /* energy perf bias */
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cpuid (&features2, &unused, &unused, &unused, 0x0d, 1);
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if (features2 & (1 << 0))
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print (" xsaveopt");
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if (features1 & (1 << 4))
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print (" pln");
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if (features1 & (1 << 6))
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print (" pts");
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if (features1 & (1 << 0))
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print (" dtherm");
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ftcprint (features1, 0, "dtherm"); /* digital thermal sensor */
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ftcprint (features1, 1, "ida"); /* Intel dynamic acceleration */
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ftcprint (features1, 2, "arat"); /* always running APIC timer */
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ftcprint (features1, 4, "pln"); /* power limit notification */
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ftcprint (features1, 6, "pts"); /* package thermal status */
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}
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if (is_intel) /* Extended feature flags */
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/* cpuid 0x00000007 ebx */
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if (maxf >= 0x07)
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{
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cpuid (&unused, &features1, &unused, &unused, 0x07, 0);
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if (features1 & (1 << 0))
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print (" fsgsbase");
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if (features1 & (1 << 1))
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print (" tsc_adjust");
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if (features1 & (1 << 3))
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print (" bmi1");
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if (features1 & (1 << 4))
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print (" hle");
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if (features1 & (1 << 5))
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print (" avx2");
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if (features1 & (1 << 7))
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print (" smep");
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if (features1 & (1 << 8))
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print (" bmi2");
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if (features1 & (1 << 9))
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print (" erms");
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if (features1 & (1 << 10))
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print (" invpcid");
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if (features1 & (1 << 11))
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print (" rtm");
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if (features1 & (1 << 14))
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print (" mpx");
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if (features1 & (1 << 16))
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print (" avx512f");
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if (features1 & (1 << 18))
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print (" rdseed");
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if (features1 & (1 << 19))
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print (" adx");
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if (features1 & (1 << 20))
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print (" smap");
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if (features1 & (1 << 23))
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print (" clflushopt");
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if (features1 & (1 << 26))
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print (" avx512pf");
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if (features1 & (1 << 27))
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print (" avx512er");
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if (features1 & (1 << 28))
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print (" avx512cd");
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ftcprint (features1, 0, "fsgsbase"); /* rd/wr fs/gs base */
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ftcprint (features1, 1, "tsc_adjust"); /* TSC adjustment MSR 0x3B */
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ftcprint (features1, 3, "bmi1"); /* bit manip ext group 1 */
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ftcprint (features1, 4, "hle"); /* hardware lock elision */
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ftcprint (features1, 5, "avx2"); /* AVX ext instructions */
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ftcprint (features1, 7, "smep"); /* super mode exec prot */
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ftcprint (features1, 8, "bmi2"); /* bit manip ext group 2 */
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ftcprint (features1, 9, "erms"); /* enh rep movsb/stosb */
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||||
ftcprint (features1, 10, "invpcid"); /* inv proc context id */
|
||||
ftcprint (features1, 11, "rtm"); /* restricted txnal mem */
|
||||
ftcprint (features1, 14, "mpx"); /* mem prot ext */
|
||||
ftcprint (features1, 16, "avx512f"); /* vec foundation */
|
||||
ftcprint (features1, 18, "rdseed"); /* RNG rdseed instruction */
|
||||
ftcprint (features1, 19, "adx"); /* adcx/adox */
|
||||
ftcprint (features1, 20, "smap"); /* sec mode access prev */
|
||||
ftcprint (features1, 23, "clflushopt"); /* cache line flush opt */
|
||||
ftcprint (features1, 26, "avx512pf"); /* vec prefetch */
|
||||
ftcprint (features1, 27, "avx512er"); /* vec exp/recip aprx */
|
||||
ftcprint (features1, 28, "avx512cd"); /* vec conflict detect */
|
||||
}
|
||||
|
||||
/* cpuid 0x0000000d:1 eax */
|
||||
if (maxf >= 0x0d)
|
||||
{
|
||||
cpuid (&features1, &unused, &unused, &unused, 0x0d, 1);
|
||||
|
||||
ftcprint (features1, 0, "xsaveopt"); /* xsaveopt instruction */
|
||||
}
|
||||
|
||||
print ("\n");
|
||||
|
|
@ -1269,31 +1163,22 @@ format_proc_cpuinfo (void *, char *&destbuf)
|
|||
phys, virt);
|
||||
}
|
||||
|
||||
/* cpuid 0x80000007 edx */
|
||||
if (maxe >= 0x80000007) /* Advanced power management. */
|
||||
{
|
||||
cpuid (&unused, &unused, &unused, &features1, 0x80000007);
|
||||
|
||||
print ("power management:");
|
||||
if (features1 & (1 << 0))
|
||||
print (" ts");
|
||||
if (features1 & (1 << 1))
|
||||
print (" fid");
|
||||
if (features1 & (1 << 2))
|
||||
print (" vid");
|
||||
if (features1 & (1 << 3))
|
||||
print (" ttp");
|
||||
if (features1 & (1 << 4))
|
||||
print (" tm");
|
||||
if (features1 & (1 << 5))
|
||||
print (" stc");
|
||||
if (features1 & (1 << 6))
|
||||
print (" 100mhzsteps");
|
||||
if (features1 & (1 << 7))
|
||||
print (" hwpstate");
|
||||
if (features1 & (1 << 9))
|
||||
print (" cpb");
|
||||
if (features1 & (1 << 10))
|
||||
print (" eff_freq_ro");
|
||||
ftcprint (features1, 0, "ts"); /* temperature sensor */
|
||||
ftcprint (features1, 1, "fid"); /* frequency id control */
|
||||
ftcprint (features1, 2, "vid"); /* voltage id control */
|
||||
ftcprint (features1, 3, "ttp"); /* thermal trip */
|
||||
ftcprint (features1, 4, "tm"); /* hw thermal control */
|
||||
ftcprint (features1, 5, "stc"); /* sw thermal control */
|
||||
ftcprint (features1, 6, "100mhzsteps"); /* 100 MHz mult control */
|
||||
ftcprint (features1, 7, "hwpstate"); /* hw P state control */
|
||||
ftcprint (features1, 9, "cpb"); /* core performance boost */
|
||||
ftcprint (features1, 10, "eff_freq_ro"); /* ro eff freq interface */
|
||||
}
|
||||
|
||||
if (orig_affinity_mask != 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue