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git://sourceware.org/git/newlib-cygwin.git
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[AArch64] Reverting recent optimized memset().
This commit is contained in:
Marcus Shawcroft
parent
c028685518
commit
c7806ef76a
@ -1,3 +1,8 @@
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2015-07-15 Wilco Dijkstra <wdijkstr@arm.com>
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* libc/machine/aarch64/memset.S (memset):
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Revert: Rewrite of optimized memset.
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2015-07-13 Wilco Dijkstra <wdijkstr@arm.com>
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* libc/machine/aarch64/memset.S (memset):
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@ -24,37 +24,10 @@
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/*
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* Copyright (c) 2015 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Assumptions:
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*
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* ARMv8-a, AArch64, unaligned accesses
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* ARMv8-a, AArch64
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* Unaligned accesses
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*
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*/
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@ -62,20 +35,32 @@
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/* See memset-stub.c */
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#else
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#define dstin x0
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#define val x1
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#define valw w1
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#define count x2
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#define dst x3
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#define dstend x4
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#define tmp1 x5
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#define tmp1w w5
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#define tmp2 x6
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#define tmp2w w6
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#define zva_len x7
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#define zva_lenw w7
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/* By default we assume that the DC instruction can be used to zero
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data blocks more efficiently. In some circumstances this might be
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unsafe, for example in an asymmetric multiprocessor environment with
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different DC clear lengths (neither the upper nor lower lengths are
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safe to use). The feature can be disabled by defining DONT_USE_DC.
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If code may be run in a virtualized environment, then define
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MAYBE_VIRT. This will cause the code to cache the system register
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values rather than re-reading them each call. */
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#define dstin x0
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#define val w1
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#define count x2
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#define tmp1 x3
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#define tmp1w w3
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#define tmp2 x4
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#define tmp2w w4
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#define zva_len_x x5
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#define zva_len w5
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#define zva_bits_x x6
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#define A_l x7
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#define A_lw w7
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#define dst x8
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#define tmp3w w9
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#define L(l) .L ## l
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.macro def_fn f p2align=0
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.text
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@ -87,153 +72,175 @@
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def_fn memset p2align=6
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dup v0.16B, valw
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add dstend, dstin, count
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cmp count, 96
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b.hi L(set_long)
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cmp count, 16
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b.hs L(set_medium)
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mov val, v0.D[0]
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/* Set 0..15 bytes. */
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tbz count, 3, 1f
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str val, [dstin]
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str val, [dstend, -8]
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ret
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nop
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1: tbz count, 2, 2f
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str valw, [dstin]
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str valw, [dstend, -4]
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ret
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2: cbz count, 3f
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strb valw, [dstin]
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tbz count, 1, 3f
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strh valw, [dstend, -2]
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3: ret
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/* Set 17..96 bytes. */
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L(set_medium):
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str q0, [dstin]
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tbnz count, 6, L(set96)
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str q0, [dstend, -16]
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tbz count, 5, 1f
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str q0, [dstin, 16]
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str q0, [dstend, -32]
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1: ret
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.p2align 4
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/* Set 64..96 bytes. Write 64 bytes from the start and
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32 bytes from the end. */
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L(set96):
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str q0, [dstin, 16]
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stp q0, q0, [dstin, 32]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 3
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nop
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L(set_long):
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and valw, valw, 255
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bic dst, dstin, 15
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str q0, [dstin]
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cmp count, 256
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ccmp valw, 0, 0, cs
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b.eq L(try_zva)
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L(no_zva):
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sub count, dstend, dst /* Count is 16 too large. */
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add dst, dst, 16
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sub count, count, 64 + 16 /* Adjust count and bias for loop. */
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1: stp q0, q0, [dst], 64
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stp q0, q0, [dst, -32]
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L(tail64):
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subs count, count, 64
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b.hi 1b
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2: stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 3
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L(try_zva):
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mrs tmp1, dczid_el0
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tbnz tmp1w, 4, L(no_zva)
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and tmp1w, tmp1w, 4
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cmp tmp1w, 4 /* ZVA size is 64 bytes. */
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b.ne L(zva_128)
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/* Write the first and last 64 byte aligned block using stp rather
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than using DC ZVA. This is faster on some cores.
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*/
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L(zva_64):
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str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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bic dst, dst, 63
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stp q0, q0, [dst, 64]
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stp q0, q0, [dst, 96]
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sub count, dstend, dst /* Count is now 128 too large. */
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sub count, count, 128+64+64 /* Adjust count and bias for loop. */
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add dst, dst, 128
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nop
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1: dc zva, dst
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add dst, dst, 64
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subs count, count, 64
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b.hi 1b
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stp q0, q0, [dst, 0]
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stp q0, q0, [dst, 32]
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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.p2align 3
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L(zva_128):
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cmp tmp1w, 5 /* ZVA size is 128 bytes. */
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b.ne L(zva_other)
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str q0, [dst, 16]
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stp q0, q0, [dst, 32]
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stp q0, q0, [dst, 64]
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stp q0, q0, [dst, 96]
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bic dst, dst, 127
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sub count, dstend, dst /* Count is now 128 too large. */
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sub count, count, 128+128 /* Adjust count and bias for loop. */
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add dst, dst, 128
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1: dc zva, dst
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add dst, dst, 128
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subs count, count, 128
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b.hi 1b
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stp q0, q0, [dstend, -128]
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stp q0, q0, [dstend, -96]
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stp q0, q0, [dstend, -64]
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stp q0, q0, [dstend, -32]
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ret
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L(zva_other):
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mov tmp2w, 4
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lsl zva_lenw, tmp2w, tmp1w
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add tmp1, zva_len, 64 /* Max alignment bytes written. */
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cmp count, tmp1
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blo L(no_zva)
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sub tmp2, zva_len, 1
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add tmp1, dst, zva_len
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add dst, dst, 16
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subs count, tmp1, dst /* Actual alignment bytes to write. */
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bic tmp1, tmp1, tmp2 /* Aligned dc zva start address. */
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beq 2f
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1: stp q0, q0, [dst], 64
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stp q0, q0, [dst, -32]
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subs count, count, 64
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b.hi 1b
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2: mov dst, tmp1
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sub count, dstend, tmp1 /* Remaining bytes to write. */
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subs count, count, zva_len
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b.lo 4f
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3: dc zva, dst
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add dst, dst, zva_len
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subs count, count, zva_len
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b.hs 3b
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4: add count, count, zva_len
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b L(tail64)
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.size memset, . - memset
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mov dst, dstin /* Preserve return value. */
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ands A_lw, val, #255
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#ifndef DONT_USE_DC
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b.eq .Lzero_mem
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#endif
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orr A_lw, A_lw, A_lw, lsl #8
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orr A_lw, A_lw, A_lw, lsl #16
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orr A_l, A_l, A_l, lsl #32
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.Ltail_maybe_long:
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cmp count, #64
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b.ge .Lnot_short
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.Ltail_maybe_tiny:
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cmp count, #15
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b.le .Ltail15tiny
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.Ltail63:
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ands tmp1, count, #0x30
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b.eq .Ltail15
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add dst, dst, tmp1
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cmp tmp1w, #0x20
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b.eq 1f
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b.lt 2f
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stp A_l, A_l, [dst, #-48]
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1:
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stp A_l, A_l, [dst, #-32]
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2:
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stp A_l, A_l, [dst, #-16]
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.Ltail15:
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and count, count, #15
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add dst, dst, count
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stp A_l, A_l, [dst, #-16] /* Repeat some/all of last store. */
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ret
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.Ltail15tiny:
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/* Set up to 15 bytes. Does not assume earlier memory
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being set. */
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tbz count, #3, 1f
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str A_l, [dst], #8
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1:
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tbz count, #2, 1f
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str A_lw, [dst], #4
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1:
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tbz count, #1, 1f
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strh A_lw, [dst], #2
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1:
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tbz count, #0, 1f
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strb A_lw, [dst]
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1:
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ret
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/* Critical loop. Start at a new cache line boundary. Assuming
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* 64 bytes per line, this ensures the entire loop is in one line. */
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.p2align 6
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.Lnot_short:
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neg tmp2, dst
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ands tmp2, tmp2, #15
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b.eq 2f
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/* Bring DST to 128-bit (16-byte) alignment. We know that there's
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* more than that to set, so we simply store 16 bytes and advance by
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* the amount required to reach alignment. */
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sub count, count, tmp2
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stp A_l, A_l, [dst]
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add dst, dst, tmp2
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/* There may be less than 63 bytes to go now. */
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cmp count, #63
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b.le .Ltail63
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2:
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sub dst, dst, #16 /* Pre-bias. */
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sub count, count, #64
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1:
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stp A_l, A_l, [dst, #16]
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stp A_l, A_l, [dst, #32]
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stp A_l, A_l, [dst, #48]
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stp A_l, A_l, [dst, #64]!
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subs count, count, #64
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b.ge 1b
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tst count, #0x3f
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add dst, dst, #16
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b.ne .Ltail63
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ret
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#ifndef DONT_USE_DC
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/* For zeroing memory, check to see if we can use the ZVA feature to
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* zero entire 'cache' lines. */
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.Lzero_mem:
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mov A_l, #0
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cmp count, #63
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b.le .Ltail_maybe_tiny
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neg tmp2, dst
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ands tmp2, tmp2, #15
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b.eq 1f
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sub count, count, tmp2
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stp A_l, A_l, [dst]
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add dst, dst, tmp2
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cmp count, #63
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b.le .Ltail63
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1:
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/* For zeroing small amounts of memory, it's not worth setting up
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* the line-clear code. */
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cmp count, #128
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b.lt .Lnot_short
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#ifdef MAYBE_VIRT
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/* For efficiency when virtualized, we cache the ZVA capability. */
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adrp tmp2, .Lcache_clear
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ldr zva_len, [tmp2, #:lo12:.Lcache_clear]
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tbnz zva_len, #31, .Lnot_short
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cbnz zva_len, .Lzero_by_line
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mrs tmp1, dczid_el0
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tbz tmp1, #4, 1f
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/* ZVA not available. Remember this for next time. */
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mov zva_len, #~0
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str zva_len, [tmp2, #:lo12:.Lcache_clear]
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b .Lnot_short
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1:
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mov tmp3w, #4
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and zva_len, tmp1w, #15 /* Safety: other bits reserved. */
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lsl zva_len, tmp3w, zva_len
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str zva_len, [tmp2, #:lo12:.Lcache_clear]
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#else
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mrs tmp1, dczid_el0
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tbnz tmp1, #4, .Lnot_short
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mov tmp3w, #4
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and zva_len, tmp1w, #15 /* Safety: other bits reserved. */
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lsl zva_len, tmp3w, zva_len
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#endif
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.Lzero_by_line:
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/* Compute how far we need to go to become suitably aligned. We're
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* already at quad-word alignment. */
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cmp count, zva_len_x
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b.lt .Lnot_short /* Not enough to reach alignment. */
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sub zva_bits_x, zva_len_x, #1
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neg tmp2, dst
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ands tmp2, tmp2, zva_bits_x
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b.eq 1f /* Already aligned. */
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/* Not aligned, check that there's enough to copy after alignment. */
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sub tmp1, count, tmp2
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cmp tmp1, #64
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ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */
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b.lt .Lnot_short
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/* We know that there's at least 64 bytes to zero and that it's safe
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* to overrun by 64 bytes. */
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mov count, tmp1
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2:
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stp A_l, A_l, [dst]
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stp A_l, A_l, [dst, #16]
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stp A_l, A_l, [dst, #32]
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subs tmp2, tmp2, #64
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stp A_l, A_l, [dst, #48]
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add dst, dst, #64
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b.ge 2b
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/* We've overrun a bit, so adjust dst downwards. */
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add dst, dst, tmp2
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1:
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sub count, count, zva_len_x
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3:
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dc zva, dst
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add dst, dst, zva_len_x
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subs count, count, zva_len_x
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b.ge 3b
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ands count, count, zva_bits_x
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b.ne .Ltail_maybe_long
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ret
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.size memset, .-memset
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#ifdef MAYBE_VIRT
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.bss
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.p2align 2
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.Lcache_clear:
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.space 4
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#endif
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#endif /* DONT_USE_DC */
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#endif
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