From c281fc320ffa1eb231e71bc179cc884626d87e6c Mon Sep 17 00:00:00 2001 From: Thiemo Seufer Date: Tue, 6 Jun 2006 10:49:48 +0000 Subject: [PATCH] [ gas/ChangeLog ] * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. (macro_build): Update comment. (mips_ip): Allow DSP64 instructions for MIPS64R2. (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and CPU_HAS_MDMX. (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and MIPS_CPU_ASE_MDMX flags for sb1. [ gas/testsuite/ChangeLog ] * gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests. * gas/mips/mips.exp: Run DSP64 tests. [ opcodes/ChangeLog ] * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. * mips-opc.c: Add DSP64 instructions. --- include/opcode/mips.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 7ff8602c2..dd99c4d3a 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -485,16 +485,15 @@ struct mips_opcode #define INSN_ISA64R2 0x00000100 /* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x0c00f000 +#define INSN_ASE_MASK 0x1c00f000 /* DSP ASE */ #define INSN_DSP 0x00001000 +#define INSN_DSP64 0x00002000 /* MIPS 16 ASE */ -#define INSN_MIPS16 0x00002000 +#define INSN_MIPS16 0x00004000 /* MIPS-3D ASE */ -#define INSN_MIPS3D 0x00004000 -/* MDMX ASE */ -#define INSN_MDMX 0x00008000 +#define INSN_MIPS3D 0x00008000 /* Chip specific instructions. These are bitmasks. */ @@ -519,11 +518,12 @@ struct mips_opcode /* NEC VR5500 instruction. */ #define INSN_5500 0x02000000 +/* MDMX ASE */ +#define INSN_MDMX 0x04000000 /* MT ASE */ -#define INSN_MT 0x04000000 - +#define INSN_MT 0x08000000 /* SmartMIPS ASE. */ -#define INSN_SMARTMIPS 0x08000000 +#define INSN_SMARTMIPS 0x10000000 /* MIPS ISA defines, use instead of hardcoding ISA level. */