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2001-10-17 Chris Demetriou <cgd@broadcom.com>
* mips.h: Sort coprocessor instruction argument characters in comment, add a few more words of description for "H".
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2001-10-17 Chris Demetriou <cgd@broadcom.com>
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* mips.h: Sort coprocessor instruction argument characters
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in comment, add a few more words of description for "H".
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2001-10-17 Chris Demetriou <cgd@broadcom.com>
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2001-10-17 Chris Demetriou <cgd@broadcom.com>
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* mips.h (INSN_SB1): New cpu-specific instruction bit.
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* mips.h (INSN_SB1): New cpu-specific instruction bit.
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@ -209,8 +209,8 @@ struct mips_opcode
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Coprocessor instructions:
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Coprocessor instructions:
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"E" 5 bit target register (OP_*_RT)
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"E" 5 bit target register (OP_*_RT)
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"G" 5 bit destination register (OP_*_RD)
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"G" 5 bit destination register (OP_*_RD)
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"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
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"P" 5 bit performance-monitor register (OP_*_PERFREG)
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"P" 5 bit performance-monitor register (OP_*_PERFREG)
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"H" 3 bit sel field (OP_*_SEL)
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Macro instructions:
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Macro instructions:
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"A" General 32 bit expression
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"A" General 32 bit expression
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