include/opcode/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Document new VU0 operand characters. (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) (OP_REG_R5900_ACC): New mips_reg_operand_types. (INSN2_VU0_CHANNEL_SUFFIX): New macro. (mips_vu0_channel_mask): Declare. opcodes/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (print_vu0_channel): New function. (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (print_insn_args): Handle '#'. (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. * mips-opc.c (mips_vu0_channel_mask): New constant. (decode_mips_operand): Handle new VU0 operand types. (VU0, VU0CH): New macros. (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. Use "+6" rather than "G" for QMFC2 and QMTC2. gas/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.c (MAX_OPERANDS): Bump to 6. (RWARN): Bump to 0x8000000. (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) (RTYPE_R5900_ACC): New register types. (RTYPE_MASK): Include them. (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New macros. (reg_names): Include them. (mips_parse_register_1): New function, split out from... (mips_parse_register): ...here. Add a channels_ptr parameter. Look for VU0 channel suffixes when nonnull. (reg_lookup): Update the call to mips_parse_register. (mips_parse_vu0_channels): New function. (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. (mips_operand_token): Add a "channels" field to the union. Extend the comment above "ch" to OT_DOUBLE_CHAR. (mips_parse_base_start): Match -- and ++. Handle channel suffixes. (mips_parse_argument_token): Handle channel suffixes here too. (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. Handle '#' formats. (md_begin): Register $vfN and $vfI registers. (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (match_vu0_suffix_operand): New function. (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (macro): Use "+7" rather than "E" for LDQ2 and STQ2. (mips_lookup_insn): New function. (mips_ip): Use it. Allow "+K" operands to be elided at the end of an instruction. Handle '#' sequences. gas/testsuite/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric coprocessor registers. * gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d, gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests. * gas/mips/mips.exp: Run them.
This commit is contained in:
Richard Sandiford
parent
fbb49d5252
commit
b98e294936
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@ -1,3 +1,13 @@
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2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
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Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h: Document new VU0 operand characters.
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(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
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(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
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(OP_REG_R5900_ACC): New mips_reg_operand_types.
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(INSN2_VU0_CHANNEL_SUFFIX): New macro.
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(mips_vu0_channel_mask): Declare.
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2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
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@ -401,7 +401,15 @@ enum mips_operand_type {
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OP_REPEAT_PREV_REG,
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/* $pc, which has no encoding in the architectural instruction. */
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OP_PC
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OP_PC,
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/* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
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which. */
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OP_VU0_SUFFIX,
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/* Like OP_VU0_SUFFIX, but used when the operand's value has already
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been set. Any suffix used here must match the previous value. */
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OP_VU0_MATCH_SUFFIX
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};
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/* Enumerates the types of MIPS register. */
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@ -430,7 +438,19 @@ enum mips_reg_operand_type {
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/* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
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also be used in some contexts. */
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OP_REG_HW
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OP_REG_HW,
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/* Floating-point registers $vf0-$vf31. */
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OP_REG_VF,
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/* Integer registers $vi0-$vi31. */
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OP_REG_VI,
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/* R5900 VU0 registers $I, $Q, $R and $ACC. */
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OP_REG_R5900_I,
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OP_REG_R5900_Q,
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OP_REG_R5900_R,
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OP_REG_R5900_ACC
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};
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/* Base class for all operands. */
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@ -781,6 +801,26 @@ struct mips_opcode
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"Y" source register (OP_*_FS)
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"Z" source register (OP_*_FT)
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R5900 VU0 Macromode instructions:
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"+5" 5 bit floating point register (FD)
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"+6" 5 bit floating point register (FS)
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"+7" 5 bit floating point register (FT)
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"+8" 5 bit integer register (FD)
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"+9" 5 bit integer register (FS)
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"+0" 5 bit integer register (FT)
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"+K" match an existing 4-bit channel mask starting at bit 21
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"+L" 2-bit channel index starting at bit 21
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"+M" 2-bit channel index starting at bit 23
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"+N" match an existing 2-bit channel index starting at bit 0
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"+f" 15 bit immediate for VCALLMS
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"+g" 5 bit signed immediate for VIADDI
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"+m" $ACC register (syntax only)
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"+q" $Q register (syntax only)
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"+r" $R register (syntax only)
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"+y" $I register (syntax only)
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"#+" "++" decorator in ($reg++) sequence
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"#-" "--" decorator in (--$reg) sequence
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DSP ASE usage:
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"2" 2 bit unsigned immediate for byte align (OP_*_BP)
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"3" 3 bit unsigned immediate (OP_*_SA3)
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@ -846,15 +886,15 @@ struct mips_opcode
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Characters used so far, for quick reference when adding more:
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"1234567890"
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"%[]<>(),+:'@!$*&\~"
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"%[]<>(),+:'@!#$*&\~"
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"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
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"abcdefghijklopqrstuvwxz"
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Extension character sequences used so far ("+" followed by the
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following), for quick reference when adding more:
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"1234"
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"ABCEFGHIJPQSXZ"
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"abcijpstxz"
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"1234567890"
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"ABCEFGHIJKLMNPQSXZ"
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"abcfgijmpqrstxyz"
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*/
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/* These are the bits which may be set in the pinfo field of an
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@ -960,6 +1000,8 @@ struct mips_opcode
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#define INSN2_COND_BRANCH 0x00001000
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/* Reads from $16. This is true of the MIPS16 0x6500 nop. */
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#define INSN2_READ_GPR_16 0x00002000
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/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */
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#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
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/* Masks used to mark instructions to indicate which MIPS ISA level
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they were introduced in. INSN_ISA_MASK masks an enumeration that
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@ -1490,6 +1532,7 @@ enum
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Many instructions are short hand for other instructions (i.e., The
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jal <register> instruction is short for jalr <register>). */
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extern const struct mips_operand mips_vu0_channel_mask;
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extern const struct mips_operand *decode_mips_operand (const char *);
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extern const struct mips_opcode mips_builtin_opcodes[];
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extern const int bfd_mips_num_builtin_opcodes;
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