* mips/crt0.S: Configure processor based on .MIPS.abiflags.
Remove FPU availability check, just use the pre-processor flags to indicicate what the user wanted. * mips/abiflags.S: New file. * mips/regs.S (SR_MSA): Define macro. * mips/mti32.ld: Place .MIPS.abiflags and wrap in marker symbols. * mips/mti64.ld: Likewise. * mips/mti64_64.ld: Likewise. * mips/mti64_n32.ld: Likewise.
This commit is contained in:
Corinna Vinschen
parent
d37bfe1da2
commit
b3281dd194
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@ -1,3 +1,16 @@
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2014-11-28 Jaydeep Patil <jaydeep.patil@imgtec.com>
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Matthew Fortune <Matthew.Fortune@imgtec.com>
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* mips/crt0.S: Configure processor based on .MIPS.abiflags.
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Remove FPU availability check, just use the pre-processor flags
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to indicicate what the user wanted.
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* mips/abiflags.S: New file.
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* mips/regs.S (SR_MSA): Define macro.
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* mips/mti32.ld: Place .MIPS.abiflags and wrap in marker symbols.
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* mips/mti64.ld: Likewise.
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* mips/mti64_64.ld: Likewise.
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* mips/mti64_n32.ld: Likewise.
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2014-11-26 Matthew Fortune <Matthew.Fortune@imgtec.com>
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* mips/crt0.S: Remove .set noreorder throughout.
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@ -0,0 +1,82 @@
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/*
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* abiflags.S - MIPS ABI flags.
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*/
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/* Values for the xxx_size bytes of an ABI flags structure. */
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#define AFL_REG_NONE 0x00 /* No registers. */
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#define AFL_REG_32 0x01 /* 32-bit registers. */
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#define AFL_REG_64 0x02 /* 64-bit registers. */
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#define AFL_REG_128 0x03 /* 128-bit registers. */
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/* Masks for the ases word of an ABI flags structure. */
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#define AFL_ASE_DSP 0x00000001 /* DSP ASE. */
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#define AFL_ASE_DSPR2 0x00000002 /* DSP R2 ASE. */
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#define AFL_ASE_EVA 0x00000004 /* Enhanced VA Scheme. */
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#define AFL_ASE_MCU 0x00000008 /* MCU (MicroController) ASE. */
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#define AFL_ASE_MDMX 0x00000010 /* MDMX ASE. */
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#define AFL_ASE_MIPS3D 0x00000020 /* MIPS-3D ASE. */
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#define AFL_ASE_MT 0x00000040 /* MT ASE. */
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#define AFL_ASE_SMARTMIPS 0x00000080 /* SmartMIPS ASE. */
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#define AFL_ASE_VIRT 0x00000100 /* VZ ASE. */
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#define AFL_ASE_MSA 0x00000200 /* MSA ASE. */
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#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */
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#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */
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#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */
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/* Values for the isa_ext word of an ABI flags structure. */
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#define AFL_EXT_XLR 1 /* RMI Xlr instruction. */
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#define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */
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#define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */
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#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */
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#define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */
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#define AFL_EXT_5900 6 /* MIPS R5900 instruction. */
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#define AFL_EXT_4650 7 /* MIPS R4650 instruction. */
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#define AFL_EXT_4010 8 /* LSI R4010 instruction. */
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#define AFL_EXT_4100 9 /* NEC VR4100 instruction. */
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#define AFL_EXT_3900 10 /* Toshiba R3900 instruction. */
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#define AFL_EXT_10000 11 /* MIPS R10000 instruction. */
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#define AFL_EXT_SB1 12 /* Broadcom SB-1 instruction. */
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#define AFL_EXT_4111 13 /* NEC VR4111/VR4181 instruction. */
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#define AFL_EXT_4120 14 /* NEC VR4120 instruction. */
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#define AFL_EXT_5400 15 /* NEC VR5400 instruction. */
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#define AFL_EXT_5500 16 /* NEC VR5500 instruction. */
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#define AFL_EXT_LOONGSON_2E 17 /* ST Microelectronics Loongson 2E. */
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#define AFL_EXT_LOONGSON_2F 18 /* ST Microelectronics Loongson 2F. */
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/* Values defined for Tag_GNU_MIPS_ABI_FP. */
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#define Val_GNU_MIPS_ABI_FP_ANY 0 /* Not tagged or not using any ABIs affected by the differences. */
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#define Val_GNU_MIPS_ABI_FP_DOUBLE 1 /* Using hard-float -mdouble-float. */
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#define Val_GNU_MIPS_ABI_FP_SINGLE 2 /* Using hard-float -msingle-float. */
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#define Val_GNU_MIPS_ABI_FP_SOFT 3 /* Using soft-float. */
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#define Val_GNU_MIPS_ABI_FP_OLD_64 4 /* Using -mips32r2 -mfp64. */
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#define Val_GNU_MIPS_ABI_FP_XX 5 /* Using -mfpxx */
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#define Val_GNU_MIPS_ABI_FP_64 6 /* Using -mips32r2 -mfp64. */
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#define Val_GNU_MIPS_ABI_MSA_ANY 0 /* Not tagged or not using any ABIs affected by the differences. */
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#define Val_GNU_MIPS_ABI_MSA_128 1 /* Using 128-bit MSA. */
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/* MIPS ABI flags structure */
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.struct 0
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ABIFlags_version:
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.struct ABIFlags_version + 2
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ABIFlags_isa_level:
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.struct ABIFlags_isa_level + 1
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ABIFlags_isa_rev:
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.struct ABIFlags_isa_rev + 1
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ABIFlags_gpr_size:
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.struct ABIFlags_gpr_size + 1
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ABIFlags_cpr1_size:
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.struct ABIFlags_cpr1_size + 1
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ABIFlags_cpr2_size:
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.struct ABIFlags_cpr2_size + 1
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ABIFlags_fp_abi:
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.struct ABIFlags_fp_abi + 1
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ABIFlags_isa_ext:
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.struct ABIFlags_isa_ext + 4
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ABIFlags_ases:
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.struct ABIFlags_ases + 4
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ABIFlags_flags1:
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.struct ABIFlags_flags1 + 4
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ABIFlags_flags2:
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.struct ABIFlags_flags2 + 4
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/*> EOF abiflags.S <*/
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@ -14,12 +14,16 @@
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* they apply.
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*/
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/* This file does not use any floating-point ABI. */
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.gnu_attribute 4,0
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#ifdef __mips16
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/* This file contains 32 bit assembly code. */
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.set nomips16
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#endif
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#include "regs.S"
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#include "abiflags.S"
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/*
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* Set up some room for a stack. We just grab a chunk of memory.
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@ -82,45 +86,86 @@ _start:
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# endif
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# endif
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#endif
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li v0, STATUS_MASK
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mtc0 v0, C0_SR
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mtc0 zero, C0_CAUSE
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/* Clear Cause register. */
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mtc0 zero,C0_CAUSE
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nop
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/* Avoid hazard from FPU enable and other SR changes. */
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LA (t0, hardware_hazard_hook)
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beq t0,zero,1f
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jalr t0
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/* Read MIPS_abiflags structure and set status/config registers
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accordingly. */
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.weak __MIPS_abiflags_start
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.weak __MIPS_abiflags_end
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LA (t0,__MIPS_abiflags_start)
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LA (t1,__MIPS_abiflags_end)
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addiu t1,t1,-24
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move v0,zero /* Mask for C0_SR. */
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/* Branch to 1f is the .MIPS.abiflags section is not 24 bytes. This
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indicates it is either missing or corrupt. */
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bne t0,t1,1f
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/* Check isa_level. */
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lbu t1,ABIFlags_isa_level(t0)
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sltu v1,t1,3 /* Is MIPS < 3? */
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xori t1,t1,64 /* Is MIPS64? */
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beq v1,zero,4f
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li v1,SR_PE
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or v0,v0,v1 /* Enable soft reset. */
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4:
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li v1,(SR_KX|SR_SX|SR_UX)
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bne t1,zero,5f
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or v0,v0,v1 /* Enable extended addressing. */
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5:
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/* Check fp_abi. */
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lbu t1,ABIFlags_fp_abi(t0)
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xori t1,t1,Val_GNU_MIPS_ABI_FP_SOFT
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li v1,SR_CU1
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beq t1,zero,2f /* Skip MSA and cpr1_size checks. */
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or v0,v0,v1 /* Enable co-processor 1. */
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/* Check cpr1_size. */
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lbu t1,ABIFlags_cpr1_size(t0)
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xori t1,t1,AFL_REG_64
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li v1,SR_FR
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bne t1,zero,3f
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or v0,v0,v1 /* Enable 64-bit FPU registers. */
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3:
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/* Check ases. */
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lw t1,ABIFlags_ases(t0)
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andi t1,t1,AFL_ASE_MSA
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li v1,SR_FR
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beq t1,zero,2f
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or v0,v0,v1 /* Enable 64-bit FPU registers. */
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li v1,SR_MSA
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.set push
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.set mips32
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mtc0 v1,C0_CONFIG,5 /* Enable MSA. */
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.set pop
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b 2f
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1:
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/* Check for FPU presence. Don't check if we know that soft_float is
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being used. (This also avoids illegal instruction exceptions.) */
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#ifndef __mips_soft_float
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li t2,0xAAAA5555
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mtc1 t2,fp0 /* write to FPR 0 */
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mtc1 zero,fp1 /* write to FPR 1 */
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mfc1 t0,fp0
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mfc1 t1,fp1
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nop
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bne t0,t2,1f /* check for match */
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bne t1,zero,1f /* double check */
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j 2f /* FPU is present. */
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/* MIPS_abiflags structure is not available. Set status/config
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registers based on flags defined by compiler. */
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#ifdef __mips_soft_float
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li v0,(STATUS_MASK-(STATUS_MASK & SR_CU1))
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#else
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li v0,STATUS_MASK
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#endif
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1:
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/* FPU is not present. Set status register to say that. */
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li v0, (STATUS_MASK-(STATUS_MASK & SR_CU1))
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mtc0 v0, C0_SR
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2:
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/* Set C0_SR, */
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mtc0 v0,C0_SR
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nop
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/* Avoid hazard from FPU disable. */
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/* Avoid hazard from C0_SR changes. */
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LA (t0, hardware_hazard_hook)
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beq t0,zero,2f
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jalr t0
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2:
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/* Fix high bits, if any, of the PC so that exception handling
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doesn't get confused. */
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/* Fix high bits, if any, of the PC so that exception handling doesn't get
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confused. */
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LA (v0, 3f)
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jr v0
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3:
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@ -93,6 +93,11 @@ SECTIONS
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}
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. = .;
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.MIPS.abiflags : {
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__MIPS_abiflags_start = .;
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*(.MIPS.abiflags)
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__MIPS_abiflags_end = .;
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}
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.rodata : {
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*(.rdata)
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*(.rodata)
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@ -137,6 +142,7 @@ SECTIONS
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*(COMMON)
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}
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. = ALIGN(4);
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PROVIDE (end = .);
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_end = .;
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@ -95,6 +95,11 @@ SECTIONS
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}
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. = .;
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.MIPS.abiflags : {
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__MIPS_abiflags_start = .;
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*(.MIPS.abiflags)
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__MIPS_abiflags_end = .;
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}
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.rodata : {
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*(.rdata)
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*(.rodata)
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@ -139,6 +144,7 @@ SECTIONS
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*(COMMON)
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}
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. = ALIGN(4);
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PROVIDE (end = .);
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_end = .;
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@ -98,6 +98,11 @@ SECTIONS
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}
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. = .;
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.MIPS.abiflags : {
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__MIPS_abiflags_start = .;
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*(.MIPS.abiflags)
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__MIPS_abiflags_end = .;
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}
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.rodata : {
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*(.rdata)
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*(.rodata)
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@ -142,6 +147,7 @@ SECTIONS
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*(COMMON)
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}
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. = ALIGN(4);
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PROVIDE (end = .);
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_end = .;
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@ -98,6 +98,11 @@ SECTIONS
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}
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. = .;
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.MIPS.abiflags : {
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__MIPS_abiflags_start = .;
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*(.MIPS.abiflags)
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__MIPS_abiflags_end = .;
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}
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.rodata : {
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*(.rdata)
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*(.rodata)
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*(COMMON)
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}
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. = ALIGN(4);
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PROVIDE (end = .);
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_end = .;
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@ -98,6 +98,8 @@
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#define SR_SX 0x00000040 /* Supervisor extended addressing enabled */
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#define SR_UX 0x00000020 /* User extended addressing enabled */
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#define SR_MSA 0x08000000 /* MSA ASE */
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/* Standard (R4000) cache operations. Taken from "MIPS R4000
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Microprocessor User's Manual" 2nd edition: */
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