Add support for ARM half-precision conversion instructions.

This commit is contained in:
Catherine Moore 2008-11-18 15:45:05 +00:00
parent aa677662af
commit b1230ddef7
4 changed files with 18 additions and 0 deletions

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@ -1,3 +1,7 @@
2008-11-18 Catherine Moore <clm@codesourcery.com>
* arm.h (Tag_ABI_FP_16bit_format): Define.
2008-11-14 Nathan Sidwell <nathan@codesourcery.com> 2008-11-14 Nathan Sidwell <nathan@codesourcery.com>
* internal.h (struct elf_segment_map): Add header_size field. * internal.h (struct elf_segment_map): Add header_size field.

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@ -272,6 +272,12 @@ enum
Tag_ABI_optimization_goals, Tag_ABI_optimization_goals,
Tag_ABI_FP_optimization_goals, Tag_ABI_FP_optimization_goals,
/* 32 is generic. */ /* 32 is generic. */
Tag_undefined33 = 33,
Tag_CPU_unaligned_access,
Tag_undefined35,
Tag_VFP_HP_extension,
Tag_undefined37,
Tag_ABI_FP_16bit_format = 38,
}; };
#endif #endif

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@ -1,3 +1,8 @@
2008-11-18 Catherine Moore <clm@codesourcery.com>
* arm.h (FPU_NEON_FP16): New.
(FPU_ARCH_NEON_FP16): New.
2008-11-06 Chao-ying Fu <fu@mips.com> 2008-11-06 Chao-ying Fu <fu@mips.com>
* mips.h: Doucument '1' for 5-bit sync type. * mips.h: Doucument '1' for 5-bit sync type.

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@ -65,6 +65,7 @@
#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */ #define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */
#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */ #define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */
#define FPU_VFP_EXT_D32 0x00400000 /* Registers D16-D31. */ #define FPU_VFP_EXT_D32 0x00400000 /* Registers D16-D31. */
#define FPU_NEON_FP16 0x00200000 /* Half-precision extensions. */
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E) /* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@ -139,6 +140,8 @@
#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) #define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
#define FPU_ARCH_NEON_FP16 \
ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_NEON_FP16)
#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) #define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)