* hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args
by 'f'.
This commit is contained in:
Jeff Law
parent
b7fdf3c074
commit
9b2c866771
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@ -1,5 +1,8 @@
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Sat Aug 28 00:25:25 1999 Jerry Quinn <jquinn@nortelnetworks.com>
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* hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args
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by 'f'.
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* hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
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Add supporting args.
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@ -70,9 +70,9 @@ struct pa_opcode
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In the args field, the following characters are unused:
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' "# & - / :;< > @'
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' BC LM U YZ[\] '
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' de gh lm { } '
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' "# & - / 34 6789:;< > @'
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' BC JKLM XYZ[\] '
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' de gh lm y { } '
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Here are all the characters:
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@ -85,7 +85,6 @@ Kinds of operands:
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b integer register field at 10.
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t integer register field at 31.
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a integer register field at 10 and 15 (for PERMH)
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y floating point register field at 31
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5 5 bit immediate at 15.
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s 2 bit space specifier at 17.
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S 3 bit space specifier at 18.
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@ -99,6 +98,49 @@ Kinds of operands:
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W 17 bit branch displacement (PC relative)
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z 17 bit branch displacement (just a number, not an address)
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Also these:
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. 2 bit shift amount at 25
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* 4 bit shift amount at 25
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p 5 bit shift count at 26 (to support the SHD instruction) encoded as
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31-p
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~ 6 bit shift count at 20,22:26 encoded as 63-~.
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P 5 bit bit position at 26
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T 5 bit field length at 31 (encoded as 32-T)
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A 13 bit immediate at 18 (to support the BREAK instruction)
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^ like b, but describes a control register
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! sar (cr11) register
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D 26 bit immediate at 31 (to support the DIAG instruction)
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$ 9 bit immediate at 28 (to support POPBTS)
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v 3 bit Special Function Unit identifier at 25
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O 20 bit Special Function Unit operation split between 15 bits at 20
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and 5 bits at 31
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o 15 bit Special Function Unit operation at 20
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2 22 bit Special Function Unit operation split between 17 bits at 20
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and 5 bits at 31
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1 15 bit Special Function Unit operation split between 10 bits at 20
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and 5 bits at 31
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0 10 bit Special Function Unit operation split between 5 bits at 20
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and 5 bits at 31
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u 3 bit coprocessor unit identifier at 25
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F Source Floating Point Operand Format Completer encoded 2 bits at 20
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I Source Floating Point Operand Format Completer encoded 1 bits at 20
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(for 0xe format FP instructions)
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G Destination Floating Point Operand Format Completer encoded 2 bits at 18
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H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
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(very similar to 'F')
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r 5 bit immediate value at 31 (for the break instruction)
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(very similar to V above, except the value is unsigned instead of
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low_sign_ext)
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R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
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(same as r above, except the value is in a different location)
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U 10 bit immediate value at 15 (for SSM, RSM on pa2.0)
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Q 5 bit immediate value at 10 (a bit position specified in
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the bb instruction. It's the same as r above, except the
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value is in a different location)
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Completer operands all have 'c' as the prefix:
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cx indexed load completer.
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@ -160,64 +202,24 @@ Condition operands all have '?' as the prefix:
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?u unit conditions
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?U 64 bit unit conditions
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Also these:
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Floating point registers all have 'f' as a prefix:
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ft target register at 31
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fT target register with L/R halves at 31
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fa operand 1 register at 10
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fA operand 1 register with L/R halves at 10
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fb operand 2 register at 15
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fB operand 2 register with L/R halves at 15
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fC operand 3 register with L/R halves at 16:18,21:23
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. 2 bit shift amount at 25
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* 4 bit shift amount at 25
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p 5 bit shift count at 26 (to support the SHD instruction) encoded as
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31-p
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~ 6 bit shift count at 20,22:26 encoded as 63-~.
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P 5 bit bit position at 26
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q 6 bit bit position at 20,22:26
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T 5 bit field length at 31 (encoded as 32-T)
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% 6 bit field length at 23,27:31 (variable extract/deposit)
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| 6 bit field length at 19,27:31 (fixed extract/deposit)
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A 13 bit immediate at 18 (to support the BREAK instruction)
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^ like b, but describes a control register
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! sar (cr11) register
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D 26 bit immediate at 31 (to support the DIAG instruction)
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$ 9 bit immediate at 28 (to support POPBTS)
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Float registers for fmpyadd and fmpysub:
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f 3 bit Special Function Unit identifier at 25
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O 20 bit Special Function Unit operation split between 15 bits at 20
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and 5 bits at 31
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o 15 bit Special Function Unit operation at 20
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2 22 bit Special Function Unit operation split between 17 bits at 20
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and 5 bits at 31
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1 15 bit Special Function Unit operation split between 10 bits at 20
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and 5 bits at 31
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0 10 bit Special Function Unit operation split between 5 bits at 20
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and 5 bits at 31
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u 3 bit coprocessor unit identifier at 25
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F Source Floating Point Operand Format Completer encoded 2 bits at 20
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I Source Floating Point Operand Format Completer encoded 1 bits at 20
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(for 0xe format FP instructions)
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G Destination Floating Point Operand Format Completer encoded 2 bits at 18
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fi mult operand 1 register at 10
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fj mult operand 2 register at 15
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fk mult target register at 20
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fl add/sub operand register at 25
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fm add/sub target register at 31
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r 5 bit immediate value at 31 (for the break instruction)
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(very similar to V above, except the value is unsigned instead of
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low_sign_ext)
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R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
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(same as r above, except the value is in a different location)
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U 10 bit immediate value at 15 (for SSM, RSM on pa2.0)
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Q 5 bit immediate value at 10 (a bit position specified in
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the bb instruction. It's the same as r above, except the
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value is in a different location)
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And these (PJH) for PA-89 F.P. registers and instructions:
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v a 't' operand type extended to handle L/R register halves.
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E a 'b' operand type extended to handle L/R register halves.
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X an 'x' operand type extended to handle L/R register halves.
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J a 'b' operand type further extended to handle extra 1.1 registers
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K a 'x' operand type further extended to handle extra 1.1 registers
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4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
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6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
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7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
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8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
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9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
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H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
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(very similar to 'F')
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*/
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@ -546,63 +548,63 @@ static const struct pa_opcode pa_opcodes[] =
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/* Floating Point Coprocessor Instructions */
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{ "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),v", pa10},
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{ "fldwx", 0x24000000, 0xfc001f80, "cxx(b),v", pa10},
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{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),y", pa10},
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{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),y", pa10},
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{ "fstwx", 0x24000200, 0xfc001f80, "cxv,x(s,b)", pa10},
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{ "fstwx", 0x24000200, 0xfc001f80, "cxv,x(b)", pa10},
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{ "fstdx", 0x2c000200, 0xfc001fc0, "cxy,x(s,b)", pa10},
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{ "fstdx", 0x2c000200, 0xfc001fc0, "cxy,x(b)", pa10},
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{ "fstqx", 0x3c000200, 0xfc001fc0, "cxy,x(s,b)", pa10},
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{ "fstqx", 0x3c000200, 0xfc001fc0, "cxy,x(b)", pa10},
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{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),v", pa10},
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{ "fldws", 0x24001000, 0xfc001f80, "cm5(b),v", pa10},
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{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),y", pa10},
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{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),y", pa10},
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{ "fstws", 0x24001200, 0xfc001f80, "cmv,5(s,b)", pa10},
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{ "fstws", 0x24001200, 0xfc001f80, "cmv,5(b)", pa10},
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{ "fstds", 0x2c001200, 0xfc001fc0, "cmy,5(s,b)", pa10},
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{ "fstds", 0x2c001200, 0xfc001fc0, "cmy,5(b)", pa10},
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{ "fstqs", 0x3c001200, 0xfc001fc0, "cmy,5(s,b)", pa10},
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{ "fstqs", 0x3c001200, 0xfc001fc0, "cmy,5(b)", pa10},
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{ "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v", pa10},
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{ "fadd", 0x38000600, 0xfc00e720, "IJ,K,v", pa10},
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{ "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v", pa10},
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{ "fsub", 0x38002600, 0xfc00e720, "IJ,K,v", pa10},
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{ "fmpy", 0x30004600, 0xfc00e7e0, "FE,X,v", pa10},
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{ "fmpy", 0x38004600, 0xfc00e720, "IJ,K,v", pa10},
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{ "fdiv", 0x30006600, 0xfc00e7e0, "FE,X,v", pa10},
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{ "fdiv", 0x38006600, 0xfc00e720, "IJ,K,v", pa10},
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{ "fsqrt", 0x30008000, 0xfc1fe7e0, "FE,v", pa10},
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{ "fsqrt", 0x38008000, 0xfc1fe720, "FJ,v", pa10},
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{ "fabs", 0x30006000, 0xfc1fe7e0, "FE,v", pa10},
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{ "fabs", 0x38006000, 0xfc1fe720, "FJ,v", pa10},
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{ "frem", 0x30008600, 0xfc00e7e0, "FE,X,v", pa10},
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{ "frem", 0x38008600, 0xfc00e720, "FJ,K,v", pa10},
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{ "frnd", 0x3000a000, 0xfc1fe7e0, "FE,v", pa10},
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{ "frnd", 0x3800a000, 0xfc1fe720, "FJ,v", pa10},
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{ "fcpy", 0x30004000, 0xfc1fe7e0, "FE,v", pa10},
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{ "fcpy", 0x38004000, 0xfc1fe720, "FJ,v", pa10},
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{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGE,v", pa10},
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{ "fcnvff", 0x38000200, 0xfc1f8720, "FGJ,v", pa10},
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{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGE,v", pa10},
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{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGJ,v", pa10},
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{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGE,v", pa10},
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{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGJ,v", pa10},
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{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGE,v", pa10},
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{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGJ,v", pa10},
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{ "fmpyfadd", 0xb8000000, 0xfc000020, "IJ,K,3,v", pa20, FLAG_STRICT},
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{ "fmpynfadd", 0xb8000020, 0xfc000020, "IJ,K,3,v", pa20, FLAG_STRICT},
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{ "fneg", 0x3000c000, 0xfc1fe7e0, "FE,v", pa20, FLAG_STRICT},
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{ "fneg", 0x3800c000, 0xfc1fe720, "IJ,v", pa20, FLAG_STRICT},
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{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "FE,v", pa20, FLAG_STRICT},
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{ "fnegabs", 0x3800e000, 0xfc1fe720, "IJ,v", pa20, FLAG_STRICT},
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{ "fcmp", 0x30000400, 0xfc00e7e0, "F?fE,X", pa10},
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{ "fcmp", 0x38000400, 0xfc00e720, "I?fJ,K", pa10},
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{ "xmpyu", 0x38004700, 0xfc00e720, "J,K,v", pa11},
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{ "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8", pa11},
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{ "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8", pa11},
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{ "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10},
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{ "fldwx", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10},
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{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10},
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{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10},
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{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10},
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{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10},
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{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10},
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{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10},
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{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10},
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{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10},
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{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10},
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{ "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10},
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{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10},
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{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10},
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{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10},
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{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10},
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{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10},
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{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10},
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{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10},
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{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10},
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{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
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{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10},
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{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
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{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10},
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{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
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{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10},
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{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
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{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10},
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{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10},
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{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10},
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{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10},
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{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10},
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{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
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{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10},
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{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10},
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{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10},
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{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10},
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{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10},
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{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10},
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{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10},
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{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10},
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{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10},
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{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10},
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{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10},
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{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10},
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{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10},
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{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
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{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
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{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
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{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
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{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
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{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
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{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10},
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{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10},
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{ "xmpyu", 0x38004700, 0xfc00e720, "fA,fB,fT", pa11},
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{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11},
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{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11},
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{ "ftest", 0x30002420, 0xffffffff, "", pa10},
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{ "fid", 0x30000000, 0xffffffff, "", pa11},
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@ -613,10 +615,10 @@ static const struct pa_opcode pa_opcodes[] =
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/* Assist Instructions */
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{ "spop0", 0x10000000, 0xfc000600, "f,ON", pa10},
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{ "spop1", 0x10000200, 0xfc000600, "f,oNt", pa10},
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{ "spop2", 0x10000400, 0xfc000600, "f,1Nb", pa10},
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{ "spop3", 0x10000600, 0xfc000600, "f,0Nx,b", pa10},
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{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10},
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{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10},
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{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10},
|
||||
{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10},
|
||||
{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10},
|
||||
{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10},
|
||||
{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10},
|
||||
|
|
|
|||
Loading…
Reference in New Issue