RISC-V: Fix floating-point environment support for soft float

We don't have floating-point exception or non-default rounding mode
support for the RISC-V soft-float environment, `feraiseexcept' and
`fesetround' do nothing unless the `__riscv_flen' macro has been set.
Therefore following ISO C language requirements[1] only define macros
for soft float that correspond to actually supported floating-point
environment features, removing failures from GCC testing such as:

FAIL: gcc.dg/torture/fp-int-convert-timode-3.c   -O0  execution test
FAIL: gcc.dg/torture/fp-int-convert-timode-4.c   -O0  execution test

References:

[1] "Programming languages -- C", ISO/IEC 9899:2023, working draft --
    September 3, 2022, Section 7.6 "Floating-point environment <fenv.h>"

Fixes: 7040b2de0883 ("Add RISC-V port for libm")
Signed-off-by: Maciej W. Rozycki <macro@embecosm.com>

newlib/libc/machine/riscv/sys/fenv.h

@@ -14,6 +14,8 @@
 
 #include <stddef.h>
 
+#if __riscv_flen
+
 /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA:
  * Version 2.1", Section 8.2, "Floating-Point Control and Status
  * Register":
@@ -69,6 +71,13 @@
  * floating-point unit."
  */
 
+#else /* !__riscv_flen */
+
+#define FE_ALL_EXCEPT   0x00000000
+#define FE_TONEAREST    0x00000000
+
+#endif /* !__riscv_flen */
+
 typedef size_t fenv_t;
 typedef size_t fexcept_t;
 extern const fenv_t fe_dfl_env;