diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index ec236b3d5..cb547e3be 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2001-10-17  Chris Demetriou  <cgd@broadcom.com>
+
+	* mips.h (INSN_SB1): New cpu-specific instruction bit.
+	(OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
+	if cpu is CPU_SB1.
+
 2001-10-17  matthew green  <mrg@redhat.com>
 
 	* ppc.h (PPC_OPCODE_BOOKE64): Fix typo.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 901c67728..b7a0fed88 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -328,6 +328,8 @@ struct mips_opcode
 #define INSN_3900                 0x00080000
 /* MIPS R10000 instruction.  */
 #define INSN_10000                0x00100000
+/* Broadcom SB-1 instruction.  */
+#define INSN_SB1                  0x00200000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -378,7 +380,8 @@ struct mips_opcode
 	 && ((insn)->membership & INSN_4100) != 0)			\
      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)	\
      || ((cpu == CPU_R10000 || cpu == CPU_R12000)			\
-	 && ((insn)->membership & INSN_10000) != 0))
+	 && ((insn)->membership & INSN_10000) != 0)			\
+     || (cpu == CPU_SB1  && ((insn)->membership & INSN_SB1) != 0))
 
 /* This is a list of macro expanded instructions.