2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
* opcode/crx.h (operand_type): Remove redundant types i3, i4, i5, i8, i12. Add new unsigned immediate types us3, us4, us5, us16.
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@ -1,3 +1,9 @@
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2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
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* opcode/crx.h (operand_type): Remove redundant types i3, i4,
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i5, i8, i12.
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Add new unsigned immediate types us3, us4, us5, us16.
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2004-10-21 H.J. Lu <hongjiu.lu@intel.com>
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PR 463
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@ -136,12 +136,20 @@ argtype;
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typedef enum
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{
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dummy, cst4, disps9,
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i3, i4, i5, i8, i12, i16, i32,
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/* Immediate operands. */
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i16, i32,
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/* Unsigned immediate operands. */
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us3, us4, us5, us16,
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/* Signed displacement operands. */
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d5, d9, d17, d25, d33,
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/* Absolute operands. */
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abs16, abs32,
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/* Register relative operands. */
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rbase, rbase_cst4,
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rbase_dispu8, rbase_dispu12, rbase_dispu16, rbase_dispu28, rbase_dispu32,
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/* Index operands. */
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rbase_ridx_scl2_dispu6, rbase_ridx_scl2_dispu22,
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/* Register and processor register operands. */
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regr, regr8, copregr,copregr8,copsregr,
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/* Not an operand. */
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nulloperand,
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@ -390,7 +398,5 @@ extern const inst *instruction;
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/* Replace all appearances of 'long long int' with LONGLONG. */
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typedef long long int LONGLONG;
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typedef unsigned long long ULONGLONG;
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/* A mask for the upper 31 bits of a 64 bits type. */
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#define UPPER31_MASK 0xFFFFFFFE00000000LL
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#endif /* _CRX_H_ */
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