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2008-08-14 Jie Zhang <jie.zhang@analog.com>

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* bfin/Makefile.in: (top_srcdir): Define.
        (mkinstalldirs): Define.
        (BOARD_SCRIPTS): Define.
        (BOARD_LDFLAGS): Define.
        (BOARD_BSP): Define.
        (BOARD_CRT0S): Define.
        (BOARD_OBJS): Define.
        (BOARD_TEST): Define.
        (BOARD_INSTALL): Define.
        (INCLUDES): Add -I$(srcdir)/include.
        (all): Add ${BOARD_CRT0S} and ${BOARD_BSP}.
        (.c.S): Remove target.
        (crt0.o): New target.
        (basiccrt.o): Likewise.
        (basiccrtb.o): Likewise.
        (basiccrts.o): Likewise.
        (basiccrt561.o, basiccrt561s.o, basiccrt561b.o): Likewise
        (clean mostlyclean): Remove ${BOARD_BSP}.
        (install): Depend on ${BOARD_INSTALL}.
        (install-sim): Reformat.
        (install-board): New target.
        * bfin/basiccrt.S: Remove useless __ADSPBF561_COREB__ in
        workaround code for 05000229.
        * bfin/syscalls.c (do_syscall): Use `EXCPT 0' instead of
        `RAISE 0' for syscall.
        * bfin/basiccrt.S: New file.
        * bfin/bf5*ld: New file.
        * bfin/bfin-common-mc.ld: New file.
        * bfin/bfin-common-sc.ld: New file.
        * bfin/include/blackfin.h: New file.
        * bfin/include/cdefBF5*.h: New file.
        * bfin/include/cdef_LPBlackfin.h: New file.
        * bfin/include/cdefblackfin.h: New file.
        * bfin/include/cplb.h: New file.
        * bfin/include/cplbtab.h: New file.
        * bfin/include/defBF5*.h: New files.
        * bfin/include/def_LPBlackfin.h: New files.
        * bfin/include/defblackfin.h: New file.
        * bfin/include/sys/_adi_platform.h: New file.
        * bfin/include/sys/anomaly_macros_rtl.h: New file.
        * bfin/include/sys/excause.h: New file.
        * bfin/include/sys/exception.h: New file.
        * bfin/include/sys/mc_typedef.h: New file.
        * bfin/include/sys/platform.h: New file.
        * bfin/include/sys/pll.h: New file.
        * bfin/include/sysreg.h: New file.
        * libnosys/configure.in (MISSING_SYSCALL_NAMES): Don't define
        for bfin.
        * libnosys/configure: Regenerate.
This commit is contained in:
Jeff Johnston 2008-08-14 22:00:47 +00:00
parent d434b57f86
commit 84132c9d9f
89 changed files with 47803 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
libgloss/ChangeLog
View File

@ -1,3 +1,55 @@
2008-08-14 Jie Zhang <jie.zhang@analog.com>
* bfin/Makefile.in: (top_srcdir): Define.
(mkinstalldirs): Define.
(BOARD_SCRIPTS): Define.
(BOARD_LDFLAGS): Define.
(BOARD_BSP): Define.
(BOARD_CRT0S): Define.
(BOARD_OBJS): Define.
(BOARD_TEST): Define.
(BOARD_INSTALL): Define.
(INCLUDES): Add -I$(srcdir)/include.
(all): Add ${BOARD_CRT0S} and ${BOARD_BSP}.
(.c.S): Remove target.
(crt0.o): New target.
(basiccrt.o): Likewise.
(basiccrtb.o): Likewise.
(basiccrts.o): Likewise.
(basiccrt561.o, basiccrt561s.o, basiccrt561b.o): Likewise
(clean mostlyclean): Remove ${BOARD_BSP}.
(install): Depend on ${BOARD_INSTALL}.
(install-sim): Reformat.
(install-board): New target.
* bfin/basiccrt.S: Remove useless __ADSPBF561_COREB__ in
workaround code for 05000229.
* bfin/syscalls.c (do_syscall): Use `EXCPT 0' instead of
`RAISE 0' for syscall.
* bfin/basiccrt.S: New file.
* bfin/bf5*ld: New file.
* bfin/bfin-common-mc.ld: New file.
* bfin/bfin-common-sc.ld: New file.
* bfin/include/blackfin.h: New file.
* bfin/include/cdefBF5*.h: New file.
* bfin/include/cdef_LPBlackfin.h: New file.
* bfin/include/cdefblackfin.h: New file.
* bfin/include/cplb.h: New file.
* bfin/include/cplbtab.h: New file.
* bfin/include/defBF5*.h: New files.
* bfin/include/def_LPBlackfin.h: New files.
* bfin/include/defblackfin.h: New file.
* bfin/include/sys/_adi_platform.h: New file.
* bfin/include/sys/anomaly_macros_rtl.h: New file.
* bfin/include/sys/excause.h: New file.
* bfin/include/sys/exception.h: New file.
* bfin/include/sys/mc_typedef.h: New file.
* bfin/include/sys/platform.h: New file.
* bfin/include/sys/pll.h: New file.
* bfin/include/sysreg.h: New file.
* libnosys/configure.in (MISSING_SYSCALL_NAMES): Don't define
for bfin.
* libnosys/configure: Regenerate.
2008-07-17 Ken Werner <ken.werner@de.ibm.com>
* spu/syscalls.c: Check and set the errno value.

88
libgloss/bfin/Makefile.in
View File

@ -7,6 +7,7 @@ srcdir = @srcdir@
objdir = .
srcroot = $(srcdir)/../..
objroot = $(objdir)/../..
top_srcdir = @top_srcdir@
prefix = @prefix@
exec_prefix = @exec_prefix@
@ -29,6 +30,8 @@ MULTISUBDIR =
SHELL = /bin/sh
mkinstalldirs = $(SHELL) $(top_srcdir)/../../mkinstalldirs
CC = @CC@
AS = @AS@
@ -56,14 +59,32 @@ SIM_OBJS = syscalls.o
SIM_TEST = sim-test
SIM_INSTALL = install-sim
# Here is all of the development board stuff
# BF531, BF532, BF533, BF537
BOARD_SCRIPTS = bfin-common-sc.ld bfin-common-mc.ld \
bf522.ld bf523.ld bf524.ld bf525.ld bf526.ld bf527.ld \
bf531.ld bf532.ld bf533.ld \
bf534.ld bf536.ld bf537.ld \
bf538.ld bf539.ld \
bf542.ld bf544.ld bf547.ld bf548.ld bf549.ld \
bf561.ld bf561a.ld bf561b.ld bf561m.ld
BOARD_LDFLAGS =
BOARD_BSP = # We actually use libnosys.a
BOARD_CRT0S = basiccrt.o basiccrts.o
BOARD_CRT0S += basiccrt561.o basiccrt561s.o basiccrt561b.o
BOARD_OBJS =
BOARD_TEST =
BOARD_INSTALL = install-board
# Host specific makefile fragment comes in here.
@host_makefile_frag@
INCLUDES += -I$(srcdir)/include
#
# build a test program for each target board. Just trying to get
# it to link is a good test, so we ignore all the errors for now.
#
all: ${SIM_CRT0} ${SIM_BSP}
all: ${SIM_CRT0} ${SIM_BSP} ${BOARD_CRT0S} ${BOARD_BSP}
#
# here's where we build the board support packages for each target
@ -75,20 +96,75 @@ ${SIM_BSP}: ${OBJS} ${SIM_OBJS}
#
#
#
.c.S:
${CC} ${CFLAGS_FOR_TARGET} -c $<
crt0.o: crt0.S
basiccrt.o: basiccrt.S
ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
$(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -o $@ -c $<
else
$(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf532-any -o $@ -c $<
endif
basiccrts.o: basiccrt.S
ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
$(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -o $@ -c $<
else
$(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf532-any -o $@ -c $<
endif
basiccrt561.o: basiccrt.S
ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
$(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-none -o $@ -c $<
else
$(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-any -o $@ -c $<
endif
basiccrt561s.o: basiccrt.S
ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
$(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-none -o $@ -c $<
else
$(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-any -o $@ -c $<
endif
basiccrt561b.o: basiccrt.S
ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
$(CC) -D__ADSPBF561_COREB__ $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-none -o $@ -c $<
else
$(CC) -D__ADSPBF561_COREB__ $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-any -o $@ -c $<
endif
clean mostlyclean:
rm -f a.out core *.i *.o $(SIM_BSP)
rm -f a.out core *.i *.o ${SIM_BSP} ${BOARD_BSP}
distclean maintainer-clean realclean: clean
rm -f Makefile config.status *~
.PHONY: install info install-info clean-info
install: ${SIM_INSTALL}
install: ${SIM_INSTALL} ${BOARD_INSTALL}
install-sim:
set -e; for x in ${SIM_CRT0} ${SIM_BSP} ${SIM_SCRIPTS}; do ${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; done
for x in ${SIM_CRT0} ${SIM_BSP} ${SIM_SCRIPTS}; do \
${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; \
done
install-board:
for x in ${BOARD_CRT0S} ${BOARD_BSP}; do \
${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; \
done
-if [ -z "${MULTISUBDIR}" ]; then \
for x in ${BOARD_SCRIPTS}; do \
${INSTALL_DATA} ${srcdir}/$$x $(DESTDIR)${tooldir}/lib/$$x; \
done; \
${mkinstalldirs} ${DESTDIR}${tooldir}/include; \
for i in ${srcdir}/include/*.h; do \
${INSTALL_DATA} $$i ${DESTDIR}${tooldir}/include/`basename $$i`; \
done; \
${mkinstalldirs} ${DESTDIR}${tooldir}/include/sys; \
for i in ${srcdir}/include/sys/*.h; do \
${INSTALL_DATA} $$i ${DESTDIR}${tooldir}/include/sys/`basename $$i`; \
done; \
else true; fi
doc:
info:

586
libgloss/bfin/basiccrt.S Normal file
View File

@ -0,0 +1,586 @@
/*
* Basic startup code for Blackfin processor
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
// basic startup code which
// - turns the cycle counter on
// - loads up FP & SP (both supervisor and user)
// - initialises the device drivers (FIOCRT)
// - calls monstartup to set up the profiling routines (PROFCRT)
// - calls the C++ startup (CPLUSCRT)
// - initialises argc/argv (FIOCRT/normal)
// - calls _main
// - calls _exit (which calls monexit to dump accumulated prof data (PROFCRT))
// - defines dummy IO routines (!FIOCRT)
#include <sys/platform.h>
#include <cplb.h>
#include <sys/anomaly_macros_rtl.h>
#define IVBh (EVT0 >> 16)
#define IVBl (EVT0 & 0xFFFF)
#define UNASSIGNED_VAL 0
#define UNASSIGNED_FILL 0
// just IVG15
#define INTERRUPT_BITS 0x400
#if defined(_ADI_THREADS) || \
!defined(__ADSPLPBLACKFIN__) || defined(__ADSPBF561__) || defined(__ADSPBF566__)
#define SET_CLOCK_SPEED 0
#else
#define SET_CLOCK_SPEED 1
#endif
#if SET_CLOCK_SPEED == 1
#include <sys/pll.h>
#define SET_CLK_MSEL 0x16
#define SET_CLK_DF 0
#define SET_CLK_LOCK_COUNT 0x300
#define SET_CLK_CSEL 0
#define SET_CLK_SSEL 5
/*
** CLKIN == 27MHz on the EZ-Kits.
** D==0 means CLKIN is passed to PLL without dividing.
** MSEL==0x16 means VCO==27*0x16 == 594MHz
** CSEL==0 means CCLK==VCO == 594MHz
** SSEL==5 means SCLK==VCO/5 == 118MHz
*/
#endif
#ifdef __ADSPBF561_COREB__
.section .b.text,"ax",@progbits
.align 2;
.global __coreb_start;
.type __coreb_start, STT_FUNC;
__coreb_start:
#else
.text;
.align 2;
.global __start;
.type __start, STT_FUNC;
__start:
#endif
#if WA_05000109
// Avoid Anomaly ID 05000109.
# define SYSCFG_VALUE 0x30
R1 = SYSCFG_VALUE;
SYSCFG = R1;
#endif
#if WA_05000229
// Avoid Anomaly 05-00-0229: DMA5_CONFIG and SPI_CTL not cleared on reset.
R1 = 0x400;
#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
P0.L = SPI0_CTL & 0xFFFF;
P0.H = SPI0_CTL >> 16;
W[P0] = R1.L;
#else
P0.L = SPI_CTL & 0xFFFF;
P0.H = SPI_CTL >> 16;
W[P0] = R1.L;
#endif
P0.L = DMA5_CONFIG & 0xFFFF;
P0.H = DMA5_CONFIG >> 16;
R1 = 0;
W[P0] = R1.L;
#endif
// Zap loop counters to zero, to make sure that
// hw loops are disabled - it could be really baffling
// if the counters and bottom regs are set, and we happen
// to run into them.
R7 = 0;
LC0 = R7;
LC1 = R7;
// Clear the DAG Length regs too, so that it's safe to
// use I-regs without them wrapping around.
L0 = R7;
L1 = R7;
L2 = R7;
L3 = R7;
// Zero ITEST_COMMAND and DTEST_COMMAND
// (in case they have crud in them and
// does a write somewhere when we enable cache)
I0.L = (ITEST_COMMAND & 0xFFFF);
I0.H = (ITEST_COMMAND >> 16);
I1.L = (DTEST_COMMAND & 0xFFFF);
I1.H = (DTEST_COMMAND >> 16);
R7 = 0;
[I0] = R7;
[I1] = R7;
// It seems writing ITEST_COMMAND from SDRAM with icache enabled
// needs SSYNC.
#ifdef __BFIN_SDRAM
SSYNC;
#else
CSYNC;
#endif
// Initialise the Event Vector table.
P0.H = IVBh;
P0.L = IVBl;
// Install __unknown_exception_occurred in EVT so that
// there is defined behaviour.
P0 += 2*4; // Skip Emulation and Reset
P1 = 13;
R1.L = __unknown_exception_occurred;
R1.H = __unknown_exception_occurred;
LSETUP (L$ivt,L$ivt) LC0 = P1;
L$ivt: [P0++] = R1;
// Set IVG15's handler to be the start of the mode-change
// code. Then, before we return from the Reset back to user
// mode, we'll raise IVG15. This will mean we stay in supervisor
// mode, and continue from the mode-change point., but at a
// much lower priority.
P1.H = L$supervisor_mode;
P1.L = L$supervisor_mode;
[P0] = P1;
// Initialise the stack.
// Note: this points just past the end of the section.
// First write should be with [--SP].
#ifdef __BFIN_SDRAM
SP.L = __end + 0x400000 - 12;
SP.H = __end + 0x400000 - 12;
#else
#ifdef __ADSPBF561_COREB__
SP.L=__coreb_stack_end - 12;
SP.H=__coreb_stack_end - 12;
#else
SP.L=__stack_end - 12;
SP.H=__stack_end - 12;
#endif
#endif
usp = sp;
// We're still in supervisor mode at the moment, so the FP
// needs to point to the supervisor stack.
FP = SP;
// And make space for incoming "parameters" for functions
// we call from here:
SP += -12;
// Zero out bss section
#ifdef __BFIN_SDRAM
R0.L = ___bss_start;
R0.H = ___bss_start;
R1.L = __end;
R1.H = __end;
#else
#ifdef __ADSPBF561_COREB__
R0.L = __coreb_bss_start;
R0.H = __coreb_bss_start;
R1.L = __coreb_bss_end;
R1.H = __coreb_bss_end;
#else
R0.L = __bss_start;
R0.H = __bss_start;
R1.L = __bss_end;
R1.H = __bss_end;
#endif
#endif
R2 = R1 - R0;
R1 = 0;
#ifdef __ADSPBF561_COREB__
CALL.X __coreb_memset;
#else
CALL.X _memset;
#endif
R0 = INTERRUPT_BITS;
R0 <<= 5; // Bits 0-4 not settable.
// CALL.X __install_default_handlers;
R4 = R0; // Save modified list
R0 = SYSCFG; // Enable the Cycle counter
BITSET(R0,1);
SYSCFG = R0;
#if WA_05000137
// Avoid anomaly #05000137
// Set the port preferences of DAG0 and DAG1 to be
// different; this gives better performance when
// performing dual-dag operations on SDRAM.
P0.L = DMEM_CONTROL & 0xFFFF;
P0.H = DMEM_CONTROL >> 16;
R0 = [P0];
BITSET(R0, 12);
BITCLR(R0, 13);
[P0] = R0;
CSYNC;
#endif
// Reinitialise data areas in RAM from ROM, if MemInit's
// been used.
// CALL.X _mi_initialize;
#if defined(__ADSPLPBLACKFIN__)
#if SET_CLOCK_SPEED == 1
#if 0
// Check if this feature is enabled, i.e. ___clk_ctrl is defined to non-zero
P0.L = ___clk_ctrl;
P0.H = ___clk_ctrl;
R0 = MAX_IN_STARTUP;
R1 = [P0];
R0 = R0 - R1;
CC = R0;
IF CC JUMP L$clock_is_set;
#endif
// Investigate whether we are a suitable revision
// for boosting the system clocks.
// speed.
P0.L = DSPID & 0xFFFF;
P0.H = DSPID >> 16;
R0 = [P0];
R0 = R0.L (Z);
CC = R0 < 2;
IF CC JUMP L$clock_is_set;
// Set the internal Voltage-Controlled Oscillator (VCO)
R0 = SET_CLK_MSEL (Z);
R1 = SET_CLK_DF (Z);
R2 = SET_CLK_LOCK_COUNT (Z);
CALL.X __pll_set_system_vco;
// Set the Core and System clocks
R0 = SET_CLK_CSEL (Z);
R1 = SET_CLK_SSEL (Z);
CALL.X __pll_set_system_clocks;
L$clock_is_set:
#endif
#endif /* ADSPLPBLACKFIN */
#if defined(__ADSPBF561__) || defined(__ADSPBF566__)
// Initialise the multi-core data tables.
// A dummy function will be called if we are not linking with
// -multicore
// CALL.X __mc_data_initialise;
#endif
#if 0
// Write the cplb exception handler to the EVT if approprate and
// initialise the CPLBs if they're needed. couldn't do
// this before we set up the stacks.
P2.H = ___cplb_ctrl;
P2.L = ___cplb_ctrl;
R0 = CPLB_ENABLE_ANY_CPLBS;
R6 = [P2];
R0 = R0 & R6;
CC = R0;
IF !CC JUMP L$no_cplbs;
#if !defined(_ADI_THREADS)
P1.H = __cplb_hdr;
P1.L = __cplb_hdr;
P0.H = IVBh;
P0.L = IVBl;
[P0+12] = P1; // write exception handler
#endif /* _ADI_THREADS */
R0 = R6;
CALL.X __cplb_init;
#endif
L$no_cplbs:
// Enable interrupts
STI R4; // Using the mask from default handlers
RAISE 15;
// Move the processor into user mode.
P0.L=L$still_interrupt_in_ipend;
P0.H=L$still_interrupt_in_ipend;
RETI=P0;
L$still_interrupt_in_ipend:
rti; // keep doing 'rti' until we've 'finished' servicing all
// interrupts of priority higher than IVG15. Normally one
// would expect to only have the reset interrupt in IPEND
// being serviced, but occasionally when debugging this may
// not be the case - if restart is hit when servicing an
// interrupt.
//
// When we clear all bits from IPEND, we'll enter user mode,
// then we'll automatically jump to supervisor_mode to start
// servicing IVG15 (which we will 'service' for the whole
// program, so that the program is in supervisor mode.
//
// Need to do this to 'finish' servicing the reset interupt.
L$supervisor_mode:
[--SP] = RETI; // re-enables the interrupt system
R0.L = UNASSIGNED_VAL;
R0.H = UNASSIGNED_VAL;
#if UNASSIGNED_FILL
R2=R0;
R3=R0;
R4=R0;
R5=R0;
R6=R0;
R7=R0;
P0=R0;
P1=R0;
P2=R0;
P3=R0;
P4=R0;
P5=R0;
#endif
// Push a RETS and Old FP onto the stack, for sanity.
[--SP]=R0;
[--SP]=R0;
// Make sure the FP is sensible.
FP = SP;
// And leave space for incoming "parameters"
SP += -12;
#ifdef PROFCRT
CALL.X monstartup; // initialise profiling routines
#endif /* PROFCRT */
#ifndef __ADSPBF561_COREB__
CALL.X __init;
R0.L = __fini;
R0.H = __fini;
CALL.X _atexit;
#endif
#if !defined(_ADI_THREADS)
#ifdef FIOCRT
// FILE IO provides access to real command-line arguments.
CALL.X __getargv;
r1.l=__Argv;
r1.h=__Argv;
#else
// Default to having no arguments and a null list.
R0=0;
#ifdef __ADSPBF561_COREB__
R1.L=L$argv_coreb;
R1.H=L$argv_coreb;
#else
R1.L=L$argv;
R1.H=L$argv;
#endif
#endif /* FIOCRT */
#endif /* _ADI_THREADS */
// At long last, call the application program.
#ifdef __ADSPBF561_COREB__
CALL.X _coreb_main;
#else
CALL.X _main;
#endif
#if !defined(_ADI_THREADS)
#ifndef __ADSPBF561_COREB__
CALL.X _exit; // passing in main's return value
#endif
#endif
#ifdef __ADSPBF561_COREB__
.size __coreb_start, .-__coreb_start
#else
.size __start, .-__start
#endif
.align 2
.type __unknown_exception_occurred, STT_FUNC;
__unknown_exception_occurred:
// This function is invoked by the default exception
// handler, if it does not recognise the kind of
// exception that has occurred. In other words, the
// default handler only handles some of the system's
// exception types, and it does not expect any others
// to occur. If your application is going to be using
// other kinds of exceptions, you must replace the
// default handler with your own, that handles all the
// exceptions you will use.
//
// Since there's nothing we can do, we just loop here
// at what we hope is a suitably informative label.
IDLE;
CSYNC;
JUMP __unknown_exception_occurred;
RTS;
.size __unknown_exception_occurred, .-__unknown_exception_occurred
#if defined(__ADSPLPBLACKFIN__)
#if SET_CLOCK_SPEED == 1
/*
** CLKIN == 27MHz on the EZ-Kits.
** D==0 means CLKIN is passed to PLL without dividing.
** MSEL==0x16 means VCO==27*0x16 == 594MHz
** CSEL==0 means CCLK==VCO == 594MHz
** SSEL==5 means SCLK==VCO/5 == 118MHz
*/
// int pll_set_system_clocks(int csel, int ssel)
// returns 0 for success, -1 for error.
.align 2
.type __pll_set_system_clocks, STT_FUNC;
__pll_set_system_clocks:
P0.H = PLL_DIV >> 16;
P0.L = PLL_DIV & 0xFFFF;
R2 = W[P0] (Z);
// Plant CSEL and SSEL
R0 <<= 16;
R0.L = (4 << 8) | 2; // 2 bits, at posn 4
R1 <<= 16;
R1.L = 4; // 4 bits, at posn 0
R2 = DEPOSIT(R2, R0);
#if defined(__WORKAROUND_DREG_COMP_LATENCY)
// Work around anomaly 05-00-0209 which affects the DEPOSIT
// instruction (and the EXTRACT, SIGNBITS, and EXPADJ instructions)
// if the previous instruction created any of its operands
NOP;
#endif
R2 = DEPOSIT(R2, R1);
W[P0] = R2;
SSYNC;
RTS;
.size __pll_set_system_clocks, .-__pll_set_system_clocks
// int pll_set_system_vco(int msel, int df, lockcnt)
.align 2
.type __pll_set_system_vco, STT_FUNC;
__pll_set_system_vco:
P0.H = PLL_CTL >> 16;
P0.L = PLL_CTL & 0xFFFF;
R3 = W[P0] (Z);
P2 = R3; // Save copy
R3 >>= 1; // Drop old DF
R1 = ROT R1 BY -1; // Move DF into CC
R3 = ROT R3 BY 1; // and into ctl space.
R0 <<= 16; // Set up pattern reg
R0.L = (9<<8) | 6; // (6 bits at posn 9)
R1 = P2; // Get the old version
R3 = DEPOSIT(R3, R0);
CC = R1 == R3; // and if we haven't changed
IF CC JUMP L$done; // Anything, return
CC = R2 == 0; // Use default lockcount if
IF CC JUMP L$wakeup; // user one is zero.
P2.H = PLL_LOCKCNT >> 16;
P2.L = PLL_LOCKCNT & 0xFFFF;
W[P2] = R2; // Set the lock counter
L$wakeup:
P2.H = SIC_IWR >> 16;
P2.L = SIC_IWR & 0xFFFF;
R2 = [P2];
BITSET(R2, 0); // enable PLL Wakeup
[P2] = R2;
W[P0] = R3; // Update PLL_CTL
SSYNC;
CLI R2; // Avoid unnecessary interrupts
IDLE; // Wait until PLL has locked
STI R2; // Restore interrupts.
L$done:
RTS;
.size __pll_set_system_vco, .-__pll_set_system_vco
#endif
#endif /* ADSPLPBLACKFIN */
#ifdef __ADSPBF561_COREB__
.section .b.text,"ax",@progbits
.type __coreb_memset, STT_FUNC
__coreb_memset:
P0 = R0 ; /* P0 = address */
P2 = R2 ; /* P2 = count */
R3 = R0 + R2; /* end */
CC = R2 <= 7(IU);
IF CC JUMP .Ltoo_small;
R1 = R1.B (Z); /* R1 = fill char */
R2 = 3;
R2 = R0 & R2; /* addr bottom two bits */
CC = R2 == 0; /* AZ set if zero. */
IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
.Laligned:
P1 = P2 >> 2; /* count = n/4 */
R2 = R1 << 8; /* create quad filler */
R2.L = R2.L + R1.L(NS);
R2.H = R2.L + R1.H(NS);
P2 = R3;
LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
.Lquad_loop:
[P0++] = R2;
CC = P0 == P2;
IF !CC JUMP .Lbytes_left;
RTS;
.Lbytes_left:
R2 = R3; /* end point */
R3 = P0; /* current position */
R2 = R2 - R3; /* bytes left */
P2 = R2;
.Ltoo_small:
CC = P2 == 0; /* Check zero count */
IF CC JUMP .Lfinished; /* Unusual */
.Lbytes:
LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
.Lbyte_loop:
B[P0++] = R1;
.Lfinished:
RTS;
.Lforce_align:
CC = BITTST (R0, 0); /* odd byte */
R0 = 4;
R0 = R0 - R2;
P1 = R0;
R0 = P0; /* Recover return address */
IF !CC JUMP .Lskip1;
B[P0++] = R1;
.Lskip1:
CC = R2 <= 2; /* 2 bytes */
P2 -= P1; /* reduce count */
IF !CC JUMP .Laligned;
B[P0++] = R1;
B[P0++] = R1;
JUMP .Laligned;
.size __coreb_memset,.-__coreb_memset
#endif
#ifdef __ADSPBF561_COREB__
.section .b.bss,"aw",@progbits
.align 4
.type L$argv_coreb, @object
.size L$argv_coreb, 4
L$argv_coreb:
.zero 4
#else
.local L$argv
.comm L$argv,4,4
#endif

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/*
* The default linker stript for standalone executables running on
* ADSP-BF522 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

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/*
* The default linker stript for standalone executables running on
* ADSP-BF523 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

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/*
* The default linker stript for standalone executables running on
* ADSP-BF522 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

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/*
* The default linker stript for standalone executables running on
* ADSP-BF525 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

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/*
* The default linker stript for standalone executables running on
* ADSP-BF522 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

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/*
* The default linker stript for standalone executables running on
* ADSP-BF527 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

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/*
* The default linker stript for standalone executables running on
* ADSP-BF531 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA08000, LENGTH = 0x4000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_A : ORIGIN = 0xFF804000, LENGTH = 0x4000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

27
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/*
* The default linker stript for standalone executables running on
* ADSP-BF532 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA08000, LENGTH = 0x8000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF904000, LENGTH = 0x4000
MEM_L1_DATA_A : ORIGIN = 0xFF804000, LENGTH = 0x4000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

27
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/*
* The default linker stript for standalone executables running on
* ADSP-BF533 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

27
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/*
* The default linker stript for standalone executable running on
* ADSP-BF534 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xC000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

27
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/*
* The default linker stript for standalone executable running on
* ADSP-BF536 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xC000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF904000, LENGTH = 0x4000
MEM_L1_DATA_A : ORIGIN = 0xFF804000, LENGTH = 0x4000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

27
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/*
* The default linker stript for standalone executable running on
* ADSP-BF537 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xC000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

27
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/*
* The default linker stript for standalone executable running on
* ADSP-BF538 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

27
libgloss/bfin/bf539.ld Normal file
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/*
* The default linker stript for standalone executable running on
* ADSP-BF539 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
}

27
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/*
* The default linker stript for standalone executables running on
* ADSP-BF542 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
}

27
libgloss/bfin/bf544.ld Normal file
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/*
* The default linker stript for standalone executables running on
* ADSP-BF544 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
}

27
libgloss/bfin/bf547.ld Normal file
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/*
* The default linker stript for standalone executables running on
* ADSP-BF547 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
}

27
libgloss/bfin/bf548.ld Normal file
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/*
* The default linker stript for standalone executables running on
* ADSP-BF548 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
}

27
libgloss/bfin/bf549.ld Normal file
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@ -0,0 +1,27 @@
/*
* The default linker stript for standalone executables running on
* ADSP-BF549 processor.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
}

27
libgloss/bfin/bf561.ld Normal file
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@ -0,0 +1,27 @@
/*
* The default linker stript for standalone executables running on
* ADSP-BF561 processor (single core).
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x4000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
}

34
libgloss/bfin/bf561a.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker stript for standalone executables running on
* Core A of ADSP-BF561 processor (dual core).
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x4000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
B_MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x0
B_MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x0
B_MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x0
B_MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x0
B_MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x0
MEM_L2 : ORIGIN = 0xFEB08000, LENGTH = 0x8000
MEM_L2_SHARED : ORIGIN = 0xFEB10000, LENGTH = 0x10000
}

36
libgloss/bfin/bf561b.ld Normal file
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@ -0,0 +1,36 @@
/*
* The default linker stript for standalone executables running on
* Core B of ADSP-BF561 processor (dual core).
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
/* These B_MEM_* are Core A memory region with zero length.
They just provide dummy memory region to satisfy bfin-common-mc.ld. */
B_MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x0
B_MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x0
B_MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x0
B_MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x0
B_MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x0
MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x4000
MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x8000
MEM_L2_SHARED : ORIGIN = 0xFEB10000, LENGTH = 0x10000
}

34
libgloss/bfin/bf561m.ld Normal file
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@ -0,0 +1,34 @@
/*
* The default linker stript for standalone executables running on
* ADSP-BF561 processor (dual core).
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
MEMORY
{
MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x4000
MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
B_MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x4000
B_MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
B_MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
B_MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
B_MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
MEM_L2_SHARED : ORIGIN = 0xFEB20000, LENGTH = 0x0
}

260
libgloss/bfin/bfin-common-mc.ld Normal file
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@ -0,0 +1,260 @@
/*
* The common part of the default linker stripts for standalone executables
* running on single core Blackfin processors.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* The default linker script, for single core blackfin standalone executables */
OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
"elf32-bfin")
OUTPUT_ARCH(bfin)
ENTRY(__start)
SECTIONS
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{
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KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
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.init :
{
KEEP (*(.init))
} >MEM_L1_CODE =0
.plt : { *(.plt) } >MEM_L1_CODE
.fini :
{
KEEP (*(.fini))
} >MEM_L1_CODE =0
PROVIDE (__etext = .);
PROVIDE (_etext = .);
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.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >MEM_L1_DATA_A
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >MEM_L1_DATA_A
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(0x1000) + (. & (0x1000 - 1));
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >MEM_L1_DATA_A
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >MEM_L1_DATA_A
/* Thread Local Storage sections */
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.preinit_array :
{
PROVIDE_HIDDEN (___preinit_array_start = .);
KEEP (*(.preinit_array))
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} >MEM_L1_DATA_A
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{
PROVIDE_HIDDEN (___init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (___init_array_end = .);
} >MEM_L1_DATA_A
.fini_array :
{
PROVIDE_HIDDEN (___fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (___fini_array_end = .);
} >MEM_L1_DATA_A
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
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KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from
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The .ctor section from the crtend file contains the
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KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >MEM_L1_DATA_A
.dtors :
{
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KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >MEM_L1_DATA_A
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SORT(CONSTRUCTORS)
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/* We want the small data sections together, so single-instruction offsets
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{
*(.sdata .sdata.* .gnu.linkonce.s.*)
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{
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{
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*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
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*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
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. = ALIGN(32 / 8);
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/* GNU DWARF 1 extensions */
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/DISCARD/ : { *(.note.GNU-stack) }
}

237
libgloss/bfin/bfin-common-sc.ld Normal file
View File

@ -0,0 +1,237 @@
/*
* The common part of the default linker stripts for standalone executables
* running on single core Blackfin processors.
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* The default linker script, for single core blackfin standalone executables */
OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
"elf32-bfin")
OUTPUT_ARCH(bfin)
ENTRY(__start)
SECTIONS
{
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/* Adjust the address for the data segment. We want to adjust up to
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/* Exception handling */
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/* Thread Local Storage sections */
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18
libgloss/bfin/include/blackfin.h Normal file
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@ -0,0 +1,18 @@
/*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#ifndef _BLACKFIN_H
#define _BLACKFIN_H
#include <sys/platform.h>
#endif

39
libgloss/bfin/include/cdefBF522.h Normal file
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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the ADSP-BF522 peripherals.
**
************************************************************************************
** System MMR Register Map
************************************************************************************/
#ifndef _CDEF_BF522_H
#define _CDEF_BF522_H
/* include all Core registers and bit definitions */
#include <defBF522.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include <cdefBF52x_base.h>
#endif /* _CDEF_BF522_H */

285
libgloss/bfin/include/cdefBF525.h Normal file
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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the ADSP-BF525 peripherals.
**
************************************************************************************
** System MMR Register Map
************************************************************************************/
#ifndef _CDEF_BF525_H
#define _CDEF_BF525_H
/* include all Core registers and bit definitions */
#include <defBF525.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include <cdefBF52x_base.h>
/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
/* USB Control Registers */
#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
/* USB Packet Control Registers */
#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
/* USB Endpoint FIFO Registers */
#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
/* USB OTG Control Registers */
#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
/* USB Phy Control Registers */
#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
/* (APHY_CNTRL is for ADI usage only) */
#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
/* (APHY_CALIB is for ADI usage only) */
#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
/* (PHY_TEST is for ADI usage only) */
#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
/* USB Endpoint 0 Control Registers */
#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
/* USB Endpoint 1 Control Registers */
#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
/* USB Endpoint 2 Control Registers */
#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
/* USB Endpoint 3 Control Registers */
#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
/* USB Endpoint 4 Control Registers */
#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
/* USB Endpoint 5 Control Registers */
#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
/* USB Endpoint 6 Control Registers */
#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
/* USB Endpoint 7 Control Registers */
#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
/* USB Channel 0 Config Registers */
#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
/* USB Channel 1 Config Registers */
#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
/* USB Channel 2 Config Registers */
#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
/* USB Channel 3 Config Registers */
#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
/* USB Channel 4 Config Registers */
#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
/* USB Channel 5 Config Registers */
#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
/* USB Channel 6 Config Registers */
#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
/* USB Channel 7 Config Registers */
#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
#endif /* _CDEF_BF525_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the ADSP-BF527 peripherals.
**
************************************************************************************
** System MMR Register Map
************************************************************************************/
#ifndef _CDEF_BF527_H
#define _CDEF_BF527_H
/* include all Core registers and bit definitions */
#include <defBF527.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include <cdefBF52x_base.h>
/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
/* USB Control Registers */
#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
/* USB Packet Control Registers */
#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
/* USB Endpoint FIFO Registers */
#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
/* USB OTG Control Registers */
#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
/* USB Phy Control Registers */
#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
/* (APHY_CNTRL is for ADI usage only) */
#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
/* (APHY_CALIB is for ADI usage only) */
#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
/* (PHY_TEST is for ADI usage only) */
#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
/* USB Endpoint 0 Control Registers */
#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
/* USB Endpoint 1 Control Registers */
#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
/* USB Endpoint 2 Control Registers */
#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
/* USB Endpoint 3 Control Registers */
#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
/* USB Endpoint 4 Control Registers */
#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
/* USB Endpoint 5 Control Registers */
#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
/* USB Endpoint 6 Control Registers */
#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
/* USB Endpoint 7 Control Registers */
#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
/* USB Channel 0 Config Registers */
#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
/* USB Channel 1 Config Registers */
#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
/* USB Channel 2 Config Registers */
#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
/* USB Channel 3 Config Registers */
#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
/* USB Channel 4 Config Registers */
#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
/* USB Channel 5 Config Registers */
#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
/* USB Channel 6 Config Registers */
#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
/* USB Channel 7 Config Registers */
#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
#endif /* _CDEF_BF527_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** cdefBF52x_base.h
**
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the registers common to the ADSP-BF52x peripherals.
**
***************************************************************/
#ifndef _CDEF_BF52X_H
#define _CDEF_BF52X_H
#include <defBF52x_base.h>
/* ==== begin from cdefBF534.h ==== */
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#else
#define _PTR_TO_VOL_VOID_PTR (volatile void **)
#endif
#endif
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
#define pVR_CTL ((volatile unsigned short *)VR_CTL)
#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
#define pCHIPID ((volatile unsigned long*)CHIPID)
/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define pSWRST ((volatile unsigned short *)SWRST)
#define pSYSCR ((volatile unsigned short *)SYSCR)
#define pSIC_RVECT (_PTR_TO_VOL_VOID_PTR SIC_RVECT)
#define pSIC_IMASK0 ((volatile unsigned long *)SIC_IMASK0)
/* legacy register name (below) provided for backwards code compatibility */
#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK0)
#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
#define pSIC_ISR0 ((volatile unsigned long *)SIC_ISR0)
/* legacy register name (below) provided for backwards code compatibility */
#define pSIC_ISR ((volatile unsigned long *)SIC_ISR0)
#define pSIC_IWR0 ((volatile unsigned long *)SIC_IWR0)
/* legacy register name (below) provided for backwards code compatibility */
#define pSIC_IWR ((volatile unsigned long *)SIC_IWR0)
/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
#define pSIC_IMASK1 ((volatile unsigned long *)SIC_IMASK1)
#define pSIC_IAR4 ((volatile unsigned long *)SIC_IAR4)
#define pSIC_IAR5 ((volatile unsigned long *)SIC_IAR5)
#define pSIC_IAR6 ((volatile unsigned long *)SIC_IAR6)
#define pSIC_IAR7 ((volatile unsigned long *)SIC_IAR7)
#define pSIC_ISR1 ((volatile unsigned long *)SIC_ISR1)
#define pSIC_IWR1 ((volatile unsigned long *)SIC_IWR1)
/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
#define pUART0_THR ((volatile unsigned short *)UART0_THR)
#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
#define pUART0_IER ((volatile unsigned short *)UART0_IER)
#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_MSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG)
#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD)
#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH)
#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG)
#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD)
#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH)
#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG)
#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD)
#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH)
#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG)
#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD)
#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH)
#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG)
#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD)
#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH)
#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
#define pTIMER_STATUS ((volatile unsigned long *)TIMER_STATUS)
/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
#define pPORTFIO ((volatile unsigned short *)PORTFIO)
#define pPORTFIO_CLEAR ((volatile unsigned short *)PORTFIO_CLEAR)
#define pPORTFIO_SET ((volatile unsigned short *)PORTFIO_SET)
#define pPORTFIO_TOGGLE ((volatile unsigned short *)PORTFIO_TOGGLE)
#define pPORTFIO_MASKA ((volatile unsigned short *)PORTFIO_MASKA)
#define pPORTFIO_MASKA_CLEAR ((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
#define pPORTFIO_MASKA_SET ((volatile unsigned short *)PORTFIO_MASKA_SET)
#define pPORTFIO_MASKA_TOGGLE ((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
#define pPORTFIO_MASKB ((volatile unsigned short *)PORTFIO_MASKB)
#define pPORTFIO_MASKB_CLEAR ((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
#define pPORTFIO_MASKB_SET ((volatile unsigned short *)PORTFIO_MASKB_SET)
#define pPORTFIO_MASKB_TOGGLE ((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
#define pPORTFIO_DIR ((volatile unsigned short *)PORTFIO_DIR)
#define pPORTFIO_POLAR ((volatile unsigned short *)PORTFIO_POLAR)
#define pPORTFIO_EDGE ((volatile unsigned short *)PORTFIO_EDGE)
#define pPORTFIO_BOTH ((volatile unsigned short *)PORTFIO_BOTH)
#define pPORTFIO_INEN ((volatile unsigned short *)PORTFIO_INEN)
/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
#define pSPORT0_TX32 ((volatile unsigned long *)SPORT0_TX)
#define pSPORT0_RX32 ((volatile unsigned long *)SPORT0_RX)
#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX)
#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX)
#define pSPORT1_TX32 ((volatile unsigned long *)SPORT1_TX)
#define pSPORT1_RX32 ((volatile unsigned long *)SPORT1_RX)
#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
/* DMA Traffic Control Registers */
#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)
#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
/* DMA Controller */
#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
#define pDMA0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
#define pDMA0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
#define pDMA0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
#define pDMA0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
#define pDMA1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
#define pDMA1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
#define pDMA1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
#define pDMA1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
#define pDMA2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
#define pDMA2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
#define pDMA2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
#define pDMA2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
#define pDMA3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
#define pDMA3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
#define pDMA3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
#define pDMA3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
#define pDMA4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
#define pDMA4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
#define pDMA4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
#define pDMA4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
#define pDMA5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
#define pDMA5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
#define pDMA5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
#define pDMA5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
#define pDMA6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
#define pDMA6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
#define pDMA6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
#define pDMA6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
#define pDMA7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
#define pDMA7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
#define pDMA7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
#define pDMA7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
#define pDMA8_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
#define pDMA8_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
#define pDMA8_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
#define pDMA8_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
#define pDMA9_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA9_NEXT_DESC_PTR)
#define pDMA9_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA9_START_ADDR)
#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
#define pDMA9_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA9_CURR_DESC_PTR)
#define pDMA9_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA9_CURR_ADDR)
#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
#define pDMA10_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA10_NEXT_DESC_PTR)
#define pDMA10_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA10_START_ADDR)
#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
#define pDMA10_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA10_CURR_DESC_PTR)
#define pDMA10_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA10_CURR_ADDR)
#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
#define pDMA11_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA11_NEXT_DESC_PTR)
#define pDMA11_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA11_START_ADDR)
#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
#define pDMA11_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA11_CURR_DESC_PTR)
#define pDMA11_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA11_CURR_ADDR)
#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
#define pMDMA_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
#define pMDMA_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
#define pMDMA_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
#define pMDMA_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
#define pMDMA_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
#define pMDMA_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
#define pMDMA_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
#define pMDMA_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
#define pMDMA_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
#define pMDMA_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
#define pMDMA_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
#define pMDMA_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
#define pMDMA_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
#define pMDMA_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
#define pMDMA_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
#define pMDMA_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
#define pTWI_CLKDIV ((volatile unsigned short *)TWI_CLKDIV)
#define pTWI_CONTROL ((volatile unsigned short *)TWI_CONTROL)
#define pTWI_SLAVE_CTL ((volatile unsigned short *)TWI_SLAVE_CTL)
#define pTWI_SLAVE_STAT ((volatile unsigned short *)TWI_SLAVE_STAT)
#define pTWI_SLAVE_ADDR ((volatile unsigned short *)TWI_SLAVE_ADDR)
#define pTWI_MASTER_CTL ((volatile unsigned short *)TWI_MASTER_CTL)
#define pTWI_MASTER_STAT ((volatile unsigned short *)TWI_MASTER_STAT)
#define pTWI_MASTER_ADDR ((volatile unsigned short *)TWI_MASTER_ADDR)
#define pTWI_INT_STAT ((volatile unsigned short *)TWI_INT_STAT)
#define pTWI_INT_MASK ((volatile unsigned short *)TWI_INT_MASK)
#define pTWI_FIFO_CTL ((volatile unsigned short *)TWI_FIFO_CTL)
#define pTWI_FIFO_STAT ((volatile unsigned short *)TWI_FIFO_STAT)
#define pTWI_XMT_DATA8 ((volatile unsigned short *)TWI_XMT_DATA8)
#define pTWI_XMT_DATA16 ((volatile unsigned short *)TWI_XMT_DATA16)
#define pTWI_RCV_DATA8 ((volatile unsigned short *)TWI_RCV_DATA8)
#define pTWI_RCV_DATA16 ((volatile unsigned short *)TWI_RCV_DATA16)
/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
#define pPORTGIO ((volatile unsigned short *)PORTGIO)
#define pPORTGIO_CLEAR ((volatile unsigned short *)PORTGIO_CLEAR)
#define pPORTGIO_SET ((volatile unsigned short *)PORTGIO_SET)
#define pPORTGIO_TOGGLE ((volatile unsigned short *)PORTGIO_TOGGLE)
#define pPORTGIO_MASKA ((volatile unsigned short *)PORTGIO_MASKA)
#define pPORTGIO_MASKA_CLEAR ((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
#define pPORTGIO_MASKA_SET ((volatile unsigned short *)PORTGIO_MASKA_SET)
#define pPORTGIO_MASKA_TOGGLE ((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
#define pPORTGIO_MASKB ((volatile unsigned short *)PORTGIO_MASKB)
#define pPORTGIO_MASKB_CLEAR ((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
#define pPORTGIO_MASKB_SET ((volatile unsigned short *)PORTGIO_MASKB_SET)
#define pPORTGIO_MASKB_TOGGLE ((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
#define pPORTGIO_DIR ((volatile unsigned short *)PORTGIO_DIR)
#define pPORTGIO_POLAR ((volatile unsigned short *)PORTGIO_POLAR)
#define pPORTGIO_EDGE ((volatile unsigned short *)PORTGIO_EDGE)
#define pPORTGIO_BOTH ((volatile unsigned short *)PORTGIO_BOTH)
#define pPORTGIO_INEN ((volatile unsigned short *)PORTGIO_INEN)
/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
#define pPORTHIO ((volatile unsigned short *)PORTHIO)
#define pPORTHIO_CLEAR ((volatile unsigned short *)PORTHIO_CLEAR)
#define pPORTHIO_SET ((volatile unsigned short *)PORTHIO_SET)
#define pPORTHIO_TOGGLE ((volatile unsigned short *)PORTHIO_TOGGLE)
#define pPORTHIO_MASKA ((volatile unsigned short *)PORTHIO_MASKA)
#define pPORTHIO_MASKA_CLEAR ((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
#define pPORTHIO_MASKA_SET ((volatile unsigned short *)PORTHIO_MASKA_SET)
#define pPORTHIO_MASKA_TOGGLE ((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
#define pPORTHIO_MASKB ((volatile unsigned short *)PORTHIO_MASKB)
#define pPORTHIO_MASKB_CLEAR ((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
#define pPORTHIO_MASKB_SET ((volatile unsigned short *)PORTHIO_MASKB_SET)
#define pPORTHIO_MASKB_TOGGLE ((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
#define pPORTHIO_DIR ((volatile unsigned short *)PORTHIO_DIR)
#define pPORTHIO_POLAR ((volatile unsigned short *)PORTHIO_POLAR)
#define pPORTHIO_EDGE ((volatile unsigned short *)PORTHIO_EDGE)
#define pPORTHIO_BOTH ((volatile unsigned short *)PORTHIO_BOTH)
#define pPORTHIO_INEN ((volatile unsigned short *)PORTHIO_INEN)
/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
#define pUART1_THR ((volatile unsigned short *)UART1_THR)
#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
#define pUART1_IER ((volatile unsigned short *)UART1_IER)
#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_MSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
#define pPORTF_FER ((volatile unsigned short *)PORTF_FER)
#define pPORTG_FER ((volatile unsigned short *)PORTG_FER)
#define pPORTH_FER ((volatile unsigned short *)PORTH_FER)
/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
#define pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL)
#define pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT)
#define pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT)
#define pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT)
#define pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW)
#define pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT)
#define pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT)
#define pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL)
#define pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT)
#define pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT)
#define pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT)
#define pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW)
#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT)
#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT)
/* ==== end from cdefBF534.h ==== */
/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
#define pPORTF_MUX ((volatile unsigned short *)PORTF_MUX)
#define pPORTG_MUX ((volatile unsigned short *)PORTG_MUX)
#define pPORTH_MUX ((volatile unsigned short *)PORTH_MUX)
#define pPORTF_DRIVE ((volatile unsigned short *)PORTF_DRIVE)
#define pPORTG_DRIVE ((volatile unsigned short *)PORTG_DRIVE)
#define pPORTH_DRIVE ((volatile unsigned short *)PORTH_DRIVE)
#define pPORTF_SLEW ((volatile unsigned short *)PORTF_SLEW)
#define pPORTG_SLEW ((volatile unsigned short *)PORTG_SLEW)
#define pPORTH_SLEW ((volatile unsigned short *)PORTH_SLEW)
#define pPORTF_HYSTERESIS ((volatile unsigned short *)PORTF_HYSTERESIS)
#define pPORTG_HYSTERESIS ((volatile unsigned short *)PORTG_HYSTERESIS)
#define pPORTH_HYSTERESIS ((volatile unsigned short *)PORTH_HYSTERESIS)
#define pNONGPIO_DRIVE ((volatile unsigned short *)NONGPIO_DRIVE)
#define pNONGPIO_SLEW ((volatile unsigned short *)NONGPIO_SLEW)
#define pNONGPIO_HYSTERESIS ((volatile unsigned short *)NONGPIO_HYSTERESIS)
/* HOST Port Registers */
#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
/* Counter Registers */
#define pCNT_CONFIG ((volatile unsigned short *)CNT_CONFIG)
#define pCNT_IMASK ((volatile unsigned short *)CNT_IMASK)
#define pCNT_STATUS ((volatile unsigned short *)CNT_STATUS)
#define pCNT_COMMAND ((volatile unsigned short *)CNT_COMMAND)
#define pCNT_DEBOUNCE ((volatile unsigned short *)CNT_DEBOUNCE)
#define pCNT_COUNTER ((volatile unsigned long *)CNT_COUNTER)
#define pCNT_MAX ((volatile unsigned long *)CNT_MAX)
#define pCNT_MIN ((volatile unsigned long *)CNT_MIN)
/* OTP/FUSE Registers */
#define pOTP_CONTROL ((volatile unsigned short *)OTP_CONTROL)
#define pOTP_BEN ((volatile unsigned short *)OTP_BEN)
#define pOTP_STATUS ((volatile unsigned short *)OTP_STATUS)
#define pOTP_TIMING ((volatile unsigned long *)OTP_TIMING)
/* Security Registers */
#define pSECURE_SYSSWT ((volatile unsigned long *)SECURE_SYSSWT)
#define pSECURE_CONTROL ((volatile unsigned short *)SECURE_CONTROL)
#define pSECURE_STATUS ((volatile unsigned short *)SECURE_STATUS)
/* OTP Read/Write Data Buffer Registers */
#define pOTP_DATA0 ((volatile unsigned long *)OTP_DATA0)
#define pOTP_DATA1 ((volatile unsigned long *)OTP_DATA1)
#define pOTP_DATA2 ((volatile unsigned long *)OTP_DATA2)
#define pOTP_DATA3 ((volatile unsigned long *)OTP_DATA3)
/* NFC Registers */
#define pNFC_CTL ((volatile unsigned short *)NFC_CTL)
#define pNFC_STAT ((volatile unsigned short *)NFC_STAT)
#define pNFC_IRQSTAT ((volatile unsigned short *)NFC_IRQSTAT)
#define pNFC_IRQMASK ((volatile unsigned short *)NFC_IRQMASK)
#define pNFC_ECC0 ((volatile unsigned short *)NFC_ECC0)
#define pNFC_ECC1 ((volatile unsigned short *)NFC_ECC1)
#define pNFC_ECC2 ((volatile unsigned short *)NFC_ECC2)
#define pNFC_ECC3 ((volatile unsigned short *)NFC_ECC3)
#define pNFC_COUNT ((volatile unsigned short *)NFC_COUNT)
#define pNFC_RST ((volatile unsigned short *)NFC_RST)
#define pNFC_PGCTL ((volatile unsigned short *)NFC_PGCTL)
#define pNFC_READ ((volatile unsigned short *)NFC_READ)
#define pNFC_ADDR ((volatile unsigned short *)NFC_ADDR)
#define pNFC_CMD ((volatile unsigned short *)NFC_CMD)
#define pNFC_DATA_WR ((volatile unsigned short *)NFC_DATA_WR)
#define pNFC_DATA_RD ((volatile unsigned short *)NFC_DATA_RD)
#endif /* _CDEF_BF52X_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cdefBF531.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _CDEFBF531_H
#define _CDEFBF531_H
#include <cdefBF532.h>
#endif /* _CDEFBF531_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cdefBF532.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _CDEF_BF532_H
#define _CDEF_BF532_H
#if !defined(__ADSPLPBLACKFIN__)
#warning cdefBF532.h should only be included for 532 compatible chips.
#endif
/* include all Core registers and bit definitions */
#include <defBF532.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/* include built-in mneumonic macros */
#include <ccblkfn.h>
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#else
#define _PTR_TO_VOL_VOID_PTR (volatile void **)
#endif
#endif
/* Clock/Regulator Control */
#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
#define pVR_CTL ((volatile unsigned short *)VR_CTL)
#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
#define pCHIPID ((volatile unsigned long *)CHIPID)
/* System Interrupt Controller */
#define pSWRST ((volatile unsigned short *)SWRST)
#define pSYSCR ((volatile unsigned short *)SYSCR)
#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
/* Watchdog Timer */
#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
/* Real Time Clock */
#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
/* UART Controller */
#define pUART_THR ((volatile unsigned short *)UART_THR)
#define pUART_RBR ((volatile unsigned short *)UART_RBR)
#define pUART_DLL ((volatile unsigned short *)UART_DLL)
#define pUART_IER ((volatile unsigned short *)UART_IER)
#define pUART_DLH ((volatile unsigned short *)UART_DLH)
#define pUART_IIR ((volatile unsigned short *)UART_IIR)
#define pUART_LCR ((volatile unsigned short *)UART_LCR)
#define pUART_MCR ((volatile unsigned short *)UART_MCR)
#define pUART_LSR ((volatile unsigned short *)UART_LSR)
/* #define UART_MSR */
#define pUART_SCR ((volatile unsigned short *)UART_SCR)
#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)
/* SPI Controller */
#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
/* TIMER 0, 1, 2 Registers */
#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS)
/* General Purpose IO */
#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)
#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)
#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)
#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)
#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)
#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)
#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)
/* SPORT0 Controller */
#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
#define pSPORT0_TX ((volatile long *)SPORT0_TX)
#define pSPORT0_RX ((volatile long *)SPORT0_RX)
#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
/* SPORT1 Controller */
#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
#define pSPORT1_TX ((volatile long *)SPORT1_TX)
#define pSPORT1_RX ((volatile long *)SPORT1_RX)
#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
/* External Bus Interface Unit */
/* Aysnchronous Memory Controller */
#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
/* SDRAM Controller */
#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
/* DMA Traffic controls */
#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)
#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)
/* Alternate deprecated register names (below) provided for backwards code compatibility */
#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
/* DMA Controller */
#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
#define pDMA0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
#define pDMA0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
#define pDMA0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
#define pDMA0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
#define pDMA1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
#define pDMA1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
#define pDMA1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
#define pDMA1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
#define pDMA2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
#define pDMA2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
#define pDMA2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
#define pDMA2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
#define pDMA3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
#define pDMA3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
#define pDMA3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
#define pDMA3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
#define pDMA4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
#define pDMA4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
#define pDMA4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
#define pDMA4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
#define pDMA5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
#define pDMA5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
#define pDMA5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
#define pDMA5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
#define pDMA6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
#define pDMA6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
#define pDMA6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
#define pDMA6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
#define pDMA7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
#define pDMA7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
#define pDMA7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
#define pDMA7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
#define pMDMA_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
#define pMDMA_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
#define pMDMA_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
#define pMDMA_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
#define pMDMA_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
#define pMDMA_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
#define pMDMA_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
#define pMDMA_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
#define pMDMA_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
#define pMDMA_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
#define pMDMA_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
#define pMDMA_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
#define pMDMA_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
#define pMDMA_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
#define pMDMA_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
#define pMDMA_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
/* Parallel Peripheral Interface (PPI) */
#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
#endif /* _CDEF_BF532_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cdefBF533.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _CDEFBF533_H
#define _CDEFBF533_H
#include <cdefBF532.h>
#endif /* _CDEFBF533_H */

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libgloss/bfin/include/cdefBF535.h Normal file
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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cdefBF535.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _CDEF_BF535_H
#define _CDEF_BF535_H
/* include all Core registers and bit definitions */
#if defined(__ADSPLPBLACKFIN__)
#warning cdefBF535.h should only be included for 535 compatible chips.
#endif
#include <defBF535.h>
/* include core specific register pointer definitions */
#include <cdefblackfin.h>
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#else
#define _PTR_TO_VOL_VOID_PTR (volatile void **)
#endif
#endif
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
#define pPLL_CTL ((volatile unsigned long *)PLL_CTL)
#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
#define pSWRST ((volatile unsigned short *)SWRST)
#define pSYSCR ((volatile unsigned short *)SYSCR)
#define pPLL_IOCKR ((volatile unsigned short *)PLL_IOCKR)
#define pPLL_IOCK ((volatile unsigned short *)PLL_IOCK)
/* JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF) */
#define pCHIPID ((volatile unsigned long *)CHIPID)
/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
/* USB Registers (0xFFC0 4400 - 0xFFC0 47FF) */
#define pUSBD_ID ((volatile unsigned short *)USBD_ID)
#define pUSBD_FRM ((volatile unsigned short *)USBD_FRM)
#define pUSBD_FRMAT ((volatile unsigned short *)USBD_FRMAT)
#define pUSBD_EPBUF ((volatile unsigned short *)USBD_EPBUF)
#define pUSBD_STAT ((volatile unsigned short *)USBD_STAT)
#define pUSBD_CTRL ((volatile unsigned short *)USBD_CTRL)
#define pUSBD_GINTR ((volatile unsigned short *)USBD_GINTR)
#define pUSBD_GMASK ((volatile unsigned short *)USBD_GMASK)
#define pUSBD_DMACFG ((volatile unsigned short *)USBD_DMACFG)
#define pUSBD_DMABL ((volatile unsigned short *)USBD_DMABL)
#define pUSBD_DMABH ((volatile unsigned short *)USBD_DMABH)
#define pUSBD_DMACT ((volatile unsigned short *)USBD_DMACT)
#define pUSBD_DMAIRQ ((volatile unsigned short *)USBD_DMAIRQ)
#define pUSBD_INTR0 ((volatile unsigned short *)USBD_INTR0)
#define pUSBD_MASK0 ((volatile unsigned short *)USBD_MASK0)
#define pUSBD_EPCFG0 ((volatile unsigned short *)USBD_EPCFG0)
#define pUSBD_EPADR0 ((volatile unsigned short *)USBD_EPADR0)
#define pUSBD_EPLEN0 ((volatile unsigned short *)USBD_EPLEN0)
#define pUSBD_INTR1 ((volatile unsigned short *)USBD_INTR1)
#define pUSBD_MASK1 ((volatile unsigned short *)USBD_MASK1)
#define pUSBD_EPCFG1 ((volatile unsigned short *)USBD_EPCFG1)
#define pUSBD_EPADR1 ((volatile unsigned short *)USBD_EPADR1)
#define pUSBD_EPLEN1 ((volatile unsigned short *)USBD_EPLEN1)
#define pUSBD_INTR2 ((volatile unsigned short *)USBD_INTR2)
#define pUSBD_MASK2 ((volatile unsigned short *)USBD_MASK2)
#define pUSBD_EPCFG2 ((volatile unsigned short *)USBD_EPCFG2)
#define pUSBD_EPADR2 ((volatile unsigned short *)USBD_EPADR2)
#define pUSBD_EPLEN2 ((volatile unsigned short *)USBD_EPLEN2)
#define pUSBD_INTR3 ((volatile unsigned short *)USBD_INTR3)
#define pUSBD_MASK3 ((volatile unsigned short *)USBD_MASK3)
#define pUSBD_EPCFG3 ((volatile unsigned short *)USBD_EPCFG3)
#define pUSBD_EPADR3 ((volatile unsigned short *)USBD_EPADR3)
#define pUSBD_EPLEN3 ((volatile unsigned short *)USBD_EPLEN3)
#define pUSBD_INTR4 ((volatile unsigned short *)USBD_INTR4)
#define pUSBD_MASK4 ((volatile unsigned short *)USBD_MASK4)
#define pUSBD_EPCFG4 ((volatile unsigned short *)USBD_EPCFG4)
#define pUSBD_EPADR4 ((volatile unsigned short *)USBD_EPADR4)
#define pUSBD_EPLEN4 ((volatile unsigned short *)USBD_EPLEN4)
#define pUSBD_INTR5 ((volatile unsigned short *)USBD_INTR5)
#define pUSBD_MASK5 ((volatile unsigned short *)USBD_MASK5)
#define pUSBD_EPCFG5 ((volatile unsigned short *)USBD_EPCFG5)
#define pUSBD_EPADR5 ((volatile unsigned short *)USBD_EPADR5)
#define pUSBD_EPLEN5 ((volatile unsigned short *)USBD_EPLEN5)
#define pUSBD_INTR6 ((volatile unsigned short *)USBD_INTR6)
#define pUSBD_MASK6 ((volatile unsigned short *)USBD_MASK6)
#define pUSBD_EPCFG6 ((volatile unsigned short *)USBD_EPCFG6)
#define pUSBD_EPADR6 ((volatile unsigned short *)USBD_EPADR6)
#define pUSBD_EPLEN6 ((volatile unsigned short *)USBD_EPLEN6)
#define pUSBD_INTR7 ((volatile unsigned short *)USBD_INTR7)
#define pUSBD_MASK7 ((volatile unsigned short *)USBD_MASK7)
#define pUSBD_EPCFG7 ((volatile unsigned short *)USBD_EPCFG7)
#define pUSBD_EPADR7 ((volatile unsigned short *)USBD_EPADR7)
#define pUSBD_EPLEN7 ((volatile unsigned short *)USBD_EPLEN7)
/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
#define pEBIU_SDBCTL ((volatile unsigned long *)EBIU_SDBCTL)
/* Memory Map */
/* Core MMRs */
#define pCOREMMR_BASE ((volatile void *)COREMMR_BASE)
/* System MMRs */
#define pSYSMMR_BASE ((volatile void *)SYSMMR_BASE)
/* L1 cache/SRAM internal memory */
#define pL1_DATA_A ((void *)L1_DATA_A)
#define pL1_DATA_B ((void *)L1_DATA_B)
#define pL1_CODE ((void *)L1_CODE)
#define pL1_SCRATCH ((void *)L1_SCRATCH)
/* L2 SRAM external memory */
#define pL2_BASE ((void *)L2_BASE)
/* PCI Spaces */
#define pPCI_CONFIG_SPACE_PORT ((volatile void *)PCI_CONFIG_SPACE_PORT)
#define pPCI_CONFIG_BASE ((volatile void *)PCI_CONFIG_BASE)
#define pPCI_IO_BASE ((volatile void *)PCI_IO_BASE)
#define pPCI_MEM_BASE ((volatile void *)PCI_MEM_BASE)
/* Async Memory Banks */
#define pASYNC_BANK3_BASE ((void *)ASYNC_BANK3_BASE)
#define pASYNC_BANK2_BASE ((void *)ASYNC_BANK2_BASE)
#define pASYNC_BANK1_BASE ((void *)ASYNC_BANK1_BASE)
#define pASYNC_BANK0_BASE ((void *)ASYNC_BANK0_BASE)
/* Sync DRAM Banks */
#define pSDRAM_BANK3_BASE ((void *)SDRAM_BANK3_BASE)
#define pSDRAM_BANK2_BASE ((void *)SDRAM_BANK2_BASE)
#define pSDRAM_BANK1_BASE ((void *)SDRAM_BANK1_BASE)
#define pSDRAM_BANK0_BASE ((void *)SDRAM_BANK0_BASE)
/* UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF) */
#define pUART0_THR ((volatile unsigned short *)UART0_THR)
#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
#define pUART0_IER ((volatile unsigned short *)UART0_IER)
#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_MSR ((volatile unsigned short *)UART0_MSR)
#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
#define pUART0_IRCR ((volatile unsigned short *)UART0_IRCR)
#define pUART0_CURR_PTR_RX ((volatile unsigned short *)UART0_CURR_PTR_RX)
#define pUART0_CONFIG_RX ((volatile unsigned short *)UART0_CONFIG_RX)
#define pUART0_START_ADDR_HI_RX ((volatile unsigned short *)UART0_START_ADDR_HI_RX)
#define pUART0_START_ADDR_LO_RX ((volatile unsigned short *)UART0_START_ADDR_LO_RX)
#define pUART0_COUNT_RX ((volatile unsigned short *)UART0_COUNT_RX)
#define pUART0_NEXT_DESCR_RX ((volatile unsigned short *)UART0_NEXT_DESCR_RX)
#define pUART0_DESCR_RDY_RX ((volatile unsigned short *)UART0_DESCR_RDY_RX)
#define pUART0_IRQSTAT_RX ((volatile unsigned short *)UART0_IRQSTAT_RX)
#define pUART0_CURR_PTR_TX ((volatile unsigned short *)UART0_CURR_PTR_TX)
#define pUART0_CONFIG_TX ((volatile unsigned short *)UART0_CONFIG_TX)
#define pUART0_START_ADDR_HI_TX ((volatile unsigned short *)UART0_START_ADDR_HI_TX)
#define pUART0_START_ADDR_LO_TX ((volatile unsigned short *)UART0_START_ADDR_LO_TX)
#define pUART0_COUNT_TX ((volatile unsigned short *)UART0_COUNT_TX)
#define pUART0_NEXT_DESCR_TX ((volatile unsigned short *)UART0_NEXT_DESCR_TX)
#define pUART0_DESCR_RDY_TX ((volatile unsigned short *)UART0_DESCR_RDY_TX)
#define pUART0_IRQSTAT_TX ((volatile unsigned short *)UART0_IRQSTAT_TX)
/* UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF) */
#define pUART1_THR ((volatile unsigned short *)UART1_THR)
#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
#define pUART1_IER ((volatile unsigned short *)UART1_IER)
#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_MSR ((volatile unsigned short *)UART1_MSR)
#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
#define pUART1_CURR_PTR_RX ((volatile unsigned short *)UART1_CURR_PTR_RX)
#define pUART1_CONFIG_RX ((volatile unsigned short *)UART1_CONFIG_RX)
#define pUART1_START_ADDR_HI_RX ((volatile unsigned short *)UART1_START_ADDR_HI_RX)
#define pUART1_START_ADDR_LO_RX ((volatile unsigned short *)UART1_START_ADDR_LO_RX)
#define pUART1_COUNT_RX ((volatile unsigned short *)UART1_COUNT_RX)
#define pUART1_NEXT_DESCR_RX ((volatile unsigned short *)UART1_NEXT_DESCR_RX)
#define pUART1_DESCR_RDY_RX ((volatile unsigned short *)UART1_DESCR_RDY_RX)
#define pUART1_IRQSTAT_RX ((volatile unsigned short *)UART1_IRQSTAT_RX)
#define pUART1_CURR_PTR_TX ((volatile unsigned short *)UART1_CURR_PTR_TX)
#define pUART1_CONFIG_TX ((volatile unsigned short *)UART1_CONFIG_TX)
#define pUART1_START_ADDR_HI_TX ((volatile unsigned short *)UART1_START_ADDR_HI_TX)
#define pUART1_START_ADDR_LO_TX ((volatile unsigned short *)UART1_START_ADDR_LO_TX)
#define pUART1_COUNT_TX ((volatile unsigned short *)UART1_COUNT_TX)
#define pUART1_NEXT_DESCR_TX ((volatile unsigned short *)UART1_NEXT_DESCR_TX)
#define pUART1_DESCR_RDY_TX ((volatile unsigned short *)UART1_DESCR_RDY_TX)
#define pUART1_IRQSTAT_TX ((volatile unsigned short *)UART1_IRQSTAT_TX)
/* TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF) */
#define pTIMER0_STATUS ((volatile unsigned short *)TIMER0_STATUS)
#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
#define pTIMER0_COUNTER_LO ((volatile unsigned short *)TIMER0_COUNTER_LO)
#define pTIMER0_COUNTER_HI ((volatile unsigned short *)TIMER0_COUNTER_HI)
#define pTIMER0_PERIOD_LO ((volatile unsigned short *)TIMER0_PERIOD_LO)
#define pTIMER0_PERIOD_HI ((volatile unsigned short *)TIMER0_PERIOD_HI)
#define pTIMER0_WIDTH_LO ((volatile unsigned short *)TIMER0_WIDTH_LO)
#define pTIMER0_WIDTH_HI ((volatile unsigned short *)TIMER0_WIDTH_HI)
#define pTIMER1_STATUS ((volatile unsigned short *)TIMER1_STATUS)
#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
#define pTIMER1_COUNTER_LO ((volatile unsigned short *)TIMER1_COUNTER_LO)
#define pTIMER1_COUNTER_HI ((volatile unsigned short *)TIMER1_COUNTER_HI)
#define pTIMER1_PERIOD_LO ((volatile unsigned short *)TIMER1_PERIOD_LO)
#define pTIMER1_PERIOD_HI ((volatile unsigned short *)TIMER1_PERIOD_HI)
#define pTIMER1_WIDTH_LO ((volatile unsigned short *)TIMER1_WIDTH_LO)
#define pTIMER1_WIDTH_HI ((volatile unsigned short *)TIMER1_WIDTH_HI)
#define pTIMER2_STATUS ((volatile unsigned short *)TIMER2_STATUS)
#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
#define pTIMER2_COUNTER_LO ((volatile unsigned short *)TIMER2_COUNTER_LO)
#define pTIMER2_COUNTER_HI ((volatile unsigned short *)TIMER2_COUNTER_HI)
#define pTIMER2_PERIOD_LO ((volatile unsigned short *)TIMER2_PERIOD_LO)
#define pTIMER2_PERIOD_HI ((volatile unsigned short *)TIMER2_PERIOD_HI)
#define pTIMER2_WIDTH_LO ((volatile unsigned short *)TIMER2_WIDTH_LO)
#define pTIMER2_WIDTH_HI ((volatile unsigned short *)TIMER2_WIDTH_HI)
/* SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF) */
#define pSPORT0_TX_CONFIG ((volatile unsigned short *)SPORT0_TX_CONFIG)
#define pSPORT0_RX_CONFIG ((volatile unsigned short *)SPORT0_RX_CONFIG)
#define pSPORT0_TX ((volatile short *)SPORT0_TX)
#define pSPORT0_RX ((volatile short *)SPORT0_RX)
#define pSPORT0_TSCLKDIV ((volatile unsigned short *)SPORT0_TSCLKDIV)
#define pSPORT0_RSCLKDIV ((volatile unsigned short *)SPORT0_RSCLKDIV)
#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
#define pSPORT0_MTCS0 ((volatile unsigned short *)SPORT0_MTCS0)
#define pSPORT0_MTCS1 ((volatile unsigned short *)SPORT0_MTCS1)
#define pSPORT0_MTCS2 ((volatile unsigned short *)SPORT0_MTCS2)
#define pSPORT0_MTCS3 ((volatile unsigned short *)SPORT0_MTCS3)
#define pSPORT0_MTCS4 ((volatile unsigned short *)SPORT0_MTCS4)
#define pSPORT0_MTCS5 ((volatile unsigned short *)SPORT0_MTCS5)
#define pSPORT0_MTCS6 ((volatile unsigned short *)SPORT0_MTCS6)
#define pSPORT0_MTCS7 ((volatile unsigned short *)SPORT0_MTCS7)
#define pSPORT0_MRCS0 ((volatile unsigned short *)SPORT0_MRCS0)
#define pSPORT0_MRCS1 ((volatile unsigned short *)SPORT0_MRCS1)
#define pSPORT0_MRCS2 ((volatile unsigned short *)SPORT0_MRCS2)
#define pSPORT0_MRCS3 ((volatile unsigned short *)SPORT0_MRCS3)
#define pSPORT0_MRCS4 ((volatile unsigned short *)SPORT0_MRCS4)
#define pSPORT0_MRCS5 ((volatile unsigned short *)SPORT0_MRCS5)
#define pSPORT0_MRCS6 ((volatile unsigned short *)SPORT0_MRCS6)
#define pSPORT0_MRCS7 ((volatile unsigned short *)SPORT0_MRCS7)
#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
#define pSPORT0_CURR_PTR_RX ((volatile unsigned short *)SPORT0_CURR_PTR_RX)
#define pSPORT0_CONFIG_DMA_RX ((volatile unsigned short *)SPORT0_CONFIG_DMA_RX)
#define pSPORT0_START_ADDR_HI_RX ((volatile unsigned short *)SPORT0_START_ADDR_HI_RX)
#define pSPORT0_START_ADDR_LO_RX ((volatile unsigned short *)SPORT0_START_ADDR_LO_RX)
#define pSPORT0_COUNT_RX ((volatile unsigned short *)SPORT0_COUNT_RX)
#define pSPORT0_NEXT_DESCR_RX ((volatile unsigned short *)SPORT0_NEXT_DESCR_RX)
#define pSPORT0_DESCR_RDY_RX ((volatile unsigned short *)SPORT0_DESCR_RDY_RX)
#define pSPORT0_IRQSTAT_RX ((volatile unsigned short *)SPORT0_IRQSTAT_RX)
#define pSPORT0_CURR_PTR_TX ((volatile unsigned short *)SPORT0_CURR_PTR_TX)
#define pSPORT0_CONFIG_DMA_TX ((volatile unsigned short *)SPORT0_CONFIG_DMA_TX)
#define pSPORT0_START_ADDR_HI_TX ((volatile unsigned short *)SPORT0_START_ADDR_HI_TX)
#define pSPORT0_START_ADDR_LO_TX ((volatile unsigned short *)SPORT0_START_ADDR_LO_TX)
#define pSPORT0_COUNT_TX ((volatile unsigned short *)SPORT0_COUNT_TX)
#define pSPORT0_NEXT_DESCR_TX ((volatile unsigned short *)SPORT0_NEXT_DESCR_TX)
#define pSPORT0_DESCR_RDY_TX ((volatile unsigned short *)SPORT0_DESCR_RDY_TX)
#define pSPORT0_IRQSTAT_TX ((volatile unsigned short *)SPORT0_IRQSTAT_TX)
/* SPORT1 Controller (0xFFC0 2C00-0xFFC0 2FFF) */
#define pSPORT1_TX_CONFIG ((volatile unsigned short *)SPORT1_TX_CONFIG)
#define pSPORT1_RX_CONFIG ((volatile unsigned short *)SPORT1_RX_CONFIG)
#define pSPORT1_TX ((volatile short *)SPORT1_TX)
#define pSPORT1_RX ((volatile short *)SPORT1_RX)
#define pSPORT1_TSCLKDIV ((volatile unsigned short *)SPORT1_TSCLKDIV)
#define pSPORT1_RSCLKDIV ((volatile unsigned short *)SPORT1_RSCLKDIV)
#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
#define pSPORT1_MTCS0 ((volatile unsigned short *)SPORT1_MTCS0)
#define pSPORT1_MTCS1 ((volatile unsigned short *)SPORT1_MTCS1)
#define pSPORT1_MTCS2 ((volatile unsigned short *)SPORT1_MTCS2)
#define pSPORT1_MTCS3 ((volatile unsigned short *)SPORT1_MTCS3)
#define pSPORT1_MTCS4 ((volatile unsigned short *)SPORT1_MTCS4)
#define pSPORT1_MTCS5 ((volatile unsigned short *)SPORT1_MTCS5)
#define pSPORT1_MTCS6 ((volatile unsigned short *)SPORT1_MTCS6)
#define pSPORT1_MTCS7 ((volatile unsigned short *)SPORT1_MTCS7)
#define pSPORT1_MRCS0 ((volatile unsigned short *)SPORT1_MRCS0)
#define pSPORT1_MRCS1 ((volatile unsigned short *)SPORT1_MRCS1)
#define pSPORT1_MRCS2 ((volatile unsigned short *)SPORT1_MRCS2)
#define pSPORT1_MRCS3 ((volatile unsigned short *)SPORT1_MRCS3)
#define pSPORT1_MRCS4 ((volatile unsigned short *)SPORT1_MRCS4)
#define pSPORT1_MRCS5 ((volatile unsigned short *)SPORT1_MRCS5)
#define pSPORT1_MRCS6 ((volatile unsigned short *)SPORT1_MRCS6)
#define pSPORT1_MRCS7 ((volatile unsigned short *)SPORT1_MRCS7)
#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
#define pSPORT1_CURR_PTR_RX ((volatile unsigned short *)SPORT1_CURR_PTR_RX)
#define pSPORT1_CONFIG_DMA_RX ((volatile unsigned short *)SPORT1_CONFIG_DMA_RX)
#define pSPORT1_START_ADDR_HI_RX ((volatile unsigned short *)SPORT1_START_ADDR_HI_RX)
#define pSPORT1_START_ADDR_LO_RX ((volatile unsigned short *)SPORT1_START_ADDR_LO_RX)
#define pSPORT1_COUNT_RX ((volatile unsigned short *)SPORT1_COUNT_RX)
#define pSPORT1_NEXT_DESCR_RX ((volatile unsigned short *)SPORT1_NEXT_DESCR_RX)
#define pSPORT1_DESCR_RDY_RX ((volatile unsigned short *)SPORT1_DESCR_RDY_RX)
#define pSPORT1_IRQSTAT_RX ((volatile unsigned short *)SPORT1_IRQSTAT_RX)
#define pSPORT1_CURR_PTR_TX ((volatile unsigned short *)SPORT1_CURR_PTR_TX)
#define pSPORT1_CONFIG_DMA_TX ((volatile unsigned short *)SPORT1_CONFIG_DMA_TX)
#define pSPORT1_START_ADDR_HI_TX ((volatile unsigned short *)SPORT1_START_ADDR_HI_TX)
#define pSPORT1_START_ADDR_LO_TX ((volatile unsigned short *)SPORT1_START_ADDR_LO_TX)
#define pSPORT1_COUNT_TX ((volatile unsigned short *)SPORT1_COUNT_TX)
#define pSPORT1_NEXT_DESCR_TX ((volatile unsigned short *)SPORT1_NEXT_DESCR_TX)
#define pSPORT1_DESCR_RDY_TX ((volatile unsigned short *)SPORT1_DESCR_RDY_TX)
#define pSPORT1_IRQSTAT_TX ((volatile unsigned short *)SPORT1_IRQSTAT_TX)
/* SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF) */
#define pSPI0_CTL ((volatile unsigned short *)SPI0_CTL)
#define pSPI0_FLG ((volatile unsigned short *)SPI0_FLG)
#define pSPI0_ST ((volatile unsigned short *)SPI0_ST)
#define pSPI0_TDBR ((volatile unsigned short *)SPI0_TDBR)
#define pSPI0_RDBR ((volatile unsigned short *)SPI0_RDBR)
#define pSPI0_BAUD ((volatile unsigned short *)SPI0_BAUD)
#define pSPI0_SHADOW ((volatile unsigned short *)SPI0_SHADOW)
#define pSPI0_CURR_PTR ((volatile unsigned short *)SPI0_CURR_PTR)
#define pSPI0_CONFIG ((volatile unsigned short *)SPI0_CONFIG)
#define pSPI0_START_ADDR_HI ((volatile unsigned short *)SPI0_START_ADDR_HI)
#define pSPI0_START_ADDR_LO ((volatile unsigned short *)SPI0_START_ADDR_LO)
#define pSPI0_COUNT ((volatile unsigned short *)SPI0_COUNT)
#define pSPI0_NEXT_DESCR ((volatile unsigned short *)SPI0_NEXT_DESCR)
#define pSPI0_DESCR_RDY ((volatile unsigned short *)SPI0_DESCR_RDY)
#define pSPI0_DMA_INT ((volatile unsigned short *)SPI0_DMA_INT)
/* SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF) */
#define pSPI1_CTL ((volatile unsigned short *)SPI1_CTL)
#define pSPI1_FLG ((volatile unsigned short *)SPI1_FLG)
#define pSPI1_ST ((volatile unsigned short *)SPI1_ST)
#define pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR)
#define pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR)
#define pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD)
#define pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW)
#define pSPI1_CURR_PTR ((volatile unsigned short *)SPI1_CURR_PTR)
#define pSPI1_CONFIG ((volatile unsigned short *)SPI1_CONFIG)
#define pSPI1_START_ADDR_HI ((volatile unsigned short *)SPI1_START_ADDR_HI)
#define pSPI1_START_ADDR_LO ((volatile unsigned short *)SPI1_START_ADDR_LO)
#define pSPI1_COUNT ((volatile unsigned short *)SPI1_COUNT)
#define pSPI1_NEXT_DESCR ((volatile unsigned short *)SPI1_NEXT_DESCR)
#define pSPI1_DESCR_RDY ((volatile unsigned short *)SPI1_DESCR_RDY)
#define pSPI1_DMA_INT ((volatile unsigned short *)SPI1_DMA_INT)
/* Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF) */
#define pMDD_DCP ((volatile unsigned short *)MDD_DCP)
#define pMDD_DCFG ((volatile unsigned short *)MDD_DCFG)
#define pMDD_DSAH ((volatile unsigned short *)MDD_DSAH)
#define pMDD_DSAL ((volatile unsigned short *)MDD_DSAL)
#define pMDD_DCT ((volatile unsigned short *)MDD_DCT)
#define pMDD_DND ((volatile unsigned short *)MDD_DND)
#define pMDD_DDR ((volatile unsigned short *)MDD_DDR)
#define pMDD_DI ((volatile unsigned short *)MDD_DI)
#define pMDS_DCP ((volatile unsigned short *)MDS_DCP)
#define pMDS_DCFG ((volatile unsigned short *)MDS_DCFG)
#define pMDS_DSAH ((volatile unsigned short *)MDS_DSAH)
#define pMDS_DSAL ((volatile unsigned short *)MDS_DSAL)
#define pMDS_DCT ((volatile unsigned short *)MDS_DCT)
#define pMDS_DND ((volatile unsigned short *)MDS_DND)
#define pMDS_DDR ((volatile unsigned short *)MDS_DDR)
#define pMDS_DI ((volatile unsigned short *)MDS_DI)
/* PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF) */
#define pPCI_CTL ((volatile unsigned short *)PCI_CTL)
#define pPCI_STAT ((volatile unsigned long *)PCI_STAT)
#define pPCI_ICTL ((volatile unsigned long *)PCI_ICTL)
#define pPCI_MBAP (_PTR_TO_VOL_VOID_PTR PCI_MBAP)
#define pPCI_IBAP (_PTR_TO_VOL_VOID_PTR PCI_IBAP)
#define pPCI_CBAP (_PTR_TO_VOL_VOID_PTR PCI_CBAP)
#define pPCI_TMBAP (_PTR_TO_VOL_VOID_PTR PCI_TMBAP)
#define pPCI_TIBAP (_PTR_TO_VOL_VOID_PTR PCI_TIBAP)
/* PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF) */
#define pPCI_DMBARM ((volatile unsigned long *)PCI_DMBARM)
#define pPCI_DIBARM ((volatile unsigned long *)PCI_DIBARM)
#define pPCI_CFG_DIC ((volatile unsigned long *)PCI_CFG_DIC)
#define pPCI_CFG_VIC ((volatile unsigned long *)PCI_CFG_VIC)
#define pPCI_CFG_STAT ((volatile unsigned long *)PCI_CFG_STAT)
#define pPCI_CFG_CMD ((volatile unsigned long *)PCI_CFG_CMD)
#define pPCI_CFG_CC ((volatile unsigned long *)PCI_CFG_CC)
#define pPCI_CFG_RID ((volatile unsigned long *)PCI_CFG_RID)
#define pPCI_CFG_BIST ((volatile unsigned long *)PCI_CFG_BIST)
#define pPCI_CFG_HT ((volatile unsigned long *)PCI_CFG_HT)
#define pPCI_CFG_MLT ((volatile unsigned long *)PCI_CFG_MLT)
#define pPCI_CFG_CLS ((volatile unsigned long *)PCI_CFG_CLS)
#define pPCI_CFG_MBAR ((volatile unsigned long *)PCI_CFG_MBAR)
#define pPCI_CFG_IBAR ((volatile unsigned long *)PCI_CFG_IBAR)
#define pPCI_CFG_SID ((volatile unsigned long *)PCI_CFG_SID)
#define pPCI_CFG_SVID ((volatile unsigned long *)PCI_CFG_SVID)
#define pPCI_CFG_MAXL ((volatile unsigned long *)PCI_CFG_MAXL)
#define pPCI_CFG_MING ((volatile unsigned long *)PCI_CFG_MING)
#define pPCI_CFG_IP ((volatile unsigned long *)PCI_CFG_IP)
#define pPCI_CFG_IL ((volatile unsigned long *)PCI_CFG_IL)
#define pPCI_HMCTL ((volatile unsigned long *)PCI_HMCTL)
/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
#define pDMA_DBP ((volatile unsigned short *)DMA_DBP)
#define pDB_ACOMP (_PTR_TO_VOL_VOID_PTR DB_ACOMP)
#define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
#endif /* _CDEF_BF535_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for register-access.
**
**/
/**********************************************************************************
** System MMR Register Map
***********************************************************************************/
#ifndef _CDEF_BF536_H
#define _CDEF_BF536_H
/* MMR Space Identical to BF537 Processor */
#include <cdefBF537.h>
#endif /* _CDEF_BF536_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for register-access.
**
**/
/**********************************************************************************
** System MMR Register Map
***********************************************************************************/
#ifndef _CDEF_BF537_H
#define _CDEF_BF537_H
/* Include MMRs Common to BF534 */
#include <cdefBF534.h>
/* Include all Core registers and bit definitions */
#include <defBF537.h>
/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
#endif /* _CDEF_BF537_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cdefBF53x.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _CDEFBF53x_H
#define _CDEFBF53x_H
#include <sys/platform.h>
#endif /* _CDEFBF53x_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** cdefBF541.h
**
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the ADSP-BF541 peripherals.
**
************************************************************************************
** System MMR Register Map
************************************************************************************/
#ifndef _CDEF_BF541_H
#define _CDEF_BF541_H
/* include all Core registers and bit definitions */
#include <defBF541.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/** ADSP-BF541 is a non-existent processor -- no additional #defines **/
#define pCHIPID ((volatile unsigned long *)CHIPID)
#endif /* _CDEF_BF541_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** cdefBF542.h
**
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the ADSP-BF542 peripherals.
**
************************************************************************************
** System MMR Register Map
************************************************************************************/
#ifndef _CDEF_BF542_H
#define _CDEF_BF542_H
/* include all Core registers and bit definitions */
#include <defBF542.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
/* ATAPI Registers */
#define pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
#define pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
#define pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
#define pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
#define pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
#define pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
#define pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
#define pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
#define pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
#define pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
#define pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
#define pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
#define pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
#define pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
#define pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
#define pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
#define pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
#define pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
#define pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
#define pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
#define pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
#define pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
#define pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
#define pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
#define pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
/* SDH Registers */
#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
/* USB Control Registers */
#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
/* USB Packet Control Registers */
#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
/* USB Endpoint FIFO Registers */
#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
/* USB OTG Control Registers */
#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
/* USB Phy Control Registers */
#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
/* (APHY_CNTRL is for ADI usage only) */
#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
/* (APHY_CALIB is for ADI usage only) */
#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
/* (PHY_TEST is for ADI usage only) */
#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
/* USB Endpoint 0 Control Registers */
#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
/* USB Endpoint 1 Control Registers */
#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
/* USB Endpoint 2 Control Registers */
#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
/* USB Endpoint 3 Control Registers */
#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
/* USB Endpoint 4 Control Registers */
#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
/* USB Endpoint 5 Control Registers */
#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
/* USB Endpoint 6 Control Registers */
#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
/* USB Endpoint 7 Control Registers */
#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
/* USB Channel 0 Config Registers */
#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
/* USB Channel 1 Config Registers */
#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
/* USB Channel 2 Config Registers */
#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
/* USB Channel 3 Config Registers */
#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
/* USB Channel 4 Config Registers */
#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
/* USB Channel 5 Config Registers */
#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
/* USB Channel 6 Config Registers */
#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
/* USB Channel 7 Config Registers */
#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
/* Keypad Registers */
#define pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
#define pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
#define pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
#define pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
#define pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
#define pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
#endif /* _CDEF_BF542_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** cdefBF544.h
**
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the ADSP-BF544 peripherals.
**
************************************************************************************
** System MMR Register Map
************************************************************************************/
#ifndef _CDEF_BF544_H
#define _CDEF_BF544_H
/* include all Core registers and bit definitions */
#include <defBF544.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
/* Timer Registers */
#define pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
#define pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
#define pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
#define pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
#define pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
#define pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
#define pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
/* Timer Group of 3 */
#define pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
#define pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
#define pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
/* EPPI0 Registers */
#define pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
#define pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
#define pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
#define pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
#define pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
#define pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
#define pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
#define pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
#define pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
#define pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
#define pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
#define pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
#define pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
#define pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
/* Two Wire Interface Registers (TWI1) */
#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
#define pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
#define pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
#define pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
/* CAN Controller 1 Config 1 Registers */
#define pCAN1_MC1 ((volatile unsigned short *)CAN1_MC1)
#define pCAN1_MD1 ((volatile unsigned short *)CAN1_MD1)
#define pCAN1_TRS1 ((volatile unsigned short *)CAN1_TRS1)
#define pCAN1_TRR1 ((volatile unsigned short *)CAN1_TRR1)
#define pCAN1_TA1 ((volatile unsigned short *)CAN1_TA1)
#define pCAN1_AA1 ((volatile unsigned short *)CAN1_AA1)
#define pCAN1_RMP1 ((volatile unsigned short *)CAN1_RMP1)
#define pCAN1_RML1 ((volatile unsigned short *)CAN1_RML1)
#define pCAN1_MBTIF1 ((volatile unsigned short *)CAN1_MBTIF1)
#define pCAN1_MBRIF1 ((volatile unsigned short *)CAN1_MBRIF1)
#define pCAN1_MBIM1 ((volatile unsigned short *)CAN1_MBIM1)
#define pCAN1_RFH1 ((volatile unsigned short *)CAN1_RFH1)
#define pCAN1_OPSS1 ((volatile unsigned short *)CAN1_OPSS1)
/* CAN Controller 1 Config 2 Registers */
#define pCAN1_MC2 ((volatile unsigned short *)CAN1_MC2)
#define pCAN1_MD2 ((volatile unsigned short *)CAN1_MD2)
#define pCAN1_TRS2 ((volatile unsigned short *)CAN1_TRS2)
#define pCAN1_TRR2 ((volatile unsigned short *)CAN1_TRR2)
#define pCAN1_TA2 ((volatile unsigned short *)CAN1_TA2)
#define pCAN1_AA2 ((volatile unsigned short *)CAN1_AA2)
#define pCAN1_RMP2 ((volatile unsigned short *)CAN1_RMP2)
#define pCAN1_RML2 ((volatile unsigned short *)CAN1_RML2)
#define pCAN1_MBTIF2 ((volatile unsigned short *)CAN1_MBTIF2)
#define pCAN1_MBRIF2 ((volatile unsigned short *)CAN1_MBRIF2)
#define pCAN1_MBIM2 ((volatile unsigned short *)CAN1_MBIM2)
#define pCAN1_RFH2 ((volatile unsigned short *)CAN1_RFH2)
#define pCAN1_OPSS2 ((volatile unsigned short *)CAN1_OPSS2)
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
#define pCAN1_CLOCK ((volatile unsigned short *)CAN1_CLOCK)
#define pCAN1_TIMING ((volatile unsigned short *)CAN1_TIMING)
#define pCAN1_DEBUG ((volatile unsigned short *)CAN1_DEBUG)
#define pCAN1_STATUS ((volatile unsigned short *)CAN1_STATUS)
#define pCAN1_CEC ((volatile unsigned short *)CAN1_CEC)
#define pCAN1_GIS ((volatile unsigned short *)CAN1_GIS)
#define pCAN1_GIM ((volatile unsigned short *)CAN1_GIM)
#define pCAN1_GIF ((volatile unsigned short *)CAN1_GIF)
#define pCAN1_CONTROL ((volatile unsigned short *)CAN1_CONTROL)
#define pCAN1_INTR ((volatile unsigned short *)CAN1_INTR)
#define pCAN1_MBTD ((volatile unsigned short *)CAN1_MBTD)
#define pCAN1_EWR ((volatile unsigned short *)CAN1_EWR)
#define pCAN1_ESR ((volatile unsigned short *)CAN1_ESR)
#define pCAN1_UCCNT ((volatile unsigned short *)CAN1_UCCNT)
#define pCAN1_UCRC ((volatile unsigned short *)CAN1_UCRC)
#define pCAN1_UCCNF ((volatile unsigned short *)CAN1_UCCNF)
/* CAN Controller 1 Mailbox Acceptance Registers */
#define pCAN1_AM00L ((volatile unsigned short *)CAN1_AM00L)
#define pCAN1_AM00H ((volatile unsigned short *)CAN1_AM00H)
#define pCAN1_AM01L ((volatile unsigned short *)CAN1_AM01L)
#define pCAN1_AM01H ((volatile unsigned short *)CAN1_AM01H)
#define pCAN1_AM02L ((volatile unsigned short *)CAN1_AM02L)
#define pCAN1_AM02H ((volatile unsigned short *)CAN1_AM02H)
#define pCAN1_AM03L ((volatile unsigned short *)CAN1_AM03L)
#define pCAN1_AM03H ((volatile unsigned short *)CAN1_AM03H)
#define pCAN1_AM04L ((volatile unsigned short *)CAN1_AM04L)
#define pCAN1_AM04H ((volatile unsigned short *)CAN1_AM04H)
#define pCAN1_AM05L ((volatile unsigned short *)CAN1_AM05L)
#define pCAN1_AM05H ((volatile unsigned short *)CAN1_AM05H)
#define pCAN1_AM06L ((volatile unsigned short *)CAN1_AM06L)
#define pCAN1_AM06H ((volatile unsigned short *)CAN1_AM06H)
#define pCAN1_AM07L ((volatile unsigned short *)CAN1_AM07L)
#define pCAN1_AM07H ((volatile unsigned short *)CAN1_AM07H)
#define pCAN1_AM08L ((volatile unsigned short *)CAN1_AM08L)
#define pCAN1_AM08H ((volatile unsigned short *)CAN1_AM08H)
#define pCAN1_AM09L ((volatile unsigned short *)CAN1_AM09L)
#define pCAN1_AM09H ((volatile unsigned short *)CAN1_AM09H)
#define pCAN1_AM10L ((volatile unsigned short *)CAN1_AM10L)
#define pCAN1_AM10H ((volatile unsigned short *)CAN1_AM10H)
#define pCAN1_AM11L ((volatile unsigned short *)CAN1_AM11L)
#define pCAN1_AM11H ((volatile unsigned short *)CAN1_AM11H)
#define pCAN1_AM12L ((volatile unsigned short *)CAN1_AM12L)
#define pCAN1_AM12H ((volatile unsigned short *)CAN1_AM12H)
#define pCAN1_AM13L ((volatile unsigned short *)CAN1_AM13L)
#define pCAN1_AM13H ((volatile unsigned short *)CAN1_AM13H)
#define pCAN1_AM14L ((volatile unsigned short *)CAN1_AM14L)
#define pCAN1_AM14H ((volatile unsigned short *)CAN1_AM14H)
#define pCAN1_AM15L ((volatile unsigned short *)CAN1_AM15L)
#define pCAN1_AM15H ((volatile unsigned short *)CAN1_AM15H)
/* CAN Controller 1 Mailbox Acceptance Registers */
#define pCAN1_AM16L ((volatile unsigned short *)CAN1_AM16L)
#define pCAN1_AM16H ((volatile unsigned short *)CAN1_AM16H)
#define pCAN1_AM17L ((volatile unsigned short *)CAN1_AM17L)
#define pCAN1_AM17H ((volatile unsigned short *)CAN1_AM17H)
#define pCAN1_AM18L ((volatile unsigned short *)CAN1_AM18L)
#define pCAN1_AM18H ((volatile unsigned short *)CAN1_AM18H)
#define pCAN1_AM19L ((volatile unsigned short *)CAN1_AM19L)
#define pCAN1_AM19H ((volatile unsigned short *)CAN1_AM19H)
#define pCAN1_AM20L ((volatile unsigned short *)CAN1_AM20L)
#define pCAN1_AM20H ((volatile unsigned short *)CAN1_AM20H)
#define pCAN1_AM21L ((volatile unsigned short *)CAN1_AM21L)
#define pCAN1_AM21H ((volatile unsigned short *)CAN1_AM21H)
#define pCAN1_AM22L ((volatile unsigned short *)CAN1_AM22L)
#define pCAN1_AM22H ((volatile unsigned short *)CAN1_AM22H)
#define pCAN1_AM23L ((volatile unsigned short *)CAN1_AM23L)
#define pCAN1_AM23H ((volatile unsigned short *)CAN1_AM23H)
#define pCAN1_AM24L ((volatile unsigned short *)CAN1_AM24L)
#define pCAN1_AM24H ((volatile unsigned short *)CAN1_AM24H)
#define pCAN1_AM25L ((volatile unsigned short *)CAN1_AM25L)
#define pCAN1_AM25H ((volatile unsigned short *)CAN1_AM25H)
#define pCAN1_AM26L ((volatile unsigned short *)CAN1_AM26L)
#define pCAN1_AM26H ((volatile unsigned short *)CAN1_AM26H)
#define pCAN1_AM27L ((volatile unsigned short *)CAN1_AM27L)
#define pCAN1_AM27H ((volatile unsigned short *)CAN1_AM27H)
#define pCAN1_AM28L ((volatile unsigned short *)CAN1_AM28L)
#define pCAN1_AM28H ((volatile unsigned short *)CAN1_AM28H)
#define pCAN1_AM29L ((volatile unsigned short *)CAN1_AM29L)
#define pCAN1_AM29H ((volatile unsigned short *)CAN1_AM29H)
#define pCAN1_AM30L ((volatile unsigned short *)CAN1_AM30L)
#define pCAN1_AM30H ((volatile unsigned short *)CAN1_AM30H)
#define pCAN1_AM31L ((volatile unsigned short *)CAN1_AM31L)
#define pCAN1_AM31H ((volatile unsigned short *)CAN1_AM31H)
/* CAN Controller 1 Mailbox Data Registers */
#define pCAN1_MB00_DATA0 ((volatile unsigned short *)CAN1_MB00_DATA0)
#define pCAN1_MB00_DATA1 ((volatile unsigned short *)CAN1_MB00_DATA1)
#define pCAN1_MB00_DATA2 ((volatile unsigned short *)CAN1_MB00_DATA2)
#define pCAN1_MB00_DATA3 ((volatile unsigned short *)CAN1_MB00_DATA3)
#define pCAN1_MB00_LENGTH ((volatile unsigned short *)CAN1_MB00_LENGTH)
#define pCAN1_MB00_TIMESTAMP ((volatile unsigned short *)CAN1_MB00_TIMESTAMP)
#define pCAN1_MB00_ID0 ((volatile unsigned short *)CAN1_MB00_ID0)
#define pCAN1_MB00_ID1 ((volatile unsigned short *)CAN1_MB00_ID1)
#define pCAN1_MB01_DATA0 ((volatile unsigned short *)CAN1_MB01_DATA0)
#define pCAN1_MB01_DATA1 ((volatile unsigned short *)CAN1_MB01_DATA1)
#define pCAN1_MB01_DATA2 ((volatile unsigned short *)CAN1_MB01_DATA2)
#define pCAN1_MB01_DATA3 ((volatile unsigned short *)CAN1_MB01_DATA3)
#define pCAN1_MB01_LENGTH ((volatile unsigned short *)CAN1_MB01_LENGTH)
#define pCAN1_MB01_TIMESTAMP ((volatile unsigned short *)CAN1_MB01_TIMESTAMP)
#define pCAN1_MB01_ID0 ((volatile unsigned short *)CAN1_MB01_ID0)
#define pCAN1_MB01_ID1 ((volatile unsigned short *)CAN1_MB01_ID1)
#define pCAN1_MB02_DATA0 ((volatile unsigned short *)CAN1_MB02_DATA0)
#define pCAN1_MB02_DATA1 ((volatile unsigned short *)CAN1_MB02_DATA1)
#define pCAN1_MB02_DATA2 ((volatile unsigned short *)CAN1_MB02_DATA2)
#define pCAN1_MB02_DATA3 ((volatile unsigned short *)CAN1_MB02_DATA3)
#define pCAN1_MB02_LENGTH ((volatile unsigned short *)CAN1_MB02_LENGTH)
#define pCAN1_MB02_TIMESTAMP ((volatile unsigned short *)CAN1_MB02_TIMESTAMP)
#define pCAN1_MB02_ID0 ((volatile unsigned short *)CAN1_MB02_ID0)
#define pCAN1_MB02_ID1 ((volatile unsigned short *)CAN1_MB02_ID1)
#define pCAN1_MB03_DATA0 ((volatile unsigned short *)CAN1_MB03_DATA0)
#define pCAN1_MB03_DATA1 ((volatile unsigned short *)CAN1_MB03_DATA1)
#define pCAN1_MB03_DATA2 ((volatile unsigned short *)CAN1_MB03_DATA2)
#define pCAN1_MB03_DATA3 ((volatile unsigned short *)CAN1_MB03_DATA3)
#define pCAN1_MB03_LENGTH ((volatile unsigned short *)CAN1_MB03_LENGTH)
#define pCAN1_MB03_TIMESTAMP ((volatile unsigned short *)CAN1_MB03_TIMESTAMP)
#define pCAN1_MB03_ID0 ((volatile unsigned short *)CAN1_MB03_ID0)
#define pCAN1_MB03_ID1 ((volatile unsigned short *)CAN1_MB03_ID1)
#define pCAN1_MB04_DATA0 ((volatile unsigned short *)CAN1_MB04_DATA0)
#define pCAN1_MB04_DATA1 ((volatile unsigned short *)CAN1_MB04_DATA1)
#define pCAN1_MB04_DATA2 ((volatile unsigned short *)CAN1_MB04_DATA2)
#define pCAN1_MB04_DATA3 ((volatile unsigned short *)CAN1_MB04_DATA3)
#define pCAN1_MB04_LENGTH ((volatile unsigned short *)CAN1_MB04_LENGTH)
#define pCAN1_MB04_TIMESTAMP ((volatile unsigned short *)CAN1_MB04_TIMESTAMP)
#define pCAN1_MB04_ID0 ((volatile unsigned short *)CAN1_MB04_ID0)
#define pCAN1_MB04_ID1 ((volatile unsigned short *)CAN1_MB04_ID1)
#define pCAN1_MB05_DATA0 ((volatile unsigned short *)CAN1_MB05_DATA0)
#define pCAN1_MB05_DATA1 ((volatile unsigned short *)CAN1_MB05_DATA1)
#define pCAN1_MB05_DATA2 ((volatile unsigned short *)CAN1_MB05_DATA2)
#define pCAN1_MB05_DATA3 ((volatile unsigned short *)CAN1_MB05_DATA3)
#define pCAN1_MB05_LENGTH ((volatile unsigned short *)CAN1_MB05_LENGTH)
#define pCAN1_MB05_TIMESTAMP ((volatile unsigned short *)CAN1_MB05_TIMESTAMP)
#define pCAN1_MB05_ID0 ((volatile unsigned short *)CAN1_MB05_ID0)
#define pCAN1_MB05_ID1 ((volatile unsigned short *)CAN1_MB05_ID1)
#define pCAN1_MB06_DATA0 ((volatile unsigned short *)CAN1_MB06_DATA0)
#define pCAN1_MB06_DATA1 ((volatile unsigned short *)CAN1_MB06_DATA1)
#define pCAN1_MB06_DATA2 ((volatile unsigned short *)CAN1_MB06_DATA2)
#define pCAN1_MB06_DATA3 ((volatile unsigned short *)CAN1_MB06_DATA3)
#define pCAN1_MB06_LENGTH ((volatile unsigned short *)CAN1_MB06_LENGTH)
#define pCAN1_MB06_TIMESTAMP ((volatile unsigned short *)CAN1_MB06_TIMESTAMP)
#define pCAN1_MB06_ID0 ((volatile unsigned short *)CAN1_MB06_ID0)
#define pCAN1_MB06_ID1 ((volatile unsigned short *)CAN1_MB06_ID1)
#define pCAN1_MB07_DATA0 ((volatile unsigned short *)CAN1_MB07_DATA0)
#define pCAN1_MB07_DATA1 ((volatile unsigned short *)CAN1_MB07_DATA1)
#define pCAN1_MB07_DATA2 ((volatile unsigned short *)CAN1_MB07_DATA2)
#define pCAN1_MB07_DATA3 ((volatile unsigned short *)CAN1_MB07_DATA3)
#define pCAN1_MB07_LENGTH ((volatile unsigned short *)CAN1_MB07_LENGTH)
#define pCAN1_MB07_TIMESTAMP ((volatile unsigned short *)CAN1_MB07_TIMESTAMP)
#define pCAN1_MB07_ID0 ((volatile unsigned short *)CAN1_MB07_ID0)
#define pCAN1_MB07_ID1 ((volatile unsigned short *)CAN1_MB07_ID1)
#define pCAN1_MB08_DATA0 ((volatile unsigned short *)CAN1_MB08_DATA0)
#define pCAN1_MB08_DATA1 ((volatile unsigned short *)CAN1_MB08_DATA1)
#define pCAN1_MB08_DATA2 ((volatile unsigned short *)CAN1_MB08_DATA2)
#define pCAN1_MB08_DATA3 ((volatile unsigned short *)CAN1_MB08_DATA3)
#define pCAN1_MB08_LENGTH ((volatile unsigned short *)CAN1_MB08_LENGTH)
#define pCAN1_MB08_TIMESTAMP ((volatile unsigned short *)CAN1_MB08_TIMESTAMP)
#define pCAN1_MB08_ID0 ((volatile unsigned short *)CAN1_MB08_ID0)
#define pCAN1_MB08_ID1 ((volatile unsigned short *)CAN1_MB08_ID1)
#define pCAN1_MB09_DATA0 ((volatile unsigned short *)CAN1_MB09_DATA0)
#define pCAN1_MB09_DATA1 ((volatile unsigned short *)CAN1_MB09_DATA1)
#define pCAN1_MB09_DATA2 ((volatile unsigned short *)CAN1_MB09_DATA2)
#define pCAN1_MB09_DATA3 ((volatile unsigned short *)CAN1_MB09_DATA3)
#define pCAN1_MB09_LENGTH ((volatile unsigned short *)CAN1_MB09_LENGTH)
#define pCAN1_MB09_TIMESTAMP ((volatile unsigned short *)CAN1_MB09_TIMESTAMP)
#define pCAN1_MB09_ID0 ((volatile unsigned short *)CAN1_MB09_ID0)
#define pCAN1_MB09_ID1 ((volatile unsigned short *)CAN1_MB09_ID1)
#define pCAN1_MB10_DATA0 ((volatile unsigned short *)CAN1_MB10_DATA0)
#define pCAN1_MB10_DATA1 ((volatile unsigned short *)CAN1_MB10_DATA1)
#define pCAN1_MB10_DATA2 ((volatile unsigned short *)CAN1_MB10_DATA2)
#define pCAN1_MB10_DATA3 ((volatile unsigned short *)CAN1_MB10_DATA3)
#define pCAN1_MB10_LENGTH ((volatile unsigned short *)CAN1_MB10_LENGTH)
#define pCAN1_MB10_TIMESTAMP ((volatile unsigned short *)CAN1_MB10_TIMESTAMP)
#define pCAN1_MB10_ID0 ((volatile unsigned short *)CAN1_MB10_ID0)
#define pCAN1_MB10_ID1 ((volatile unsigned short *)CAN1_MB10_ID1)
#define pCAN1_MB11_DATA0 ((volatile unsigned short *)CAN1_MB11_DATA0)
#define pCAN1_MB11_DATA1 ((volatile unsigned short *)CAN1_MB11_DATA1)
#define pCAN1_MB11_DATA2 ((volatile unsigned short *)CAN1_MB11_DATA2)
#define pCAN1_MB11_DATA3 ((volatile unsigned short *)CAN1_MB11_DATA3)
#define pCAN1_MB11_LENGTH ((volatile unsigned short *)CAN1_MB11_LENGTH)
#define pCAN1_MB11_TIMESTAMP ((volatile unsigned short *)CAN1_MB11_TIMESTAMP)
#define pCAN1_MB11_ID0 ((volatile unsigned short *)CAN1_MB11_ID0)
#define pCAN1_MB11_ID1 ((volatile unsigned short *)CAN1_MB11_ID1)
#define pCAN1_MB12_DATA0 ((volatile unsigned short *)CAN1_MB12_DATA0)
#define pCAN1_MB12_DATA1 ((volatile unsigned short *)CAN1_MB12_DATA1)
#define pCAN1_MB12_DATA2 ((volatile unsigned short *)CAN1_MB12_DATA2)
#define pCAN1_MB12_DATA3 ((volatile unsigned short *)CAN1_MB12_DATA3)
#define pCAN1_MB12_LENGTH ((volatile unsigned short *)CAN1_MB12_LENGTH)
#define pCAN1_MB12_TIMESTAMP ((volatile unsigned short *)CAN1_MB12_TIMESTAMP)
#define pCAN1_MB12_ID0 ((volatile unsigned short *)CAN1_MB12_ID0)
#define pCAN1_MB12_ID1 ((volatile unsigned short *)CAN1_MB12_ID1)
#define pCAN1_MB13_DATA0 ((volatile unsigned short *)CAN1_MB13_DATA0)
#define pCAN1_MB13_DATA1 ((volatile unsigned short *)CAN1_MB13_DATA1)
#define pCAN1_MB13_DATA2 ((volatile unsigned short *)CAN1_MB13_DATA2)
#define pCAN1_MB13_DATA3 ((volatile unsigned short *)CAN1_MB13_DATA3)
#define pCAN1_MB13_LENGTH ((volatile unsigned short *)CAN1_MB13_LENGTH)
#define pCAN1_MB13_TIMESTAMP ((volatile unsigned short *)CAN1_MB13_TIMESTAMP)
#define pCAN1_MB13_ID0 ((volatile unsigned short *)CAN1_MB13_ID0)
#define pCAN1_MB13_ID1 ((volatile unsigned short *)CAN1_MB13_ID1)
#define pCAN1_MB14_DATA0 ((volatile unsigned short *)CAN1_MB14_DATA0)
#define pCAN1_MB14_DATA1 ((volatile unsigned short *)CAN1_MB14_DATA1)
#define pCAN1_MB14_DATA2 ((volatile unsigned short *)CAN1_MB14_DATA2)
#define pCAN1_MB14_DATA3 ((volatile unsigned short *)CAN1_MB14_DATA3)
#define pCAN1_MB14_LENGTH ((volatile unsigned short *)CAN1_MB14_LENGTH)
#define pCAN1_MB14_TIMESTAMP ((volatile unsigned short *)CAN1_MB14_TIMESTAMP)
#define pCAN1_MB14_ID0 ((volatile unsigned short *)CAN1_MB14_ID0)
#define pCAN1_MB14_ID1 ((volatile unsigned short *)CAN1_MB14_ID1)
#define pCAN1_MB15_DATA0 ((volatile unsigned short *)CAN1_MB15_DATA0)
#define pCAN1_MB15_DATA1 ((volatile unsigned short *)CAN1_MB15_DATA1)
#define pCAN1_MB15_DATA2 ((volatile unsigned short *)CAN1_MB15_DATA2)
#define pCAN1_MB15_DATA3 ((volatile unsigned short *)CAN1_MB15_DATA3)
#define pCAN1_MB15_LENGTH ((volatile unsigned short *)CAN1_MB15_LENGTH)
#define pCAN1_MB15_TIMESTAMP ((volatile unsigned short *)CAN1_MB15_TIMESTAMP)
#define pCAN1_MB15_ID0 ((volatile unsigned short *)CAN1_MB15_ID0)
#define pCAN1_MB15_ID1 ((volatile unsigned short *)CAN1_MB15_ID1)
/* CAN Controller 1 Mailbox Data Registers */
#define pCAN1_MB16_DATA0 ((volatile unsigned short *)CAN1_MB16_DATA0)
#define pCAN1_MB16_DATA1 ((volatile unsigned short *)CAN1_MB16_DATA1)
#define pCAN1_MB16_DATA2 ((volatile unsigned short *)CAN1_MB16_DATA2)
#define pCAN1_MB16_DATA3 ((volatile unsigned short *)CAN1_MB16_DATA3)
#define pCAN1_MB16_LENGTH ((volatile unsigned short *)CAN1_MB16_LENGTH)
#define pCAN1_MB16_TIMESTAMP ((volatile unsigned short *)CAN1_MB16_TIMESTAMP)
#define pCAN1_MB16_ID0 ((volatile unsigned short *)CAN1_MB16_ID0)
#define pCAN1_MB16_ID1 ((volatile unsigned short *)CAN1_MB16_ID1)
#define pCAN1_MB17_DATA0 ((volatile unsigned short *)CAN1_MB17_DATA0)
#define pCAN1_MB17_DATA1 ((volatile unsigned short *)CAN1_MB17_DATA1)
#define pCAN1_MB17_DATA2 ((volatile unsigned short *)CAN1_MB17_DATA2)
#define pCAN1_MB17_DATA3 ((volatile unsigned short *)CAN1_MB17_DATA3)
#define pCAN1_MB17_LENGTH ((volatile unsigned short *)CAN1_MB17_LENGTH)
#define pCAN1_MB17_TIMESTAMP ((volatile unsigned short *)CAN1_MB17_TIMESTAMP)
#define pCAN1_MB17_ID0 ((volatile unsigned short *)CAN1_MB17_ID0)
#define pCAN1_MB17_ID1 ((volatile unsigned short *)CAN1_MB17_ID1)
#define pCAN1_MB18_DATA0 ((volatile unsigned short *)CAN1_MB18_DATA0)
#define pCAN1_MB18_DATA1 ((volatile unsigned short *)CAN1_MB18_DATA1)
#define pCAN1_MB18_DATA2 ((volatile unsigned short *)CAN1_MB18_DATA2)
#define pCAN1_MB18_DATA3 ((volatile unsigned short *)CAN1_MB18_DATA3)
#define pCAN1_MB18_LENGTH ((volatile unsigned short *)CAN1_MB18_LENGTH)
#define pCAN1_MB18_TIMESTAMP ((volatile unsigned short *)CAN1_MB18_TIMESTAMP)
#define pCAN1_MB18_ID0 ((volatile unsigned short *)CAN1_MB18_ID0)
#define pCAN1_MB18_ID1 ((volatile unsigned short *)CAN1_MB18_ID1)
#define pCAN1_MB19_DATA0 ((volatile unsigned short *)CAN1_MB19_DATA0)
#define pCAN1_MB19_DATA1 ((volatile unsigned short *)CAN1_MB19_DATA1)
#define pCAN1_MB19_DATA2 ((volatile unsigned short *)CAN1_MB19_DATA2)
#define pCAN1_MB19_DATA3 ((volatile unsigned short *)CAN1_MB19_DATA3)
#define pCAN1_MB19_LENGTH ((volatile unsigned short *)CAN1_MB19_LENGTH)
#define pCAN1_MB19_TIMESTAMP ((volatile unsigned short *)CAN1_MB19_TIMESTAMP)
#define pCAN1_MB19_ID0 ((volatile unsigned short *)CAN1_MB19_ID0)
#define pCAN1_MB19_ID1 ((volatile unsigned short *)CAN1_MB19_ID1)
#define pCAN1_MB20_DATA0 ((volatile unsigned short *)CAN1_MB20_DATA0)
#define pCAN1_MB20_DATA1 ((volatile unsigned short *)CAN1_MB20_DATA1)
#define pCAN1_MB20_DATA2 ((volatile unsigned short *)CAN1_MB20_DATA2)
#define pCAN1_MB20_DATA3 ((volatile unsigned short *)CAN1_MB20_DATA3)
#define pCAN1_MB20_LENGTH ((volatile unsigned short *)CAN1_MB20_LENGTH)
#define pCAN1_MB20_TIMESTAMP ((volatile unsigned short *)CAN1_MB20_TIMESTAMP)
#define pCAN1_MB20_ID0 ((volatile unsigned short *)CAN1_MB20_ID0)
#define pCAN1_MB20_ID1 ((volatile unsigned short *)CAN1_MB20_ID1)
#define pCAN1_MB21_DATA0 ((volatile unsigned short *)CAN1_MB21_DATA0)
#define pCAN1_MB21_DATA1 ((volatile unsigned short *)CAN1_MB21_DATA1)
#define pCAN1_MB21_DATA2 ((volatile unsigned short *)CAN1_MB21_DATA2)
#define pCAN1_MB21_DATA3 ((volatile unsigned short *)CAN1_MB21_DATA3)
#define pCAN1_MB21_LENGTH ((volatile unsigned short *)CAN1_MB21_LENGTH)
#define pCAN1_MB21_TIMESTAMP ((volatile unsigned short *)CAN1_MB21_TIMESTAMP)
#define pCAN1_MB21_ID0 ((volatile unsigned short *)CAN1_MB21_ID0)
#define pCAN1_MB21_ID1 ((volatile unsigned short *)CAN1_MB21_ID1)
#define pCAN1_MB22_DATA0 ((volatile unsigned short *)CAN1_MB22_DATA0)
#define pCAN1_MB22_DATA1 ((volatile unsigned short *)CAN1_MB22_DATA1)
#define pCAN1_MB22_DATA2 ((volatile unsigned short *)CAN1_MB22_DATA2)
#define pCAN1_MB22_DATA3 ((volatile unsigned short *)CAN1_MB22_DATA3)
#define pCAN1_MB22_LENGTH ((volatile unsigned short *)CAN1_MB22_LENGTH)
#define pCAN1_MB22_TIMESTAMP ((volatile unsigned short *)CAN1_MB22_TIMESTAMP)
#define pCAN1_MB22_ID0 ((volatile unsigned short *)CAN1_MB22_ID0)
#define pCAN1_MB22_ID1 ((volatile unsigned short *)CAN1_MB22_ID1)
#define pCAN1_MB23_DATA0 ((volatile unsigned short *)CAN1_MB23_DATA0)
#define pCAN1_MB23_DATA1 ((volatile unsigned short *)CAN1_MB23_DATA1)
#define pCAN1_MB23_DATA2 ((volatile unsigned short *)CAN1_MB23_DATA2)
#define pCAN1_MB23_DATA3 ((volatile unsigned short *)CAN1_MB23_DATA3)
#define pCAN1_MB23_LENGTH ((volatile unsigned short *)CAN1_MB23_LENGTH)
#define pCAN1_MB23_TIMESTAMP ((volatile unsigned short *)CAN1_MB23_TIMESTAMP)
#define pCAN1_MB23_ID0 ((volatile unsigned short *)CAN1_MB23_ID0)
#define pCAN1_MB23_ID1 ((volatile unsigned short *)CAN1_MB23_ID1)
#define pCAN1_MB24_DATA0 ((volatile unsigned short *)CAN1_MB24_DATA0)
#define pCAN1_MB24_DATA1 ((volatile unsigned short *)CAN1_MB24_DATA1)
#define pCAN1_MB24_DATA2 ((volatile unsigned short *)CAN1_MB24_DATA2)
#define pCAN1_MB24_DATA3 ((volatile unsigned short *)CAN1_MB24_DATA3)
#define pCAN1_MB24_LENGTH ((volatile unsigned short *)CAN1_MB24_LENGTH)
#define pCAN1_MB24_TIMESTAMP ((volatile unsigned short *)CAN1_MB24_TIMESTAMP)
#define pCAN1_MB24_ID0 ((volatile unsigned short *)CAN1_MB24_ID0)
#define pCAN1_MB24_ID1 ((volatile unsigned short *)CAN1_MB24_ID1)
#define pCAN1_MB25_DATA0 ((volatile unsigned short *)CAN1_MB25_DATA0)
#define pCAN1_MB25_DATA1 ((volatile unsigned short *)CAN1_MB25_DATA1)
#define pCAN1_MB25_DATA2 ((volatile unsigned short *)CAN1_MB25_DATA2)
#define pCAN1_MB25_DATA3 ((volatile unsigned short *)CAN1_MB25_DATA3)
#define pCAN1_MB25_LENGTH ((volatile unsigned short *)CAN1_MB25_LENGTH)
#define pCAN1_MB25_TIMESTAMP ((volatile unsigned short *)CAN1_MB25_TIMESTAMP)
#define pCAN1_MB25_ID0 ((volatile unsigned short *)CAN1_MB25_ID0)
#define pCAN1_MB25_ID1 ((volatile unsigned short *)CAN1_MB25_ID1)
#define pCAN1_MB26_DATA0 ((volatile unsigned short *)CAN1_MB26_DATA0)
#define pCAN1_MB26_DATA1 ((volatile unsigned short *)CAN1_MB26_DATA1)
#define pCAN1_MB26_DATA2 ((volatile unsigned short *)CAN1_MB26_DATA2)
#define pCAN1_MB26_DATA3 ((volatile unsigned short *)CAN1_MB26_DATA3)
#define pCAN1_MB26_LENGTH ((volatile unsigned short *)CAN1_MB26_LENGTH)
#define pCAN1_MB26_TIMESTAMP ((volatile unsigned short *)CAN1_MB26_TIMESTAMP)
#define pCAN1_MB26_ID0 ((volatile unsigned short *)CAN1_MB26_ID0)
#define pCAN1_MB26_ID1 ((volatile unsigned short *)CAN1_MB26_ID1)
#define pCAN1_MB27_DATA0 ((volatile unsigned short *)CAN1_MB27_DATA0)
#define pCAN1_MB27_DATA1 ((volatile unsigned short *)CAN1_MB27_DATA1)
#define pCAN1_MB27_DATA2 ((volatile unsigned short *)CAN1_MB27_DATA2)
#define pCAN1_MB27_DATA3 ((volatile unsigned short *)CAN1_MB27_DATA3)
#define pCAN1_MB27_LENGTH ((volatile unsigned short *)CAN1_MB27_LENGTH)
#define pCAN1_MB27_TIMESTAMP ((volatile unsigned short *)CAN1_MB27_TIMESTAMP)
#define pCAN1_MB27_ID0 ((volatile unsigned short *)CAN1_MB27_ID0)
#define pCAN1_MB27_ID1 ((volatile unsigned short *)CAN1_MB27_ID1)
#define pCAN1_MB28_DATA0 ((volatile unsigned short *)CAN1_MB28_DATA0)
#define pCAN1_MB28_DATA1 ((volatile unsigned short *)CAN1_MB28_DATA1)
#define pCAN1_MB28_DATA2 ((volatile unsigned short *)CAN1_MB28_DATA2)
#define pCAN1_MB28_DATA3 ((volatile unsigned short *)CAN1_MB28_DATA3)
#define pCAN1_MB28_LENGTH ((volatile unsigned short *)CAN1_MB28_LENGTH)
#define pCAN1_MB28_TIMESTAMP ((volatile unsigned short *)CAN1_MB28_TIMESTAMP)
#define pCAN1_MB28_ID0 ((volatile unsigned short *)CAN1_MB28_ID0)
#define pCAN1_MB28_ID1 ((volatile unsigned short *)CAN1_MB28_ID1)
#define pCAN1_MB29_DATA0 ((volatile unsigned short *)CAN1_MB29_DATA0)
#define pCAN1_MB29_DATA1 ((volatile unsigned short *)CAN1_MB29_DATA1)
#define pCAN1_MB29_DATA2 ((volatile unsigned short *)CAN1_MB29_DATA2)
#define pCAN1_MB29_DATA3 ((volatile unsigned short *)CAN1_MB29_DATA3)
#define pCAN1_MB29_LENGTH ((volatile unsigned short *)CAN1_MB29_LENGTH)
#define pCAN1_MB29_TIMESTAMP ((volatile unsigned short *)CAN1_MB29_TIMESTAMP)
#define pCAN1_MB29_ID0 ((volatile unsigned short *)CAN1_MB29_ID0)
#define pCAN1_MB29_ID1 ((volatile unsigned short *)CAN1_MB29_ID1)
#define pCAN1_MB30_DATA0 ((volatile unsigned short *)CAN1_MB30_DATA0)
#define pCAN1_MB30_DATA1 ((volatile unsigned short *)CAN1_MB30_DATA1)
#define pCAN1_MB30_DATA2 ((volatile unsigned short *)CAN1_MB30_DATA2)
#define pCAN1_MB30_DATA3 ((volatile unsigned short *)CAN1_MB30_DATA3)
#define pCAN1_MB30_LENGTH ((volatile unsigned short *)CAN1_MB30_LENGTH)
#define pCAN1_MB30_TIMESTAMP ((volatile unsigned short *)CAN1_MB30_TIMESTAMP)
#define pCAN1_MB30_ID0 ((volatile unsigned short *)CAN1_MB30_ID0)
#define pCAN1_MB30_ID1 ((volatile unsigned short *)CAN1_MB30_ID1)
#define pCAN1_MB31_DATA0 ((volatile unsigned short *)CAN1_MB31_DATA0)
#define pCAN1_MB31_DATA1 ((volatile unsigned short *)CAN1_MB31_DATA1)
#define pCAN1_MB31_DATA2 ((volatile unsigned short *)CAN1_MB31_DATA2)
#define pCAN1_MB31_DATA3 ((volatile unsigned short *)CAN1_MB31_DATA3)
#define pCAN1_MB31_LENGTH ((volatile unsigned short *)CAN1_MB31_LENGTH)
#define pCAN1_MB31_TIMESTAMP ((volatile unsigned short *)CAN1_MB31_TIMESTAMP)
#define pCAN1_MB31_ID0 ((volatile unsigned short *)CAN1_MB31_ID0)
#define pCAN1_MB31_ID1 ((volatile unsigned short *)CAN1_MB31_ID1)
/* HOST Port Registers */
#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
/* Pixel Compositor (PIXC) Registers */
#define pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
#define pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
#define pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
#define pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
#define pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
#define pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
#define pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
#define pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
#define pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
#define pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
#define pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
#define pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
#define pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
#define pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
#define pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
#define pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
#define pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
#endif /* _CDEF_BF544_H */

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@ -0,0 +1,490 @@
/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** cdefBF547.h
**
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the ADSP-BF547 peripherals.
**
************************************************************************************
** System MMR Register Map
************************************************************************************/
#ifndef _CDEF_BF547_H
#define _CDEF_BF547_H
/* include all Core registers and bit definitions */
#include <defBF547.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
/* Timer Registers */
#define pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
#define pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
#define pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
#define pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
#define pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
#define pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
#define pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
/* Timer Group of 3 */
#define pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
#define pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
#define pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
/* SPORT0 Registers */
#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
/* EPPI0 Registers */
#define pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
#define pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
#define pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
#define pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
#define pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
#define pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
#define pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
#define pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
#define pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
#define pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
#define pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
#define pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
#define pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
#define pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
/* UART2 Registers */
#define pUART2_DLL ((volatile unsigned short *)UART2_DLL)
#define pUART2_DLH ((volatile unsigned short *)UART2_DLH)
#define pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
#define pUART2_LCR ((volatile unsigned short *)UART2_LCR)
#define pUART2_MCR ((volatile unsigned short *)UART2_MCR)
#define pUART2_LSR ((volatile unsigned short *)UART2_LSR)
#define pUART2_MSR ((volatile unsigned short *)UART2_MSR)
#define pUART2_SCR ((volatile unsigned short *)UART2_SCR)
#define pUART2_IER_SET ((volatile unsigned short *)UART2_IER_SET)
#define pUART2_IER_CLEAR ((volatile unsigned short *)UART2_IER_CLEAR)
#define pUART2_THR ((volatile unsigned short *)UART2_THR)
#define pUART2_RBR ((volatile unsigned short *)UART2_RBR)
/* Two Wire Interface Registers (TWI1) */
#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
#define pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
#define pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
#define pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
/* SPI2 Registers */
#define pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
#define pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
#define pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
#define pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
#define pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
#define pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
#define pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
/* ATAPI Registers */
#define pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
#define pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
#define pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
#define pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
#define pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
#define pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
#define pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
#define pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
#define pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
#define pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
#define pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
#define pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
#define pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
#define pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
#define pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
#define pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
#define pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
#define pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
#define pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
#define pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
#define pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
#define pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
#define pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
#define pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
#define pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
/* SDH Registers */
#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
/* HOST Port Registers */
#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
/* USB Control Registers */
#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
/* USB Packet Control Registers */
#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
/* USB Endpoint FIFO Registers */
#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
/* USB OTG Control Registers */
#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
/* USB Phy Control Registers */
#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
/* (APHY_CNTRL is for ADI usage only) */
#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
/* (APHY_CALIB is for ADI usage only) */
#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
/* (PHY_TEST is for ADI usage only) */
#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
/* USB Endpoint 0 Control Registers */
#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
/* USB Endpoint 1 Control Registers */
#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
/* USB Endpoint 2 Control Registers */
#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
/* USB Endpoint 3 Control Registers */
#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
/* USB Endpoint 4 Control Registers */
#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
/* USB Endpoint 5 Control Registers */
#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
/* USB Endpoint 6 Control Registers */
#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
/* USB Endpoint 7 Control Registers */
#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
/* USB Channel 0 Config Registers */
#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
/* USB Channel 1 Config Registers */
#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
/* USB Channel 2 Config Registers */
#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
/* USB Channel 3 Config Registers */
#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
/* USB Channel 4 Config Registers */
#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
/* USB Channel 5 Config Registers */
#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
/* USB Channel 6 Config Registers */
#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
/* USB Channel 7 Config Registers */
#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
/* Keypad Registers */
#define pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
#define pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
#define pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
#define pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
#define pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
#define pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
/* Pixel Compositor (PIXC) Registers */
#define pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
#define pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
#define pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
#define pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
#define pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
#define pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
#define pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
#define pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
#define pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
#define pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
#define pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
#define pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
#define pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
#define pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
#define pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
#define pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
#define pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
#endif /* _CDEF_BF547_H */

873
libgloss/bfin/include/cdefBF548.h Normal file
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@ -0,0 +1,873 @@
/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** cdefBF548.h
**
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for the ADSP-BF548 peripherals.
**
************************************************************************************
** System MMR Register Map
************************************************************************************/
#ifndef _CDEF_BF548_H
#define _CDEF_BF548_H
/* include all Core registers and bit definitions */
#include <defBF548.h>
/* include core specific register pointer definitions */
#include <cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <cdefBF54x_base.h>
/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
/* Timer Registers */
#define pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
#define pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
#define pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
#define pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
#define pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
#define pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
#define pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
/* Timer Group of 3 */
#define pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
#define pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
#define pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
/* SPORT0 Registers */
#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
/* EPPI0 Registers */
#define pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
#define pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
#define pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
#define pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
#define pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
#define pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
#define pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
#define pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
#define pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
#define pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
#define pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
#define pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
#define pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
#define pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
/* UART2 Registers */
#define pUART2_DLL ((volatile unsigned short *)UART2_DLL)
#define pUART2_DLH ((volatile unsigned short *)UART2_DLH)
#define pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
#define pUART2_LCR ((volatile unsigned short *)UART2_LCR)
#define pUART2_MCR ((volatile unsigned short *)UART2_MCR)
#define pUART2_LSR ((volatile unsigned short *)UART2_LSR)
#define pUART2_MSR ((volatile unsigned short *)UART2_MSR)
#define pUART2_SCR ((volatile unsigned short *)UART2_SCR)
#define pUART2_IER_SET ((volatile unsigned short *)UART2_IER_SET)
#define pUART2_IER_CLEAR ((volatile unsigned short *)UART2_IER_CLEAR)
#define pUART2_THR ((volatile unsigned short *)UART2_THR)
#define pUART2_RBR ((volatile unsigned short *)UART2_RBR)
/* Two Wire Interface Registers (TWI1) */
#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
#define pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
#define pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
#define pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
/* SPI2 Registers */
#define pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
#define pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
#define pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
#define pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
#define pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
#define pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
#define pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
/* CAN Controller 1 Config 1 Registers */
#define pCAN1_MC1 ((volatile unsigned short *)CAN1_MC1)
#define pCAN1_MD1 ((volatile unsigned short *)CAN1_MD1)
#define pCAN1_TRS1 ((volatile unsigned short *)CAN1_TRS1)
#define pCAN1_TRR1 ((volatile unsigned short *)CAN1_TRR1)
#define pCAN1_TA1 ((volatile unsigned short *)CAN1_TA1)
#define pCAN1_AA1 ((volatile unsigned short *)CAN1_AA1)
#define pCAN1_RMP1 ((volatile unsigned short *)CAN1_RMP1)
#define pCAN1_RML1 ((volatile unsigned short *)CAN1_RML1)
#define pCAN1_MBTIF1 ((volatile unsigned short *)CAN1_MBTIF1)
#define pCAN1_MBRIF1 ((volatile unsigned short *)CAN1_MBRIF1)
#define pCAN1_MBIM1 ((volatile unsigned short *)CAN1_MBIM1)
#define pCAN1_RFH1 ((volatile unsigned short *)CAN1_RFH1)
#define pCAN1_OPSS1 ((volatile unsigned short *)CAN1_OPSS1)
/* CAN Controller 1 Config 2 Registers */
#define pCAN1_MC2 ((volatile unsigned short *)CAN1_MC2)
#define pCAN1_MD2 ((volatile unsigned short *)CAN1_MD2)
#define pCAN1_TRS2 ((volatile unsigned short *)CAN1_TRS2)
#define pCAN1_TRR2 ((volatile unsigned short *)CAN1_TRR2)
#define pCAN1_TA2 ((volatile unsigned short *)CAN1_TA2)
#define pCAN1_AA2 ((volatile unsigned short *)CAN1_AA2)
#define pCAN1_RMP2 ((volatile unsigned short *)CAN1_RMP2)
#define pCAN1_RML2 ((volatile unsigned short *)CAN1_RML2)
#define pCAN1_MBTIF2 ((volatile unsigned short *)CAN1_MBTIF2)
#define pCAN1_MBRIF2 ((volatile unsigned short *)CAN1_MBRIF2)
#define pCAN1_MBIM2 ((volatile unsigned short *)CAN1_MBIM2)
#define pCAN1_RFH2 ((volatile unsigned short *)CAN1_RFH2)
#define pCAN1_OPSS2 ((volatile unsigned short *)CAN1_OPSS2)
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
#define pCAN1_CLOCK ((volatile unsigned short *)CAN1_CLOCK)
#define pCAN1_TIMING ((volatile unsigned short *)CAN1_TIMING)
#define pCAN1_DEBUG ((volatile unsigned short *)CAN1_DEBUG)
#define pCAN1_STATUS ((volatile unsigned short *)CAN1_STATUS)
#define pCAN1_CEC ((volatile unsigned short *)CAN1_CEC)
#define pCAN1_GIS ((volatile unsigned short *)CAN1_GIS)
#define pCAN1_GIM ((volatile unsigned short *)CAN1_GIM)
#define pCAN1_GIF ((volatile unsigned short *)CAN1_GIF)
#define pCAN1_CONTROL ((volatile unsigned short *)CAN1_CONTROL)
#define pCAN1_INTR ((volatile unsigned short *)CAN1_INTR)
#define pCAN1_MBTD ((volatile unsigned short *)CAN1_MBTD)
#define pCAN1_EWR ((volatile unsigned short *)CAN1_EWR)
#define pCAN1_ESR ((volatile unsigned short *)CAN1_ESR)
#define pCAN1_UCCNT ((volatile unsigned short *)CAN1_UCCNT)
#define pCAN1_UCRC ((volatile unsigned short *)CAN1_UCRC)
#define pCAN1_UCCNF ((volatile unsigned short *)CAN1_UCCNF)
/* CAN Controller 1 Mailbox Acceptance Registers */
#define pCAN1_AM00L ((volatile unsigned short *)CAN1_AM00L)
#define pCAN1_AM00H ((volatile unsigned short *)CAN1_AM00H)
#define pCAN1_AM01L ((volatile unsigned short *)CAN1_AM01L)
#define pCAN1_AM01H ((volatile unsigned short *)CAN1_AM01H)
#define pCAN1_AM02L ((volatile unsigned short *)CAN1_AM02L)
#define pCAN1_AM02H ((volatile unsigned short *)CAN1_AM02H)
#define pCAN1_AM03L ((volatile unsigned short *)CAN1_AM03L)
#define pCAN1_AM03H ((volatile unsigned short *)CAN1_AM03H)
#define pCAN1_AM04L ((volatile unsigned short *)CAN1_AM04L)
#define pCAN1_AM04H ((volatile unsigned short *)CAN1_AM04H)
#define pCAN1_AM05L ((volatile unsigned short *)CAN1_AM05L)
#define pCAN1_AM05H ((volatile unsigned short *)CAN1_AM05H)
#define pCAN1_AM06L ((volatile unsigned short *)CAN1_AM06L)
#define pCAN1_AM06H ((volatile unsigned short *)CAN1_AM06H)
#define pCAN1_AM07L ((volatile unsigned short *)CAN1_AM07L)
#define pCAN1_AM07H ((volatile unsigned short *)CAN1_AM07H)
#define pCAN1_AM08L ((volatile unsigned short *)CAN1_AM08L)
#define pCAN1_AM08H ((volatile unsigned short *)CAN1_AM08H)
#define pCAN1_AM09L ((volatile unsigned short *)CAN1_AM09L)
#define pCAN1_AM09H ((volatile unsigned short *)CAN1_AM09H)
#define pCAN1_AM10L ((volatile unsigned short *)CAN1_AM10L)
#define pCAN1_AM10H ((volatile unsigned short *)CAN1_AM10H)
#define pCAN1_AM11L ((volatile unsigned short *)CAN1_AM11L)
#define pCAN1_AM11H ((volatile unsigned short *)CAN1_AM11H)
#define pCAN1_AM12L ((volatile unsigned short *)CAN1_AM12L)
#define pCAN1_AM12H ((volatile unsigned short *)CAN1_AM12H)
#define pCAN1_AM13L ((volatile unsigned short *)CAN1_AM13L)
#define pCAN1_AM13H ((volatile unsigned short *)CAN1_AM13H)
#define pCAN1_AM14L ((volatile unsigned short *)CAN1_AM14L)
#define pCAN1_AM14H ((volatile unsigned short *)CAN1_AM14H)
#define pCAN1_AM15L ((volatile unsigned short *)CAN1_AM15L)
#define pCAN1_AM15H ((volatile unsigned short *)CAN1_AM15H)
/* CAN Controller 1 Mailbox Acceptance Registers */
#define pCAN1_AM16L ((volatile unsigned short *)CAN1_AM16L)
#define pCAN1_AM16H ((volatile unsigned short *)CAN1_AM16H)
#define pCAN1_AM17L ((volatile unsigned short *)CAN1_AM17L)
#define pCAN1_AM17H ((volatile unsigned short *)CAN1_AM17H)
#define pCAN1_AM18L ((volatile unsigned short *)CAN1_AM18L)
#define pCAN1_AM18H ((volatile unsigned short *)CAN1_AM18H)
#define pCAN1_AM19L ((volatile unsigned short *)CAN1_AM19L)
#define pCAN1_AM19H ((volatile unsigned short *)CAN1_AM19H)
#define pCAN1_AM20L ((volatile unsigned short *)CAN1_AM20L)
#define pCAN1_AM20H ((volatile unsigned short *)CAN1_AM20H)
#define pCAN1_AM21L ((volatile unsigned short *)CAN1_AM21L)
#define pCAN1_AM21H ((volatile unsigned short *)CAN1_AM21H)
#define pCAN1_AM22L ((volatile unsigned short *)CAN1_AM22L)
#define pCAN1_AM22H ((volatile unsigned short *)CAN1_AM22H)
#define pCAN1_AM23L ((volatile unsigned short *)CAN1_AM23L)
#define pCAN1_AM23H ((volatile unsigned short *)CAN1_AM23H)
#define pCAN1_AM24L ((volatile unsigned short *)CAN1_AM24L)
#define pCAN1_AM24H ((volatile unsigned short *)CAN1_AM24H)
#define pCAN1_AM25L ((volatile unsigned short *)CAN1_AM25L)
#define pCAN1_AM25H ((volatile unsigned short *)CAN1_AM25H)
#define pCAN1_AM26L ((volatile unsigned short *)CAN1_AM26L)
#define pCAN1_AM26H ((volatile unsigned short *)CAN1_AM26H)
#define pCAN1_AM27L ((volatile unsigned short *)CAN1_AM27L)
#define pCAN1_AM27H ((volatile unsigned short *)CAN1_AM27H)
#define pCAN1_AM28L ((volatile unsigned short *)CAN1_AM28L)
#define pCAN1_AM28H ((volatile unsigned short *)CAN1_AM28H)
#define pCAN1_AM29L ((volatile unsigned short *)CAN1_AM29L)
#define pCAN1_AM29H ((volatile unsigned short *)CAN1_AM29H)
#define pCAN1_AM30L ((volatile unsigned short *)CAN1_AM30L)
#define pCAN1_AM30H ((volatile unsigned short *)CAN1_AM30H)
#define pCAN1_AM31L ((volatile unsigned short *)CAN1_AM31L)
#define pCAN1_AM31H ((volatile unsigned short *)CAN1_AM31H)
/* CAN Controller 1 Mailbox Data Registers */
#define pCAN1_MB00_DATA0 ((volatile unsigned short *)CAN1_MB00_DATA0)
#define pCAN1_MB00_DATA1 ((volatile unsigned short *)CAN1_MB00_DATA1)
#define pCAN1_MB00_DATA2 ((volatile unsigned short *)CAN1_MB00_DATA2)
#define pCAN1_MB00_DATA3 ((volatile unsigned short *)CAN1_MB00_DATA3)
#define pCAN1_MB00_LENGTH ((volatile unsigned short *)CAN1_MB00_LENGTH)
#define pCAN1_MB00_TIMESTAMP ((volatile unsigned short *)CAN1_MB00_TIMESTAMP)
#define pCAN1_MB00_ID0 ((volatile unsigned short *)CAN1_MB00_ID0)
#define pCAN1_MB00_ID1 ((volatile unsigned short *)CAN1_MB00_ID1)
#define pCAN1_MB01_DATA0 ((volatile unsigned short *)CAN1_MB01_DATA0)
#define pCAN1_MB01_DATA1 ((volatile unsigned short *)CAN1_MB01_DATA1)
#define pCAN1_MB01_DATA2 ((volatile unsigned short *)CAN1_MB01_DATA2)
#define pCAN1_MB01_DATA3 ((volatile unsigned short *)CAN1_MB01_DATA3)
#define pCAN1_MB01_LENGTH ((volatile unsigned short *)CAN1_MB01_LENGTH)
#define pCAN1_MB01_TIMESTAMP ((volatile unsigned short *)CAN1_MB01_TIMESTAMP)
#define pCAN1_MB01_ID0 ((volatile unsigned short *)CAN1_MB01_ID0)
#define pCAN1_MB01_ID1 ((volatile unsigned short *)CAN1_MB01_ID1)
#define pCAN1_MB02_DATA0 ((volatile unsigned short *)CAN1_MB02_DATA0)
#define pCAN1_MB02_DATA1 ((volatile unsigned short *)CAN1_MB02_DATA1)
#define pCAN1_MB02_DATA2 ((volatile unsigned short *)CAN1_MB02_DATA2)
#define pCAN1_MB02_DATA3 ((volatile unsigned short *)CAN1_MB02_DATA3)
#define pCAN1_MB02_LENGTH ((volatile unsigned short *)CAN1_MB02_LENGTH)
#define pCAN1_MB02_TIMESTAMP ((volatile unsigned short *)CAN1_MB02_TIMESTAMP)
#define pCAN1_MB02_ID0 ((volatile unsigned short *)CAN1_MB02_ID0)
#define pCAN1_MB02_ID1 ((volatile unsigned short *)CAN1_MB02_ID1)
#define pCAN1_MB03_DATA0 ((volatile unsigned short *)CAN1_MB03_DATA0)
#define pCAN1_MB03_DATA1 ((volatile unsigned short *)CAN1_MB03_DATA1)
#define pCAN1_MB03_DATA2 ((volatile unsigned short *)CAN1_MB03_DATA2)
#define pCAN1_MB03_DATA3 ((volatile unsigned short *)CAN1_MB03_DATA3)
#define pCAN1_MB03_LENGTH ((volatile unsigned short *)CAN1_MB03_LENGTH)
#define pCAN1_MB03_TIMESTAMP ((volatile unsigned short *)CAN1_MB03_TIMESTAMP)
#define pCAN1_MB03_ID0 ((volatile unsigned short *)CAN1_MB03_ID0)
#define pCAN1_MB03_ID1 ((volatile unsigned short *)CAN1_MB03_ID1)
#define pCAN1_MB04_DATA0 ((volatile unsigned short *)CAN1_MB04_DATA0)
#define pCAN1_MB04_DATA1 ((volatile unsigned short *)CAN1_MB04_DATA1)
#define pCAN1_MB04_DATA2 ((volatile unsigned short *)CAN1_MB04_DATA2)
#define pCAN1_MB04_DATA3 ((volatile unsigned short *)CAN1_MB04_DATA3)
#define pCAN1_MB04_LENGTH ((volatile unsigned short *)CAN1_MB04_LENGTH)
#define pCAN1_MB04_TIMESTAMP ((volatile unsigned short *)CAN1_MB04_TIMESTAMP)
#define pCAN1_MB04_ID0 ((volatile unsigned short *)CAN1_MB04_ID0)
#define pCAN1_MB04_ID1 ((volatile unsigned short *)CAN1_MB04_ID1)
#define pCAN1_MB05_DATA0 ((volatile unsigned short *)CAN1_MB05_DATA0)
#define pCAN1_MB05_DATA1 ((volatile unsigned short *)CAN1_MB05_DATA1)
#define pCAN1_MB05_DATA2 ((volatile unsigned short *)CAN1_MB05_DATA2)
#define pCAN1_MB05_DATA3 ((volatile unsigned short *)CAN1_MB05_DATA3)
#define pCAN1_MB05_LENGTH ((volatile unsigned short *)CAN1_MB05_LENGTH)
#define pCAN1_MB05_TIMESTAMP ((volatile unsigned short *)CAN1_MB05_TIMESTAMP)
#define pCAN1_MB05_ID0 ((volatile unsigned short *)CAN1_MB05_ID0)
#define pCAN1_MB05_ID1 ((volatile unsigned short *)CAN1_MB05_ID1)
#define pCAN1_MB06_DATA0 ((volatile unsigned short *)CAN1_MB06_DATA0)
#define pCAN1_MB06_DATA1 ((volatile unsigned short *)CAN1_MB06_DATA1)
#define pCAN1_MB06_DATA2 ((volatile unsigned short *)CAN1_MB06_DATA2)
#define pCAN1_MB06_DATA3 ((volatile unsigned short *)CAN1_MB06_DATA3)
#define pCAN1_MB06_LENGTH ((volatile unsigned short *)CAN1_MB06_LENGTH)
#define pCAN1_MB06_TIMESTAMP ((volatile unsigned short *)CAN1_MB06_TIMESTAMP)
#define pCAN1_MB06_ID0 ((volatile unsigned short *)CAN1_MB06_ID0)
#define pCAN1_MB06_ID1 ((volatile unsigned short *)CAN1_MB06_ID1)
#define pCAN1_MB07_DATA0 ((volatile unsigned short *)CAN1_MB07_DATA0)
#define pCAN1_MB07_DATA1 ((volatile unsigned short *)CAN1_MB07_DATA1)
#define pCAN1_MB07_DATA2 ((volatile unsigned short *)CAN1_MB07_DATA2)
#define pCAN1_MB07_DATA3 ((volatile unsigned short *)CAN1_MB07_DATA3)
#define pCAN1_MB07_LENGTH ((volatile unsigned short *)CAN1_MB07_LENGTH)
#define pCAN1_MB07_TIMESTAMP ((volatile unsigned short *)CAN1_MB07_TIMESTAMP)
#define pCAN1_MB07_ID0 ((volatile unsigned short *)CAN1_MB07_ID0)
#define pCAN1_MB07_ID1 ((volatile unsigned short *)CAN1_MB07_ID1)
#define pCAN1_MB08_DATA0 ((volatile unsigned short *)CAN1_MB08_DATA0)
#define pCAN1_MB08_DATA1 ((volatile unsigned short *)CAN1_MB08_DATA1)
#define pCAN1_MB08_DATA2 ((volatile unsigned short *)CAN1_MB08_DATA2)
#define pCAN1_MB08_DATA3 ((volatile unsigned short *)CAN1_MB08_DATA3)
#define pCAN1_MB08_LENGTH ((volatile unsigned short *)CAN1_MB08_LENGTH)
#define pCAN1_MB08_TIMESTAMP ((volatile unsigned short *)CAN1_MB08_TIMESTAMP)
#define pCAN1_MB08_ID0 ((volatile unsigned short *)CAN1_MB08_ID0)
#define pCAN1_MB08_ID1 ((volatile unsigned short *)CAN1_MB08_ID1)
#define pCAN1_MB09_DATA0 ((volatile unsigned short *)CAN1_MB09_DATA0)
#define pCAN1_MB09_DATA1 ((volatile unsigned short *)CAN1_MB09_DATA1)
#define pCAN1_MB09_DATA2 ((volatile unsigned short *)CAN1_MB09_DATA2)
#define pCAN1_MB09_DATA3 ((volatile unsigned short *)CAN1_MB09_DATA3)
#define pCAN1_MB09_LENGTH ((volatile unsigned short *)CAN1_MB09_LENGTH)
#define pCAN1_MB09_TIMESTAMP ((volatile unsigned short *)CAN1_MB09_TIMESTAMP)
#define pCAN1_MB09_ID0 ((volatile unsigned short *)CAN1_MB09_ID0)
#define pCAN1_MB09_ID1 ((volatile unsigned short *)CAN1_MB09_ID1)
#define pCAN1_MB10_DATA0 ((volatile unsigned short *)CAN1_MB10_DATA0)
#define pCAN1_MB10_DATA1 ((volatile unsigned short *)CAN1_MB10_DATA1)
#define pCAN1_MB10_DATA2 ((volatile unsigned short *)CAN1_MB10_DATA2)
#define pCAN1_MB10_DATA3 ((volatile unsigned short *)CAN1_MB10_DATA3)
#define pCAN1_MB10_LENGTH ((volatile unsigned short *)CAN1_MB10_LENGTH)
#define pCAN1_MB10_TIMESTAMP ((volatile unsigned short *)CAN1_MB10_TIMESTAMP)
#define pCAN1_MB10_ID0 ((volatile unsigned short *)CAN1_MB10_ID0)
#define pCAN1_MB10_ID1 ((volatile unsigned short *)CAN1_MB10_ID1)
#define pCAN1_MB11_DATA0 ((volatile unsigned short *)CAN1_MB11_DATA0)
#define pCAN1_MB11_DATA1 ((volatile unsigned short *)CAN1_MB11_DATA1)
#define pCAN1_MB11_DATA2 ((volatile unsigned short *)CAN1_MB11_DATA2)
#define pCAN1_MB11_DATA3 ((volatile unsigned short *)CAN1_MB11_DATA3)
#define pCAN1_MB11_LENGTH ((volatile unsigned short *)CAN1_MB11_LENGTH)
#define pCAN1_MB11_TIMESTAMP ((volatile unsigned short *)CAN1_MB11_TIMESTAMP)
#define pCAN1_MB11_ID0 ((volatile unsigned short *)CAN1_MB11_ID0)
#define pCAN1_MB11_ID1 ((volatile unsigned short *)CAN1_MB11_ID1)
#define pCAN1_MB12_DATA0 ((volatile unsigned short *)CAN1_MB12_DATA0)
#define pCAN1_MB12_DATA1 ((volatile unsigned short *)CAN1_MB12_DATA1)
#define pCAN1_MB12_DATA2 ((volatile unsigned short *)CAN1_MB12_DATA2)
#define pCAN1_MB12_DATA3 ((volatile unsigned short *)CAN1_MB12_DATA3)
#define pCAN1_MB12_LENGTH ((volatile unsigned short *)CAN1_MB12_LENGTH)
#define pCAN1_MB12_TIMESTAMP ((volatile unsigned short *)CAN1_MB12_TIMESTAMP)
#define pCAN1_MB12_ID0 ((volatile unsigned short *)CAN1_MB12_ID0)
#define pCAN1_MB12_ID1 ((volatile unsigned short *)CAN1_MB12_ID1)
#define pCAN1_MB13_DATA0 ((volatile unsigned short *)CAN1_MB13_DATA0)
#define pCAN1_MB13_DATA1 ((volatile unsigned short *)CAN1_MB13_DATA1)
#define pCAN1_MB13_DATA2 ((volatile unsigned short *)CAN1_MB13_DATA2)
#define pCAN1_MB13_DATA3 ((volatile unsigned short *)CAN1_MB13_DATA3)
#define pCAN1_MB13_LENGTH ((volatile unsigned short *)CAN1_MB13_LENGTH)
#define pCAN1_MB13_TIMESTAMP ((volatile unsigned short *)CAN1_MB13_TIMESTAMP)
#define pCAN1_MB13_ID0 ((volatile unsigned short *)CAN1_MB13_ID0)
#define pCAN1_MB13_ID1 ((volatile unsigned short *)CAN1_MB13_ID1)
#define pCAN1_MB14_DATA0 ((volatile unsigned short *)CAN1_MB14_DATA0)
#define pCAN1_MB14_DATA1 ((volatile unsigned short *)CAN1_MB14_DATA1)
#define pCAN1_MB14_DATA2 ((volatile unsigned short *)CAN1_MB14_DATA2)
#define pCAN1_MB14_DATA3 ((volatile unsigned short *)CAN1_MB14_DATA3)
#define pCAN1_MB14_LENGTH ((volatile unsigned short *)CAN1_MB14_LENGTH)
#define pCAN1_MB14_TIMESTAMP ((volatile unsigned short *)CAN1_MB14_TIMESTAMP)
#define pCAN1_MB14_ID0 ((volatile unsigned short *)CAN1_MB14_ID0)
#define pCAN1_MB14_ID1 ((volatile unsigned short *)CAN1_MB14_ID1)
#define pCAN1_MB15_DATA0 ((volatile unsigned short *)CAN1_MB15_DATA0)
#define pCAN1_MB15_DATA1 ((volatile unsigned short *)CAN1_MB15_DATA1)
#define pCAN1_MB15_DATA2 ((volatile unsigned short *)CAN1_MB15_DATA2)
#define pCAN1_MB15_DATA3 ((volatile unsigned short *)CAN1_MB15_DATA3)
#define pCAN1_MB15_LENGTH ((volatile unsigned short *)CAN1_MB15_LENGTH)
#define pCAN1_MB15_TIMESTAMP ((volatile unsigned short *)CAN1_MB15_TIMESTAMP)
#define pCAN1_MB15_ID0 ((volatile unsigned short *)CAN1_MB15_ID0)
#define pCAN1_MB15_ID1 ((volatile unsigned short *)CAN1_MB15_ID1)
/* CAN Controller 1 Mailbox Data Registers */
#define pCAN1_MB16_DATA0 ((volatile unsigned short *)CAN1_MB16_DATA0)
#define pCAN1_MB16_DATA1 ((volatile unsigned short *)CAN1_MB16_DATA1)
#define pCAN1_MB16_DATA2 ((volatile unsigned short *)CAN1_MB16_DATA2)
#define pCAN1_MB16_DATA3 ((volatile unsigned short *)CAN1_MB16_DATA3)
#define pCAN1_MB16_LENGTH ((volatile unsigned short *)CAN1_MB16_LENGTH)
#define pCAN1_MB16_TIMESTAMP ((volatile unsigned short *)CAN1_MB16_TIMESTAMP)
#define pCAN1_MB16_ID0 ((volatile unsigned short *)CAN1_MB16_ID0)
#define pCAN1_MB16_ID1 ((volatile unsigned short *)CAN1_MB16_ID1)
#define pCAN1_MB17_DATA0 ((volatile unsigned short *)CAN1_MB17_DATA0)
#define pCAN1_MB17_DATA1 ((volatile unsigned short *)CAN1_MB17_DATA1)
#define pCAN1_MB17_DATA2 ((volatile unsigned short *)CAN1_MB17_DATA2)
#define pCAN1_MB17_DATA3 ((volatile unsigned short *)CAN1_MB17_DATA3)
#define pCAN1_MB17_LENGTH ((volatile unsigned short *)CAN1_MB17_LENGTH)
#define pCAN1_MB17_TIMESTAMP ((volatile unsigned short *)CAN1_MB17_TIMESTAMP)
#define pCAN1_MB17_ID0 ((volatile unsigned short *)CAN1_MB17_ID0)
#define pCAN1_MB17_ID1 ((volatile unsigned short *)CAN1_MB17_ID1)
#define pCAN1_MB18_DATA0 ((volatile unsigned short *)CAN1_MB18_DATA0)
#define pCAN1_MB18_DATA1 ((volatile unsigned short *)CAN1_MB18_DATA1)
#define pCAN1_MB18_DATA2 ((volatile unsigned short *)CAN1_MB18_DATA2)
#define pCAN1_MB18_DATA3 ((volatile unsigned short *)CAN1_MB18_DATA3)
#define pCAN1_MB18_LENGTH ((volatile unsigned short *)CAN1_MB18_LENGTH)
#define pCAN1_MB18_TIMESTAMP ((volatile unsigned short *)CAN1_MB18_TIMESTAMP)
#define pCAN1_MB18_ID0 ((volatile unsigned short *)CAN1_MB18_ID0)
#define pCAN1_MB18_ID1 ((volatile unsigned short *)CAN1_MB18_ID1)
#define pCAN1_MB19_DATA0 ((volatile unsigned short *)CAN1_MB19_DATA0)
#define pCAN1_MB19_DATA1 ((volatile unsigned short *)CAN1_MB19_DATA1)
#define pCAN1_MB19_DATA2 ((volatile unsigned short *)CAN1_MB19_DATA2)
#define pCAN1_MB19_DATA3 ((volatile unsigned short *)CAN1_MB19_DATA3)
#define pCAN1_MB19_LENGTH ((volatile unsigned short *)CAN1_MB19_LENGTH)
#define pCAN1_MB19_TIMESTAMP ((volatile unsigned short *)CAN1_MB19_TIMESTAMP)
#define pCAN1_MB19_ID0 ((volatile unsigned short *)CAN1_MB19_ID0)
#define pCAN1_MB19_ID1 ((volatile unsigned short *)CAN1_MB19_ID1)
#define pCAN1_MB20_DATA0 ((volatile unsigned short *)CAN1_MB20_DATA0)
#define pCAN1_MB20_DATA1 ((volatile unsigned short *)CAN1_MB20_DATA1)
#define pCAN1_MB20_DATA2 ((volatile unsigned short *)CAN1_MB20_DATA2)
#define pCAN1_MB20_DATA3 ((volatile unsigned short *)CAN1_MB20_DATA3)
#define pCAN1_MB20_LENGTH ((volatile unsigned short *)CAN1_MB20_LENGTH)
#define pCAN1_MB20_TIMESTAMP ((volatile unsigned short *)CAN1_MB20_TIMESTAMP)
#define pCAN1_MB20_ID0 ((volatile unsigned short *)CAN1_MB20_ID0)
#define pCAN1_MB20_ID1 ((volatile unsigned short *)CAN1_MB20_ID1)
#define pCAN1_MB21_DATA0 ((volatile unsigned short *)CAN1_MB21_DATA0)
#define pCAN1_MB21_DATA1 ((volatile unsigned short *)CAN1_MB21_DATA1)
#define pCAN1_MB21_DATA2 ((volatile unsigned short *)CAN1_MB21_DATA2)
#define pCAN1_MB21_DATA3 ((volatile unsigned short *)CAN1_MB21_DATA3)
#define pCAN1_MB21_LENGTH ((volatile unsigned short *)CAN1_MB21_LENGTH)
#define pCAN1_MB21_TIMESTAMP ((volatile unsigned short *)CAN1_MB21_TIMESTAMP)
#define pCAN1_MB21_ID0 ((volatile unsigned short *)CAN1_MB21_ID0)
#define pCAN1_MB21_ID1 ((volatile unsigned short *)CAN1_MB21_ID1)
#define pCAN1_MB22_DATA0 ((volatile unsigned short *)CAN1_MB22_DATA0)
#define pCAN1_MB22_DATA1 ((volatile unsigned short *)CAN1_MB22_DATA1)
#define pCAN1_MB22_DATA2 ((volatile unsigned short *)CAN1_MB22_DATA2)
#define pCAN1_MB22_DATA3 ((volatile unsigned short *)CAN1_MB22_DATA3)
#define pCAN1_MB22_LENGTH ((volatile unsigned short *)CAN1_MB22_LENGTH)
#define pCAN1_MB22_TIMESTAMP ((volatile unsigned short *)CAN1_MB22_TIMESTAMP)
#define pCAN1_MB22_ID0 ((volatile unsigned short *)CAN1_MB22_ID0)
#define pCAN1_MB22_ID1 ((volatile unsigned short *)CAN1_MB22_ID1)
#define pCAN1_MB23_DATA0 ((volatile unsigned short *)CAN1_MB23_DATA0)
#define pCAN1_MB23_DATA1 ((volatile unsigned short *)CAN1_MB23_DATA1)
#define pCAN1_MB23_DATA2 ((volatile unsigned short *)CAN1_MB23_DATA2)
#define pCAN1_MB23_DATA3 ((volatile unsigned short *)CAN1_MB23_DATA3)
#define pCAN1_MB23_LENGTH ((volatile unsigned short *)CAN1_MB23_LENGTH)
#define pCAN1_MB23_TIMESTAMP ((volatile unsigned short *)CAN1_MB23_TIMESTAMP)
#define pCAN1_MB23_ID0 ((volatile unsigned short *)CAN1_MB23_ID0)
#define pCAN1_MB23_ID1 ((volatile unsigned short *)CAN1_MB23_ID1)
#define pCAN1_MB24_DATA0 ((volatile unsigned short *)CAN1_MB24_DATA0)
#define pCAN1_MB24_DATA1 ((volatile unsigned short *)CAN1_MB24_DATA1)
#define pCAN1_MB24_DATA2 ((volatile unsigned short *)CAN1_MB24_DATA2)
#define pCAN1_MB24_DATA3 ((volatile unsigned short *)CAN1_MB24_DATA3)
#define pCAN1_MB24_LENGTH ((volatile unsigned short *)CAN1_MB24_LENGTH)
#define pCAN1_MB24_TIMESTAMP ((volatile unsigned short *)CAN1_MB24_TIMESTAMP)
#define pCAN1_MB24_ID0 ((volatile unsigned short *)CAN1_MB24_ID0)
#define pCAN1_MB24_ID1 ((volatile unsigned short *)CAN1_MB24_ID1)
#define pCAN1_MB25_DATA0 ((volatile unsigned short *)CAN1_MB25_DATA0)
#define pCAN1_MB25_DATA1 ((volatile unsigned short *)CAN1_MB25_DATA1)
#define pCAN1_MB25_DATA2 ((volatile unsigned short *)CAN1_MB25_DATA2)
#define pCAN1_MB25_DATA3 ((volatile unsigned short *)CAN1_MB25_DATA3)
#define pCAN1_MB25_LENGTH ((volatile unsigned short *)CAN1_MB25_LENGTH)
#define pCAN1_MB25_TIMESTAMP ((volatile unsigned short *)CAN1_MB25_TIMESTAMP)
#define pCAN1_MB25_ID0 ((volatile unsigned short *)CAN1_MB25_ID0)
#define pCAN1_MB25_ID1 ((volatile unsigned short *)CAN1_MB25_ID1)
#define pCAN1_MB26_DATA0 ((volatile unsigned short *)CAN1_MB26_DATA0)
#define pCAN1_MB26_DATA1 ((volatile unsigned short *)CAN1_MB26_DATA1)
#define pCAN1_MB26_DATA2 ((volatile unsigned short *)CAN1_MB26_DATA2)
#define pCAN1_MB26_DATA3 ((volatile unsigned short *)CAN1_MB26_DATA3)
#define pCAN1_MB26_LENGTH ((volatile unsigned short *)CAN1_MB26_LENGTH)
#define pCAN1_MB26_TIMESTAMP ((volatile unsigned short *)CAN1_MB26_TIMESTAMP)
#define pCAN1_MB26_ID0 ((volatile unsigned short *)CAN1_MB26_ID0)
#define pCAN1_MB26_ID1 ((volatile unsigned short *)CAN1_MB26_ID1)
#define pCAN1_MB27_DATA0 ((volatile unsigned short *)CAN1_MB27_DATA0)
#define pCAN1_MB27_DATA1 ((volatile unsigned short *)CAN1_MB27_DATA1)
#define pCAN1_MB27_DATA2 ((volatile unsigned short *)CAN1_MB27_DATA2)
#define pCAN1_MB27_DATA3 ((volatile unsigned short *)CAN1_MB27_DATA3)
#define pCAN1_MB27_LENGTH ((volatile unsigned short *)CAN1_MB27_LENGTH)
#define pCAN1_MB27_TIMESTAMP ((volatile unsigned short *)CAN1_MB27_TIMESTAMP)
#define pCAN1_MB27_ID0 ((volatile unsigned short *)CAN1_MB27_ID0)
#define pCAN1_MB27_ID1 ((volatile unsigned short *)CAN1_MB27_ID1)
#define pCAN1_MB28_DATA0 ((volatile unsigned short *)CAN1_MB28_DATA0)
#define pCAN1_MB28_DATA1 ((volatile unsigned short *)CAN1_MB28_DATA1)
#define pCAN1_MB28_DATA2 ((volatile unsigned short *)CAN1_MB28_DATA2)
#define pCAN1_MB28_DATA3 ((volatile unsigned short *)CAN1_MB28_DATA3)
#define pCAN1_MB28_LENGTH ((volatile unsigned short *)CAN1_MB28_LENGTH)
#define pCAN1_MB28_TIMESTAMP ((volatile unsigned short *)CAN1_MB28_TIMESTAMP)
#define pCAN1_MB28_ID0 ((volatile unsigned short *)CAN1_MB28_ID0)
#define pCAN1_MB28_ID1 ((volatile unsigned short *)CAN1_MB28_ID1)
#define pCAN1_MB29_DATA0 ((volatile unsigned short *)CAN1_MB29_DATA0)
#define pCAN1_MB29_DATA1 ((volatile unsigned short *)CAN1_MB29_DATA1)
#define pCAN1_MB29_DATA2 ((volatile unsigned short *)CAN1_MB29_DATA2)
#define pCAN1_MB29_DATA3 ((volatile unsigned short *)CAN1_MB29_DATA3)
#define pCAN1_MB29_LENGTH ((volatile unsigned short *)CAN1_MB29_LENGTH)
#define pCAN1_MB29_TIMESTAMP ((volatile unsigned short *)CAN1_MB29_TIMESTAMP)
#define pCAN1_MB29_ID0 ((volatile unsigned short *)CAN1_MB29_ID0)
#define pCAN1_MB29_ID1 ((volatile unsigned short *)CAN1_MB29_ID1)
#define pCAN1_MB30_DATA0 ((volatile unsigned short *)CAN1_MB30_DATA0)
#define pCAN1_MB30_DATA1 ((volatile unsigned short *)CAN1_MB30_DATA1)
#define pCAN1_MB30_DATA2 ((volatile unsigned short *)CAN1_MB30_DATA2)
#define pCAN1_MB30_DATA3 ((volatile unsigned short *)CAN1_MB30_DATA3)
#define pCAN1_MB30_LENGTH ((volatile unsigned short *)CAN1_MB30_LENGTH)
#define pCAN1_MB30_TIMESTAMP ((volatile unsigned short *)CAN1_MB30_TIMESTAMP)
#define pCAN1_MB30_ID0 ((volatile unsigned short *)CAN1_MB30_ID0)
#define pCAN1_MB30_ID1 ((volatile unsigned short *)CAN1_MB30_ID1)
#define pCAN1_MB31_DATA0 ((volatile unsigned short *)CAN1_MB31_DATA0)
#define pCAN1_MB31_DATA1 ((volatile unsigned short *)CAN1_MB31_DATA1)
#define pCAN1_MB31_DATA2 ((volatile unsigned short *)CAN1_MB31_DATA2)
#define pCAN1_MB31_DATA3 ((volatile unsigned short *)CAN1_MB31_DATA3)
#define pCAN1_MB31_LENGTH ((volatile unsigned short *)CAN1_MB31_LENGTH)
#define pCAN1_MB31_TIMESTAMP ((volatile unsigned short *)CAN1_MB31_TIMESTAMP)
#define pCAN1_MB31_ID0 ((volatile unsigned short *)CAN1_MB31_ID0)
#define pCAN1_MB31_ID1 ((volatile unsigned short *)CAN1_MB31_ID1)
/* ATAPI Registers */
#define pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
#define pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
#define pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
#define pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
#define pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
#define pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
#define pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
#define pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
#define pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
#define pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
#define pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
#define pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
#define pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
#define pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
#define pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
#define pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
#define pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
#define pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
#define pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
#define pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
#define pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
#define pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
#define pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
#define pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
#define pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
/* SDH Registers */
#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
/* HOST Port Registers */
#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
/* USB Control Registers */
#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
/* USB Packet Control Registers */
#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
/* USB Endpoint FIFO Registers */
#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
/* USB OTG Control Registers */
#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
/* USB Phy Control Registers */
#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
/* (APHY_CNTRL is for ADI usage only) */
#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
/* (APHY_CALIB is for ADI usage only) */
#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
/* (PHY_TEST is for ADI usage only) */
#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
/* USB Endpoint 0 Control Registers */
#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
/* USB Endpoint 1 Control Registers */
#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
/* USB Endpoint 2 Control Registers */
#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
/* USB Endpoint 3 Control Registers */
#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
/* USB Endpoint 4 Control Registers */
#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
/* USB Endpoint 5 Control Registers */
#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
/* USB Endpoint 6 Control Registers */
#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
/* USB Endpoint 7 Control Registers */
#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
/* USB Channel 0 Config Registers */
#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
/* USB Channel 1 Config Registers */
#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
/* USB Channel 2 Config Registers */
#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
/* USB Channel 3 Config Registers */
#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
/* USB Channel 4 Config Registers */
#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
/* USB Channel 5 Config Registers */
#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
/* USB Channel 6 Config Registers */
#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
/* USB Channel 7 Config Registers */
#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
/* Keypad Registers */
#define pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
#define pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
#define pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
#define pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
#define pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
#define pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
/* Pixel Compositor (PIXC) Registers */
#define pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
#define pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
#define pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
#define pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
#define pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
#define pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
#define pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
#define pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
#define pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
#define pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
#define pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
#define pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
#define pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
#define pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
#define pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
#define pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
#define pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
#endif /* _CDEF_BF548_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cdefBF561.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
#ifndef _CDEF_BF561_H
#define _CDEF_BF561_H
#if !defined(__ADSPBF561__)
#warning cdefBF561.h should only be included for BF561 chip.
#endif
/* include all Core registers and bit definitions */
#include <defBF561.h>
#include <cdef_LPBlackfin.h>
/*********************************************************************************** */
/* System MMR Register Map */
/*********************************************************************************** */
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#else
#define _PTR_TO_VOL_VOID_PTR (volatile void **)
#endif
#endif
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define pPLL_CTL (volatile unsigned short *)PLL_CTL
#define pPLL_DIV (volatile unsigned short *)PLL_DIV
#define pVR_CTL (volatile unsigned short *)VR_CTL
#define pPLL_STAT (volatile unsigned short *)PLL_STAT
#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT
#define pCHIPID ((volatile unsigned long*)CHIPID)
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST
#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR
#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT
#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK
#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0
#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1
#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0
#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1
#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2
#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3
#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4
#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5
#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6
#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7
#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0
#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1
#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0
#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1
/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST
#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR
#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT
#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0
#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1
#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0
#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1
#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2
#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3
#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4
#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5
#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6
#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7
#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0
#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1
#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0
#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1
/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL
#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT
#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT
/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL
#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT
#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
#define pUART_THR (volatile unsigned short *)UART_THR
#define pUART_RBR (volatile unsigned short *)UART_RBR
#define pUART_DLL (volatile unsigned short *)UART_DLL
#define pUART_IER (volatile unsigned short *)UART_IER
#define pUART_DLH (volatile unsigned short *)UART_DLH
#define pUART_IIR (volatile unsigned short *)UART_IIR
#define pUART_LCR (volatile unsigned short *)UART_LCR
#define pUART_MCR (volatile unsigned short *)UART_MCR
#define pUART_LSR (volatile unsigned short *)UART_LSR
#define pUART_MSR (volatile unsigned short *)UART_MSR
#define pUART_SCR (volatile unsigned short *)UART_SCR
#define pUART_GCTL (volatile unsigned short *)UART_GCTL
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define pSPI_CTL (volatile unsigned short *)SPI_CTL
#define pSPI_FLG (volatile unsigned short *)SPI_FLG
#define pSPI_STAT (volatile unsigned short *)SPI_STAT
#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR
#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR
#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD
#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW
/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG
#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER
#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD
#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH
#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG
#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER
#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD
#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH
#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG
#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER
#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD
#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH
#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG
#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER
#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD
#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH
#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG
#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER
#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD
#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH
#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG
#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER
#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD
#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH
#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG
#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER
#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD
#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH
#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG
#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER
#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD
#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH
/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE
#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE
#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS
#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG
#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER
#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD
#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH
#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG
#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER
#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD
#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH
#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG
#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER
#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD
#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH
#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG
#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER
#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD
#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH
#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE
#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE
#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS
/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D
#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C
#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S
#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T
#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D
#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C
#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S
#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T
#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D
#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C
#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S
#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T
#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR
#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR
#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE
#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH
#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN
/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D
#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C
#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S
#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T
#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D
#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C
#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S
#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T
#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D
#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C
#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S
#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T
#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR
#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR
#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE
#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH
#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN
/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D
#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C
#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S
#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T
#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D
#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C
#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S
#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T
#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D
#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C
#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S
#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T
#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR
#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR
#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE
#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH
#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN
/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1
#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2
#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV
#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV
#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX
#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX
#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1
#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2
#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV
#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV
#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT
#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL
#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1
#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2
#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0
#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1
#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2
#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3
#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0
#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1
#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2
#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3
/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1
#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2
#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV
#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV
#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX
#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX
#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1
#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2
#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV
#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV
#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT
#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL
#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1
#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2
#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0
#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1
#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2
#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3
#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0
#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1
#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2
#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3
/* Asynchronous Memory Controller - External Bus Interface Unit */
#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL
#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0
#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1
/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL
#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL
#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC
#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT
/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL
#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS
#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT
#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY
#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME
/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL
#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS
#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT
#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY
#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME
/*DMA traffic control registers */
#define pDMA1_TC_PER (volatile unsigned short *)DMA1_TC_PER
#define pDMA1_TC_CNT (volatile unsigned short *)DMA1_TC_CNT
#define pDMA2_TC_PER (volatile unsigned short *)DMA2_TC_PER
#define pDMA2_TC_CNT (volatile unsigned short *)DMA2_TC_CNT
/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG
#define pDMA1_0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_0_NEXT_DESC_PTR
#define pDMA1_0_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_0_START_ADDR
#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT
#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT
#define pDMA1_0_X_MODIFY (volatile signed short *)DMA1_0_X_MODIFY
#define pDMA1_0_Y_MODIFY (volatile signed short *)DMA1_0_Y_MODIFY
#define pDMA1_0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_0_CURR_DESC_PTR
#define pDMA1_0_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_0_CURR_ADDR
#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT
#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT
#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS
#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG
#define pDMA1_1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_1_NEXT_DESC_PTR
#define pDMA1_1_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_1_START_ADDR
#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT
#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT
#define pDMA1_1_X_MODIFY (volatile signed short *)DMA1_1_X_MODIFY
#define pDMA1_1_Y_MODIFY (volatile signed short *)DMA1_1_Y_MODIFY
#define pDMA1_1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_1_CURR_DESC_PTR
#define pDMA1_1_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_1_CURR_ADDR
#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT
#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT
#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS
#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP
#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG
#define pDMA1_2_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_2_NEXT_DESC_PTR
#define pDMA1_2_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_2_START_ADDR
#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT
#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT
#define pDMA1_2_X_MODIFY (volatile signed short *)DMA1_2_X_MODIFY
#define pDMA1_2_Y_MODIFY (volatile signed short *)DMA1_2_Y_MODIFY
#define pDMA1_2_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_2_CURR_DESC_PTR
#define pDMA1_2_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_2_CURR_ADDR
#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT
#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT
#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS
#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP
#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG
#define pDMA1_3_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_3_NEXT_DESC_PTR
#define pDMA1_3_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_3_START_ADDR
#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT
#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT
#define pDMA1_3_X_MODIFY (volatile signed short *)DMA1_3_X_MODIFY
#define pDMA1_3_Y_MODIFY (volatile signed short *)DMA1_3_Y_MODIFY
#define pDMA1_3_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_3_CURR_DESC_PTR
#define pDMA1_3_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_3_CURR_ADDR
#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT
#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT
#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS
#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP
#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG
#define pDMA1_4_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_4_NEXT_DESC_PTR
#define pDMA1_4_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_4_START_ADDR
#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT
#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT
#define pDMA1_4_X_MODIFY (volatile signed short *)DMA1_4_X_MODIFY
#define pDMA1_4_Y_MODIFY (volatile signed short *)DMA1_4_Y_MODIFY
#define pDMA1_4_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_4_CURR_DESC_PTR
#define pDMA1_4_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_4_CURR_ADDR
#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT
#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT
#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS
#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP
#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG
#define pDMA1_5_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_5_NEXT_DESC_PTR
#define pDMA1_5_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_5_START_ADDR
#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT
#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT
#define pDMA1_5_X_MODIFY (volatile signed short *)DMA1_5_X_MODIFY
#define pDMA1_5_Y_MODIFY (volatile signed short *)DMA1_5_Y_MODIFY
#define pDMA1_5_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_5_CURR_DESC_PTR
#define pDMA1_5_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_5_CURR_ADDR
#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT
#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT
#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS
#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP
#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG
#define pDMA1_6_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_6_NEXT_DESC_PTR
#define pDMA1_6_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_6_START_ADDR
#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT
#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT
#define pDMA1_6_X_MODIFY (volatile signed short *)DMA1_6_X_MODIFY
#define pDMA1_6_Y_MODIFY (volatile signed short *)DMA1_6_Y_MODIFY
#define pDMA1_6_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_6_CURR_DESC_PTR
#define pDMA1_6_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_6_CURR_ADDR
#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT
#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT
#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS
#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP
#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG
#define pDMA1_7_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_7_NEXT_DESC_PTR
#define pDMA1_7_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_7_START_ADDR
#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT
#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT
#define pDMA1_7_X_MODIFY (volatile signed short *)DMA1_7_X_MODIFY
#define pDMA1_7_Y_MODIFY (volatile signed short *)DMA1_7_Y_MODIFY
#define pDMA1_7_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_7_CURR_DESC_PTR
#define pDMA1_7_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_7_CURR_ADDR
#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT
#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT
#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS
#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP
#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG
#define pDMA1_8_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_8_NEXT_DESC_PTR
#define pDMA1_8_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_8_START_ADDR
#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT
#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT
#define pDMA1_8_X_MODIFY (volatile signed short *)DMA1_8_X_MODIFY
#define pDMA1_8_Y_MODIFY (volatile signed short *)DMA1_8_Y_MODIFY
#define pDMA1_8_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_8_CURR_DESC_PTR
#define pDMA1_8_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_8_CURR_ADDR
#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT
#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT
#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS
#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP
#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG
#define pDMA1_9_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_9_NEXT_DESC_PTR
#define pDMA1_9_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_9_START_ADDR
#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT
#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT
#define pDMA1_9_X_MODIFY (volatile signed short *)DMA1_9_X_MODIFY
#define pDMA1_9_Y_MODIFY (volatile signed short *)DMA1_9_Y_MODIFY
#define pDMA1_9_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_9_CURR_DESC_PTR
#define pDMA1_9_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_9_CURR_ADDR
#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT
#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT
#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS
#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP
#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG
#define pDMA1_10_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_10_NEXT_DESC_PTR
#define pDMA1_10_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_10_START_ADDR
#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT
#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT
#define pDMA1_10_X_MODIFY (volatile signed short *)DMA1_10_X_MODIFY
#define pDMA1_10_Y_MODIFY (volatile signed short *)DMA1_10_Y_MODIFY
#define pDMA1_10_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_10_CURR_DESC_PTR
#define pDMA1_10_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_10_CURR_ADDR
#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT
#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT
#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS
#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP
#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG
#define pDMA1_11_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_11_NEXT_DESC_PTR
#define pDMA1_11_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_11_START_ADDR
#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT
#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT
#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY
#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY
#define pDMA1_11_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_11_CURR_DESC_PTR
#define pDMA1_11_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_11_CURR_ADDR
#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT
#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT
#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS
#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP
/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG
#define pMDMA1_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D0_NEXT_DESC_PTR
#define pMDMA1_D0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D0_START_ADDR
#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT
#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT
#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY
#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY
#define pMDMA1_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_DESC_PTR
#define pMDMA1_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_ADDR
#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS
#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG
#define pMDMA1_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S0_NEXT_DESC_PTR
#define pMDMA1_S0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S0_START_ADDR
#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT
#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT
#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY
#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY
#define pMDMA1_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_DESC_PTR
#define pMDMA1_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_ADDR
#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS
#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG
#define pMDMA1_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D1_NEXT_DESC_PTR
#define pMDMA1_D1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D1_START_ADDR
#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT
#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT
#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY
#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY
#define pMDMA1_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_DESC_PTR
#define pMDMA1_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_ADDR
#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS
#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG
#define pMDMA1_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S1_NEXT_DESC_PTR
#define pMDMA1_S1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S1_START_ADDR
#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT
#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT
#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY
#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY
#define pMDMA1_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_DESC_PTR
#define pMDMA1_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_ADDR
#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS
#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG
#define pDMA2_0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_0_NEXT_DESC_PTR
#define pDMA2_0_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_0_START_ADDR
#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT
#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT
#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY
#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY
#define pDMA2_0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_0_CURR_DESC_PTR
#define pDMA2_0_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_0_CURR_ADDR
#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT
#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT
#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS
#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG
#define pDMA2_1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_1_NEXT_DESC_PTR
#define pDMA2_1_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_1_START_ADDR
#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT
#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT
#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY
#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY
#define pDMA2_1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_1_CURR_DESC_PTR
#define pDMA2_1_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_1_CURR_ADDR
#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT
#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT
#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS
#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG
#define pDMA2_2_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_2_NEXT_DESC_PTR
#define pDMA2_2_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_2_START_ADDR
#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT
#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT
#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY
#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY
#define pDMA2_2_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_2_CURR_DESC_PTR
#define pDMA2_2_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_2_CURR_ADDR
#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT
#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT
#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS
#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG
#define pDMA2_3_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_3_NEXT_DESC_PTR
#define pDMA2_3_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_3_START_ADDR
#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT
#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT
#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY
#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY
#define pDMA2_3_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_3_CURR_DESC_PTR
#define pDMA2_3_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_3_CURR_ADDR
#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT
#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT
#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS
#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG
#define pDMA2_4_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_4_NEXT_DESC_PTR
#define pDMA2_4_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_4_START_ADDR
#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT
#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT
#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY
#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY
#define pDMA2_4_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_4_CURR_DESC_PTR
#define pDMA2_4_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_4_CURR_ADDR
#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT
#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT
#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS
#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG
#define pDMA2_5_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_5_NEXT_DESC_PTR
#define pDMA2_5_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_5_START_ADDR
#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT
#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT
#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY
#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY
#define pDMA2_5_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_5_CURR_DESC_PTR
#define pDMA2_5_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_5_CURR_ADDR
#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT
#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT
#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS
#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG
#define pDMA2_6_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_6_NEXT_DESC_PTR
#define pDMA2_6_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_6_START_ADDR
#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT
#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT
#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY
#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY
#define pDMA2_6_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_6_CURR_DESC_PTR
#define pDMA2_6_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_6_CURR_ADDR
#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT
#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT
#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS
#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG
#define pDMA2_7_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_7_NEXT_DESC_PTR
#define pDMA2_7_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_7_START_ADDR
#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT
#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT
#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY
#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY
#define pDMA2_7_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_7_CURR_DESC_PTR
#define pDMA2_7_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_7_CURR_ADDR
#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT
#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT
#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS
#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP
#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG
#define pDMA2_8_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_8_NEXT_DESC_PTR
#define pDMA2_8_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_8_START_ADDR
#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT
#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT
#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY
#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY
#define pDMA2_8_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_8_CURR_DESC_PTR
#define pDMA2_8_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_8_CURR_ADDR
#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT
#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT
#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS
#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP
#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG
#define pDMA2_9_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_9_NEXT_DESC_PTR
#define pDMA2_9_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_9_START_ADDR
#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT
#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT
#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY
#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY
#define pDMA2_9_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_9_CURR_DESC_PTR
#define pDMA2_9_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_9_CURR_ADDR
#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT
#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT
#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS
#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP
#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG
#define pDMA2_10_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_10_NEXT_DESC_PTR
#define pDMA2_10_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_10_START_ADDR
#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT
#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT
#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY
#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY
#define pDMA2_10_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_10_CURR_DESC_PTR
#define pDMA2_10_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_10_CURR_ADDR
#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT
#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT
#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS
#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP
#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG
#define pDMA2_11_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_11_NEXT_DESC_PTR
#define pDMA2_11_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_11_START_ADDR
#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT
#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT
#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY
#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY
#define pDMA2_11_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_11_CURR_DESC_PTR
#define pDMA2_11_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_11_CURR_ADDR
#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT
#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT
#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS
#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP
/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG
#define pMDMA2_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D0_NEXT_DESC_PTR
#define pMDMA2_D0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D0_START_ADDR
#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT
#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT
#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY
#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY
#define pMDMA2_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_DESC_PTR
#define pMDMA2_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_ADDR
#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT
#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT
#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS
#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP
#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG
#define pMDMA2_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S0_NEXT_DESC_PTR
#define pMDMA2_S0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S0_START_ADDR
#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT
#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT
#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY
#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY
#define pMDMA2_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_DESC_PTR
#define pMDMA2_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_ADDR
#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT
#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT
#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS
#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP
#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG
#define pMDMA2_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D1_NEXT_DESC_PTR
#define pMDMA2_D1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D1_START_ADDR
#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT
#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT
#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY
#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY
#define pMDMA2_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_DESC_PTR
#define pMDMA2_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_ADDR
#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT
#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT
#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS
#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP
#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG
#define pMDMA2_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S1_NEXT_DESC_PTR
#define pMDMA2_S1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S1_START_ADDR
#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT
#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT
#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY
#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY
#define pMDMA2_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_DESC_PTR
#define pMDMA2_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_ADDR
#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT
#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT
#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS
#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP
/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG
#define pIMDMA_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D0_NEXT_DESC_PTR
#define pIMDMA_D0_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D0_START_ADDR
#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT
#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT
#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY
#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY
#define pIMDMA_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_DESC_PTR
#define pIMDMA_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_ADDR
#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT
#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT
#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS
#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG
#define pIMDMA_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S0_NEXT_DESC_PTR
#define pIMDMA_S0_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S0_START_ADDR
#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT
#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT
#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY
#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY
#define pIMDMA_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_DESC_PTR
#define pIMDMA_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_ADDR
#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT
#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT
#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS
#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG
#define pIMDMA_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D1_NEXT_DESC_PTR
#define pIMDMA_D1_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D1_START_ADDR
#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT
#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT
#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY
#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY
#define pIMDMA_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_DESC_PTR
#define pIMDMA_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_ADDR
#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT
#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT
#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS
#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG
#define pIMDMA_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S1_NEXT_DESC_PTR
#define pIMDMA_S1_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S1_START_ADDR
#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT
#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT
#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY
#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY
#define pIMDMA_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_DESC_PTR
#define pIMDMA_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_ADDR
#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT
#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT
#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS
#endif /* _CDEF_BF561_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cdef_LPBlackfin.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _CDEF_LPBLACKFIN_H
#define _CDEF_LPBLACKFIN_H
#if !defined(__ADSPLPBLACKFIN__)
#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
#endif
#include <def_LPBlackfin.h>
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#else
#define _PTR_TO_VOL_VOID_PTR (volatile void **)
#endif
#endif
/* Cache & SRAM Memory */
#define pSRAM_BASE_ADDRESS (_PTR_TO_VOL_VOID_PTR SRAM_BASE_ADDRESS)
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
#define pDCPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR DCPLB_FAULT_ADDR)
#define pDCPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR0)
#define pDCPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR1)
#define pDCPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR2)
#define pDCPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR3)
#define pDCPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR4)
#define pDCPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR5)
#define pDCPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR6)
#define pDCPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR7)
#define pDCPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR8)
#define pDCPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR9)
#define pDCPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR10)
#define pDCPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR11)
#define pDCPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR12)
#define pDCPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR13)
#define pDCPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR14)
#define pDCPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR15)
#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
#define pICPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR ICPLB_FAULT_ADDR)
#define pICPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR0)
#define pICPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR1)
#define pICPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR2)
#define pICPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR3)
#define pICPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR4)
#define pICPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR5)
#define pICPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR6)
#define pICPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR7)
#define pICPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR8)
#define pICPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR9)
#define pICPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR10)
#define pICPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR11)
#define pICPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR12)
#define pICPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR13)
#define pICPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR14)
#define pICPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR15)
#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
/* Event/Interrupt Registers */
#define pEVT0 (_PTR_TO_VOL_VOID_PTR EVT0)
#define pEVT1 (_PTR_TO_VOL_VOID_PTR EVT1)
#define pEVT2 (_PTR_TO_VOL_VOID_PTR EVT2)
#define pEVT3 (_PTR_TO_VOL_VOID_PTR EVT3)
#define pEVT4 (_PTR_TO_VOL_VOID_PTR EVT4)
#define pEVT5 (_PTR_TO_VOL_VOID_PTR EVT5)
#define pEVT6 (_PTR_TO_VOL_VOID_PTR EVT6)
#define pEVT7 (_PTR_TO_VOL_VOID_PTR EVT7)
#define pEVT8 (_PTR_TO_VOL_VOID_PTR EVT8)
#define pEVT9 (_PTR_TO_VOL_VOID_PTR EVT9)
#define pEVT10 (_PTR_TO_VOL_VOID_PTR EVT10)
#define pEVT11 (_PTR_TO_VOL_VOID_PTR EVT11)
#define pEVT12 (_PTR_TO_VOL_VOID_PTR EVT12)
#define pEVT13 (_PTR_TO_VOL_VOID_PTR EVT13)
#define pEVT14 (_PTR_TO_VOL_VOID_PTR EVT14)
#define pEVT15 (_PTR_TO_VOL_VOID_PTR EVT15)
#define pIMASK ((volatile unsigned long *)IMASK)
#define pIPEND ((volatile unsigned long *)IPEND)
#define pILAT ((volatile unsigned long *)ILAT)
/* Core Timer Registers */
#define pTCNTL ((volatile unsigned long *)TCNTL)
#define pTPERIOD ((volatile unsigned long *)TPERIOD)
#define pTSCALE ((volatile unsigned long *)TSCALE)
#define pTCOUNT ((volatile unsigned long *)TCOUNT)
/* Debug/MP/Emulation Registers */
#define pDSPID ((volatile unsigned long *)DSPID)
#define pDBGCTL ((volatile unsigned long *)DBGCTL)
#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
#define pEMUDAT ((volatile unsigned long *)EMUDAT)
/* Trace Buffer Registers */
#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
#define pTBUF (_PTR_TO_VOL_VOID_PTR TBUF)
/* Watch Point Control Registers */
#define pWPIACTL ((volatile unsigned long *)WPIACTL)
#define pWPIA0 (_PTR_TO_VOL_VOID_PTR WPIA0)
#define pWPIA1 (_PTR_TO_VOL_VOID_PTR WPIA1)
#define pWPIA2 (_PTR_TO_VOL_VOID_PTR WPIA2)
#define pWPIA3 (_PTR_TO_VOL_VOID_PTR WPIA3)
#define pWPIA4 (_PTR_TO_VOL_VOID_PTR WPIA4)
#define pWPIA5 (_PTR_TO_VOL_VOID_PTR WPIA5)
#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
#define pWPDACTL ((volatile unsigned long *)WPDACTL)
#define pWPDA0 (_PTR_TO_VOL_VOID_PTR WPDA0)
#define pWPDA1 (_PTR_TO_VOL_VOID_PTR WPDA1)
#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
#define pWPSTAT ((volatile unsigned long *)WPSTAT)
/* Performance Monitor Registers */
#define pPFCTL ((volatile unsigned long *)PFCTL)
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
#endif /* _CDEF_LPBLACKFIN_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cdefblackfin.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _CDEF_BLACKFIN_H
#define _CDEF_BLACKFIN_H
#if defined(__ADSPLPBLACKFIN__)
#warning cdefblackfin.h should only be included for 535 compatible chips.
#endif
#include <defblackfin.h>
#ifndef _PTR_TO_VOL_VOID_PTR
#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
#else
#define _PTR_TO_VOL_VOID_PTR (volatile void **)
#endif
#endif
/* Cache & SRAM Memory */
#define pSRAM_BASE_ADDRESS (_PTR_TO_VOL_VOID_PTR SRAM_BASE_ADDRESS)
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
#define pDCPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR DCPLB_FAULT_ADDR)
#define pDCPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR0)
#define pDCPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR1)
#define pDCPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR2)
#define pDCPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR3)
#define pDCPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR4)
#define pDCPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR5)
#define pDCPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR6)
#define pDCPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR7)
#define pDCPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR8)
#define pDCPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR9)
#define pDCPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR10)
#define pDCPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR11)
#define pDCPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR12)
#define pDCPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR13)
#define pDCPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR14)
#define pDCPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR15)
#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
#define pICPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR ICPLB_FAULT_ADDR)
#define pICPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR0)
#define pICPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR1)
#define pICPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR2)
#define pICPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR3)
#define pICPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR4)
#define pICPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR5)
#define pICPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR6)
#define pICPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR7)
#define pICPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR8)
#define pICPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR9)
#define pICPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR10)
#define pICPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR11)
#define pICPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR12)
#define pICPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR13)
#define pICPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR14)
#define pICPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR15)
#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
/* Event/Interrupt Registers */
#define pEVT0 (_PTR_TO_VOL_VOID_PTR EVT0)
#define pEVT1 (_PTR_TO_VOL_VOID_PTR EVT1)
#define pEVT2 (_PTR_TO_VOL_VOID_PTR EVT2)
#define pEVT3 (_PTR_TO_VOL_VOID_PTR EVT3)
#define pEVT4 (_PTR_TO_VOL_VOID_PTR EVT4)
#define pEVT5 (_PTR_TO_VOL_VOID_PTR EVT5)
#define pEVT6 (_PTR_TO_VOL_VOID_PTR EVT6)
#define pEVT7 (_PTR_TO_VOL_VOID_PTR EVT7)
#define pEVT8 (_PTR_TO_VOL_VOID_PTR EVT8)
#define pEVT9 (_PTR_TO_VOL_VOID_PTR EVT9)
#define pEVT10 (_PTR_TO_VOL_VOID_PTR EVT10)
#define pEVT11 (_PTR_TO_VOL_VOID_PTR EVT11)
#define pEVT12 (_PTR_TO_VOL_VOID_PTR EVT12)
#define pEVT13 (_PTR_TO_VOL_VOID_PTR EVT13)
#define pEVT14 (_PTR_TO_VOL_VOID_PTR EVT14)
#define pEVT15 (_PTR_TO_VOL_VOID_PTR EVT15)
#define pIMASK ((volatile unsigned short *)IMASK)
#define pIPEND ((volatile unsigned short *)IPEND)
#define pILAT ((volatile unsigned short *)ILAT)
/* Core Timer Registers */
#define pTCNTL ((volatile unsigned long *)TCNTL)
#define pTPERIOD ((volatile unsigned long *)TPERIOD)
#define pTSCALE ((volatile unsigned long *)TSCALE)
#define pTCOUNT ((volatile unsigned long *)TCOUNT)
/* Debug/MP/Emulation Registers */
#define pDSPID ((volatile unsigned long *)DSPID)
#define pDBGCTL ((volatile unsigned long *)DBGCTL)
#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
#define pEMUDAT ((volatile unsigned long *)EMUDAT)
/* Trace Buffer Registers */
#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
#define pTBUF (_PTR_TO_VOL_VOID_PTR TBUF)
/* Watch Point Control Registers */
#define pWPIACTL ((volatile unsigned long *)WPIACTL)
#define pWPIA0 (_PTR_TO_VOL_VOID_PTR WPIA0)
#define pWPIA1 (_PTR_TO_VOL_VOID_PTR WPIA1)
#define pWPIA2 (_PTR_TO_VOL_VOID_PTR WPIA2)
#define pWPIA3 (_PTR_TO_VOL_VOID_PTR WPIA3)
#define pWPIA4 (_PTR_TO_VOL_VOID_PTR WPIA4)
#define pWPIA5 (_PTR_TO_VOL_VOID_PTR WPIA5)
#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
#define pWPDACTL ((volatile unsigned long *)WPDACTL)
#define pWPDA0 (_PTR_TO_VOL_VOID_PTR WPDA0)
#define pWPDA1 (_PTR_TO_VOL_VOID_PTR WPDA1)
#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
#define pWPSTAT ((volatile unsigned long *)WPSTAT)
/* Performance Monitor Registers */
#define pPFCTL ((volatile unsigned long *)PFCTL)
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
#endif /* _CDEF_BLACKFIN_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* cplb.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
/* Defines necessary for cplb initialisation routines. */
#ifndef _CPLB_H
#define _CPLB_H
#include <sys/platform.h>
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#endif /* _MISRA_RULES */
#define CPLB_ENABLE_ICACHE_P 0
#define CPLB_ENABLE_DCACHE_P 1
#define CPLB_ENABLE_DCACHE2_P 2
#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
#define CPLB_ENABLE_ICPLBS_P 4
#define CPLB_ENABLE_DCPLBS_P 5
#define CPLB_SET_DCBS_P 6
#define CPLB_INVALIDATE_B_P 23
/* ___cplb_ctrl bitmasks */
#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
#define CPLB_ENABLE_ANY_CPLBS \
( CPLB_ENABLE_CPLBS | CPLB_ENABLE_ICPLBS | CPLB_ENABLE_DCPLBS )
#define CPLB_SET_DCBS (1<<CPLB_SET_DCBS_P)
/* Bitmasks for dcache_invalidate routine parameters */
#define CPLB_INVALIDATE_A 0
#define CPLB_INVALIDATE_B (1<<CPLB_INVALIDATE_B_P)
/* _cplb_mgr return values */
#define CPLB_RELOADED 0x0000
#define CPLB_NO_UNLOCKED 0x0001
#define CPLB_NO_ADDR_MATCH 0x0002
#define CPLB_PROT_VIOL 0x0003
#define CPLB_NO_ACTION 0x0004
/* CPLB configurations */
#define CPLB_DEF_CACHE_WT ( CPLB_L1_CHBL | CPLB_WT )
#define CPLB_DEF_CACHE_WB ( CPLB_L1_CHBL )
#define CPLB_CACHE_ENABLED ( CPLB_L1_CHBL | CPLB_DIRTY )
#define CPLB_DEF_CACHE ( CPLB_L1_CHBL | CPLB_WT )
#define CPLB_ALL_ACCESS ( CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR )
#define CPLB_I_PAGE_MGMT ( CPLB_LOCK | CPLB_VALID )
#define CPLB_D_PAGE_MGMT ( CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID )
#define CPLB_DNOCACHE ( CPLB_ALL_ACCESS | CPLB_VALID )
#define CPLB_DDOCACHE ( CPLB_DNOCACHE | CPLB_DEF_CACHE )
#define CPLB_INOCACHE ( CPLB_USER_RD | CPLB_VALID )
#define CPLB_IDOCACHE ( CPLB_INOCACHE | CPLB_L1_CHBL )
#define CPLB_DDOCACHE_WT ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WT )
#define CPLB_DDOCACHE_WB ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WB )
/* Event type parameter for replacement manager _cplb_mgr */
#define CPLB_EVT_ICPLB_MISS 0
#define CPLB_EVT_DCPLB_MISS 1
#define CPLB_EVT_DCPLB_WRITE 2
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
#endif /* _CPLB_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#pragma once
#ifndef __NO_BUILTIN
#pragma system_header /* cplbtab.h */
#endif
/************************************************************************
*
* cplbtab.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
/* Define structures for the CPLB tables. */
#ifndef _CPLBTAB_H
#define _CPLBTAB_H
#include <cplb.h>
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_6_3)
#pragma diag(suppress:misra_rule_8_12)
#endif /* _MISRA_RULES */
typedef struct {
unsigned long addr;
unsigned long flags;
} cplb_entry;
extern cplb_entry dcplbs_table[];
extern cplb_entry icplbs_table[];
extern int __cplb_ctrl;
#ifdef __cplusplus
extern "C" {
#endif
void cplb_init(int _enable_cpls_caches);
int cplb_mgr(int _is_data_miss, int _enable_cache);
void cplb_hdr(void);
void cache_invalidate(int _caches);
void icache_invalidate(void);
void dcache_invalidate(int _caches);
void dcache_invalidate_both(void);
void flush_data_cache(void);
void flush_data_buffer(void *_start, void *_end, int _invalidate);
void disable_data_cache(void);
void enable_data_cache(int _cplb_ctrl);
#ifdef __cplusplus
}
#endif
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
#endif /* _CPLBTAB_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for register-access and bit-manipulation.
**
**/
#ifndef _DEF_BF522_H
#define _DEF_BF522_H
/* Include all Core registers and bit definitions */
#include <def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include <defBF52x_base.h>
#endif /* _DEF_BF522_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for register-access and bit-manipulation.
**
**/
#ifndef _DEF_BF525_H
#define _DEF_BF525_H
/* Include all Core registers and bit definitions */
#include <def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
#include <defBF52x_base.h>
/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
/* USB Control Registers */
#define USB_FADDR 0xffc03800 /* Function address register */
#define USB_POWER 0xffc03804 /* Power management register */
#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
#define USB_FRAME 0xffc03820 /* USB frame number */
#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
/* USB Packet Control Registers */
#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* USB Endpoint FIFO Registers */
#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
/* USB OTG Control Registers */
#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
/* USB Phy Control Registers */
#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
/* (APHY_CNTRL is for ADI usage only) */
#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
/* (APHY_CALIB is for ADI usage only) */
#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
/* (PHY_TEST is for ADI usage only) */
#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
/* USB Endpoint 0 Control Registers */
#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
/* USB Endpoint 1 Control Registers */
#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
/* USB Endpoint 2 Control Registers */
#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
/* USB Endpoint 3 Control Registers */
#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
/* USB Endpoint 4 Control Registers */
#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
/* USB Endpoint 5 Control Registers */
#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
/* USB Endpoint 6 Control Registers */
#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
/* USB Endpoint 7 Control Registers */
#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
/* USB Channel 0 Config Registers */
#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
/* USB Channel 1 Config Registers */
#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
/* USB Channel 2 Config Registers */
#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
/* USB Channel 3 Config Registers */
#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
/* USB Channel 4 Config Registers */
#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
/* USB Channel 5 Config Registers */
#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
/* USB Channel 6 Config Registers */
#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
/* USB Channel 7 Config Registers */
#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
/* Bit masks for USB_FADDR */
#define FUNCTION_ADDRESS 0x7f /* Function address */
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
#define nENABLE_SUSPENDM 0x0
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
#define nSUSPEND_MODE 0x0
#define RESUME_MODE 0x4 /* DMA Mode */
#define nRESUME_MODE 0x0
#define RESET 0x8 /* Reset indicator */
#define nRESET 0x0
#define HS_MODE 0x10 /* High Speed mode indicator */
#define nHS_MODE 0x0
#define HS_ENABLE 0x20 /* high Speed Enable */
#define nHS_ENABLE 0x0
#define SOFT_CONN 0x40 /* Soft connect */
#define nSOFT_CONN 0x0
#define ISO_UPDATE 0x80 /* Isochronous update */
#define nISO_UPDATE 0x0
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
#define nEP0_TX 0x0
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
#define nEP1_TX 0x0
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
#define nEP2_TX 0x0
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
#define nEP3_TX 0x0
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
#define nEP4_TX 0x0
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
#define nEP5_TX 0x0
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
#define nEP6_TX 0x0
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
#define nEP7_TX 0x0
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
#define nEP1_RX 0x0
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
#define nEP2_RX 0x0
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
#define nEP3_RX 0x0
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
#define nEP4_RX 0x0
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
#define nEP5_RX 0x0
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
#define nEP6_RX 0x0
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
#define nEP7_RX 0x0
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
#define nEP0_TX_E 0x0
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
#define nEP1_TX_E 0x0
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
#define nEP2_TX_E 0x0
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
#define nEP3_TX_E 0x0
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
#define nEP4_TX_E 0x0
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
#define nEP5_TX_E 0x0
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
#define nEP6_TX_E 0x0
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
#define nEP7_TX_E 0x0
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
#define nEP1_RX_E 0x0
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
#define nEP2_RX_E 0x0
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
#define nEP3_RX_E 0x0
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
#define nEP4_RX_E 0x0
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
#define nEP5_RX_E 0x0
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
#define nEP6_RX_E 0x0
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
#define nEP7_RX_E 0x0
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
#define nSUSPEND_B 0x0
#define RESUME_B 0x2 /* Resume indicator */
#define nRESUME_B 0x0
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
#define nRESET_OR_BABLE_B 0x0
#define SOF_B 0x8 /* Start of frame */
#define nSOF_B 0x0
#define CONN_B 0x10 /* Connection indicator */
#define nCONN_B 0x0
#define DISCON_B 0x20 /* Disconnect indicator */
#define nDISCON_B 0x0
#define SESSION_REQ_B 0x40 /* Session Request */
#define nSESSION_REQ_B 0x0
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
#define nVBUS_ERROR_B 0x0
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
#define nSUSPEND_BE 0x0
#define RESUME_BE 0x2 /* Resume indicator int enable */
#define nRESUME_BE 0x0
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
#define nRESET_OR_BABLE_BE 0x0
#define SOF_BE 0x8 /* Start of frame int enable */
#define nSOF_BE 0x0
#define CONN_BE 0x10 /* Connection indicator int enable */
#define nCONN_BE 0x0
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
#define nDISCON_BE 0x0
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
#define nSESSION_REQ_BE 0x0
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
#define nVBUS_ERROR_BE 0x0
/* Bit masks for USB_FRAME */
#define FRAME_NUMBER 0x7ff /* Frame number */
/* Bit masks for USB_INDEX */
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
#define nGLOBAL_ENA 0x0
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
#define nEP1_TX_ENA 0x0
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
#define nEP2_TX_ENA 0x0
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
#define nEP3_TX_ENA 0x0
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
#define nEP4_TX_ENA 0x0
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
#define nEP5_TX_ENA 0x0
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
#define nEP6_TX_ENA 0x0
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
#define nEP7_TX_ENA 0x0
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
#define nEP1_RX_ENA 0x0
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
#define nEP2_RX_ENA 0x0
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
#define nEP3_RX_ENA 0x0
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
#define nEP4_RX_ENA 0x0
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
#define nEP5_RX_ENA 0x0
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
#define nEP6_RX_ENA 0x0
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
#define nEP7_RX_ENA 0x0
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
#define nSESSION 0x0
#define HOST_REQ 0x2 /* Host negotiation request */
#define nHOST_REQ 0x0
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
#define nHOST_MODE 0x0
#define VBUS0 0x8 /* Vbus level indicator[0] */
#define nVBUS0 0x0
#define VBUS1 0x10 /* Vbus level indicator[1] */
#define nVBUS1 0x0
#define LSDEV 0x20 /* Low-speed indicator */
#define nLSDEV 0x0
#define FSDEV 0x40 /* Full or High-speed indicator */
#define nFSDEV 0x0
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
#define nB_DEVICE 0x0
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
#define nDRIVE_VBUS_ON 0x0
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
#define nDRIVE_VBUS_OFF 0x0
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
#define nCHRG_VBUS_START 0x0
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
#define nCHRG_VBUS_END 0x0
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
#define nDISCHRG_VBUS_START 0x0
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
#define nDISCHRG_VBUS_END 0x0
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
#define nDRIVE_VBUS_ON_ENA 0x0
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
#define nDRIVE_VBUS_OFF_ENA 0x0
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
#define nCHRG_VBUS_START_ENA 0x0
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
#define nCHRG_VBUS_END_ENA 0x0
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
#define nDISCHRG_VBUS_START_ENA 0x0
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
#define nDISCHRG_VBUS_END_ENA 0x0
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
#define nRXPKTRDY 0x0
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
#define nTXPKTRDY 0x0
#define STALL_SENT 0x4 /* STALL handshake sent */
#define nSTALL_SENT 0x0
#define DATAEND 0x8 /* Data end indicator */
#define nDATAEND 0x0
#define SETUPEND 0x10 /* Setup end */
#define nSETUPEND 0x0
#define SENDSTALL 0x20 /* Send STALL handshake */
#define nSENDSTALL 0x0
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
#define nSERVICED_RXPKTRDY 0x0
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
#define nSERVICED_SETUPEND 0x0
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
#define nFLUSHFIFO 0x0
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
#define nSTALL_RECEIVED_H 0x0
#define SETUPPKT_H 0x8 /* send Setup token host mode */
#define nSETUPPKT_H 0x0
#define ERROR_H 0x10 /* timeout error indicator host mode */
#define nERROR_H 0x0
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
#define nREQPKT_H 0x0
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
#define nSTATUSPKT_H 0x0
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
#define nNAK_TIMEOUT_H 0x0
/* Bit masks for USB_COUNT0 */
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
/* Bit masks for USB_NAKLIMIT0 */
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
/* Bit masks for USB_TX_MAX_PACKET */
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_RX_MAX_PACKET */
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
#define nTXPKTRDY_T 0x0
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
#define nFIFO_NOT_EMPTY_T 0x0
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
#define nUNDERRUN_T 0x0
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
#define nFLUSHFIFO_T 0x0
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
#define nSTALL_SEND_T 0x0
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
#define nSTALL_SENT_T 0x0
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_T 0x0
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
#define nINCOMPTX_T 0x0
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_T 0x0
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
#define nFORCE_DATATOGGLE_T 0x0
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_T 0x0
#define ISO_T 0x4000 /* enable Isochronous transfers */
#define nISO_T 0x0
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOSET_T 0x0
#define ERROR_TH 0x4 /* error condition host mode */
#define nERROR_TH 0x0
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_TH 0x0
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
#define nNAK_TIMEOUT_TH 0x0
/* Bit masks for USB_TXCOUNT */
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
#define nRXPKTRDY_R 0x0
#define FIFO_FULL_R 0x2 /* FIFO not empty */
#define nFIFO_FULL_R 0x0
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
#define nOVERRUN_R 0x0
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
#define nDATAERROR_R 0x0
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
#define nFLUSHFIFO_R 0x0
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
#define nSTALL_SEND_R 0x0
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
#define nSTALL_SENT_R 0x0
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
#define nCLEAR_DATATOGGLE_R 0x0
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
#define nINCOMPRX_R 0x0
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
#define nDMAREQMODE_R 0x0
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
#define nDISNYET_R 0x0
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
#define nDMAREQ_ENA_R 0x0
#define ISO_R 0x4000 /* enable Isochronous transfers */
#define nISO_R 0x0
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
#define nAUTOCLEAR_R 0x0
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
#define nERROR_RH 0x0
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
#define nREQPKT_RH 0x0
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
#define nSTALL_RECEIVED_RH 0x0
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
#define nINCOMPRX_RH 0x0
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
#define nDMAREQMODE_RH 0x0
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
#define nAUTOREQ_RH 0x0
/* Bit masks for USB_RXCOUNT */
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
/* Bit masks for USB_TXTYPE */
#define TARGET_EP_NO_T 0xf /* EP number */
#define PROTOCOL_T 0xc /* transfer type */
/* Bit masks for USB_TXINTERVAL */
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
/* Bit masks for USB_RXTYPE */
#define TARGET_EP_NO_R 0xf /* EP number */
#define PROTOCOL_R 0xc /* transfer type */
/* Bit masks for USB_RXINTERVAL */
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
#define nDMA0_INT 0x0
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
#define nDMA1_INT 0x0
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
#define nDMA2_INT 0x0
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
#define nDMA3_INT 0x0
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
#define nDMA4_INT 0x0
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
#define nDMA5_INT 0x0
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
#define nDMA6_INT 0x0
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
#define nDMA7_INT 0x0
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
#define nDMA_ENA 0x0
#define DIRECTION 0x2 /* direction of DMA transfer */
#define nDIRECTION 0x0
#define MODE 0x4 /* DMA Bus error */
#define nMODE 0x0
#define INT_ENA 0x8 /* Interrupt enable */
#define nINT_ENA 0x0
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
#define nBUSERROR 0x0
/* Bit masks for USB_DMAxADDRHIGH */
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxADDRLOW */
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxCOUNTHIGH */
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
/* Bit masks for USB_DMAxCOUNTLOW */
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
#endif /* _DEF_BF525_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* defBF531.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _DEFBF531_H
#define _DEFBF531_H
#include <defBF532.h>
#endif /* _DEFBF531_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* defBF533.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _DEFBF533_H
#define _DEFBF533_H
#include <defBF532.h>
#endif /* _DEFBF533_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for register-access and bit-manipulation.
**
**/
#ifndef _DEF_BF536_H
#define _DEF_BF536_H
/* Identical MMR Space To BF537 Processor */
#include <defBF537.h>
#endif /* _DEF_BF536_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for register-access and bit-manipulation.
**
**/
#ifndef _DEF_BF537_H
#define _DEF_BF537_H
/* Include all Core registers and bit definitions */
#include <def_LPBlackfin.h>
/* Include all MMR and bit defines common to BF534 */
#include <defBF534.h>
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#endif /* _MISRA_RULES */
/************************************************************************************
** Define EMAC Section Unique to BF536/BF537
*************************************************************************************/
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
/* Listing for IEEE-Supported Count Registers */
#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
/***********************************************************************************
** System MMR Register Bits And Macros
**
** Disclaimer: All macros are intended to make C and Assembly code more readable.
** Use these macros carefully, as any that do left shifts for field
** depositing will result in the lower order bits being destroyed. Any
** macro that shifts left to properly position the bit-field should be
** used as part of an OR to initialize a register and NOT as a dynamic
** modifier UNLESS the lower order bits are saved and ORed back in when
** the macro is used.
*************************************************************************************/
/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
/* EMAC_OPMODE Masks */
#define RE 0x00000001 /* Receiver Enable */
#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
#define HU 0x00000010 /* Hash Filter Unicast Address */
#define HM 0x00000020 /* Hash Filter Multicast Address */
#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
#define PR 0x00000080 /* Promiscuous Mode Enable */
#define IFE 0x00000100 /* Inverse Filtering Enable */
#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
#define PBF 0x00000400 /* Pass Bad Frames Enable */
#define PSF 0x00000800 /* Pass Short Frames Enable */
#define RAF 0x00001000 /* Receive-All Mode */
#define TE 0x00010000 /* Transmitter Enable */
#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
#define DC 0x00080000 /* Deferral Check */
#define BOLMT 0x00300000 /* Back-Off Limit */
#define BOLMT_10 0x00000000 /* 10-bit range */
#define BOLMT_8 0x00100000 /* 8-bit range */
#define BOLMT_4 0x00200000 /* 4-bit range */
#define BOLMT_1 0x00300000 /* 1-bit range */
#define DRTY 0x00400000 /* Disable TX Retry On Collision */
#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
#define RMII 0x01000000 /* RMII/MII* Mode */
#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
#define LB 0x08000000 /* Internal Loopback Enable */
#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
/* EMAC_STAADD Masks */
#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
#define STADISPRE 0x00000004 /* Disable Preamble Generation */
#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
#define REGAD 0x000007C0 /* STA Register Address */
#define PHYAD 0x0000F800 /* PHY Device Address */
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
/* EMAC_STADAT Mask */
#define STADATA 0x0000FFFF /* Station Management Data */
/* EMAC_FLC Masks */
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
#define FLCE 0x00000002 /* Flow Control Enable */
#define PCF 0x00000004 /* Pass Control Frames */
#define BKPRSEN 0x00000008 /* Enable Backpressure */
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
/* EMAC_WKUP_CTL Masks */
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
#define MPKE 0x00000002 /* Magic Packet Enable */
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
#define MPKS 0x00000020 /* Magic Packet Received Status */
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
/* EMAC_WKUP_FFCMD Masks */
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
/* EMAC_WKUP_FFOFF Masks */
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
/* Set ALL Offsets */
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
/* EMAC_WKUP_FFCRC0 Masks */
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
/* EMAC_WKUP_FFCRC1 Masks */
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
/* EMAC_SYSCTL Masks */
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
/* EMAC_SYSTAT Masks */
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
#define RX_COMP 0x00001000 /* RX Frame Complete */
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
#define RX_LEN 0x00020000 /* RX Frame Length Error */
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
#define TX_COMP 0x00000001 /* TX Frame Complete */
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
/* EMAC_MMC_CTL Masks */
#define RSTC 0x00000001 /* Reset All Counters */
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
#endif /* _DEF_BF537_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** defBF541.h
**
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for register-access and bit-manipulation for the ADSP-BF541 peripherals.
**
**/
#ifndef _DEF_BF541_H
#define _DEF_BF541_H
/* Include all Core registers and bit definitions */
#include <def_LPBlackfin.h>
/** ADSP-BF541 is a non-existent processor -- no additional #defines **/
#define CHIPID 0xffc00014
#endif /* _DEF_BF541_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** defBF544.h
**
** Copyright (C) 2008 Analog Devices, Inc.
**
************************************************************************************
**
** This include file contains a list of macro "defines" to enable the programmer
** to use symbolic names for register-access and bit-manipulation.
**
**/
#ifndef _DEF_BF544_H
#define _DEF_BF544_H
/* Include all Core registers and bit definitions */
#include <def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include <defBF54x_base.h>
/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
/* Timer Registers */
#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
/* Timer Group of 3 Registers */
#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
/* EPPI0 Registers */
#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
/* Two Wire Interface Registers (TWI1) */
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
/* CAN Controller 1 Config 1 Registers */
#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
/* CAN Controller 1 Config 2 Registers */
#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
/* CAN Controller 1 Clock/Interrupt/Counter Registers */
#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
/* CAN Controller 1 Mailbox Acceptance Registers */
#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
/* CAN Controller 1 Mailbox Data Registers */
#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
/* CAN Controller 1 Mailbox Data Registers */
#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
/* HOST Port Registers */
#define HOST_CONTROL 0xffc03a00 /* HOSTDP Control Register */
#define HOST_STATUS 0xffc03a04 /* HOSTDP Status Register */
#define HOST_TIMEOUT 0xffc03a08 /* HOSTDP Acknowledge Mode Timeout Register */
/* Pixel Compositor (PIXC) Registers */
#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
/* ********************************************************** */
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
/* and MULTI BIT READ MACROS */
/* ********************************************************** */
/* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
#define nPIXC_EN 0x0
#define OVR_A_EN 0x2 /* Overlay A Enable */
#define nOVR_A_EN 0x0
#define OVR_B_EN 0x4 /* Overlay B Enable */
#define nOVR_B_EN 0x0
#define IMG_FORM 0x8 /* Image Data Format */
#define nIMG_FORM 0x0
#define OVR_FORM 0x10 /* Overlay Data Format */
#define nOVR_FORM 0x0
#define OUT_FORM 0x20 /* Output Data Format */
#define nOUT_FORM 0x0
#define UDS_MOD 0x40 /* Resampling Mode */
#define nUDS_MOD 0x0
#define TC_EN 0x80 /* Transparent Color Enable */
#define nTC_EN 0x0
#define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */
/* Bit masks for PIXC_AHSTART */
#define A_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_AHEND */
#define A_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_AVSTART */
#define A_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_AVEND */
#define A_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_ATRANSP */
#define A_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_BHSTART */
#define B_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_BHEND */
#define B_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_BVSTART */
#define B_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_BVEND */
#define B_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_BTRANSP */
#define B_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
#define nOVR_INT_EN 0x0
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
#define nFRM_INT_EN 0x0
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
#define nOVR_INT_STAT 0x0
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
#define nFRM_INT_STAT 0x0
/* Bit masks for PIXC_RYCON */
#define A11 0x3ff /* A11 in the Coefficient Matrix */
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
#define nRY_MULT4 0x0
/* Bit masks for PIXC_GUCON */
#define A21 0x3ff /* A21 in the Coefficient Matrix */
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
#define nGU_MULT4 0x0
/* Bit masks for PIXC_BVCON */
#define A31 0x3ff /* A31 in the Coefficient Matrix */
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
#define nBV_MULT4 0x0
/* Bit masks for PIXC_CCBIAS */
#define A14 0x3ff /* A14 in the Bias Vector */
#define A24 0xffc00 /* A24 in the Bias Vector */
#define A34 0x3ff00000 /* A34 in the Bias Vector */
/* Bit masks for PIXC_TC */
#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
/* Bit masks for HOST_CONTROL */
#define HOSTDP_EN 0x1 /* HOSTDP Enable */
#define nHOSTDP_EN 0x0
#define HOSTDP_END 0x2 /* Host Endianess */
#define nHOSTDP_END 0x0
#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
#define nHOSTDP_DATA_SIZE 0x0
#define HOSTDP_RST 0x8 /* HOSTDP Reset */
#define nHOSTDP_RST 0x0
#define HRDY_OVR 0x20 /* HRDY Override */
#define nHRDY_OVR 0x0
#define INT_MODE 0x40 /* Interrupt Mode */
#define nINT_MODE 0x0
#define BT_EN 0x80 /* Bus Timeout Enable */
#define nBT_EN 0x0
#define EHW 0x100 /* Enable Host Write */
#define nEHW 0x0
#define EHR 0x200 /* Enable Host Read */
#define nEHR 0x0
#define BDR 0x400 /* Burst DMA Requests */
#define nBDR 0x0
/* Bit masks for HOST_STATUS */
#define DMA_RDY 0x1 /* DMA Ready */
#define nDMA_RDY 0x0
#define FIFOFULL 0x2 /* FIFO Full */
#define nFIFOFULL 0x0
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define nFIFOEMPTY 0x0
#define DMA_CMPLT 0x8 /* DMA Complete */
#define nDMA_CMPLT 0x0
#define HSHK 0x10 /* Host Handshake */
#define nHSHK 0x0
#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
#define nHOSTDP_TOUT 0x0
#define HIRQ 0x40 /* Host Interrupt Request */
#define nHIRQ 0x0
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define nALLOW_CNFG 0x0
#define DMA_DIR 0x100 /* DMA Direction */
#define nDMA_DIR 0x0
#define BTE 0x200 /* Bus Timeout Enabled */
#define nBTE 0x0
/* Bit masks for HOST_TIMEOUT */
#define COUNT_TIMEOUT 0x7ff /* HOSTDP Timeout count */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
#define nTIMEN8 0x0
#define TIMEN9 0x2 /* Timer 9 Enable */
#define nTIMEN9 0x0
#define TIMEN10 0x4 /* Timer 10 Enable */
#define nTIMEN10 0x0
/* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */
#define nTIMDIS8 0x0
#define TIMDIS9 0x2 /* Timer 9 Disable */
#define nTIMDIS9 0x0
#define TIMDIS10 0x4 /* Timer 10 Disable */
#define nTIMDIS10 0x0
/* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */
#define nTIMIL8 0x0
#define TIMIL9 0x2 /* Timer 9 Interrupt */
#define nTIMIL9 0x0
#define TIMIL10 0x4 /* Timer 10 Interrupt */
#define nTIMIL10 0x0
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
#define nTOVF_ERR8 0x0
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
#define nTOVF_ERR9 0x0
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
#define nTOVF_ERR10 0x0
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
#define nTRUN8 0x0
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
#define nTRUN9 0x0
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
#define nTRUN10 0x0
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
#endif /* _DEF_BF544_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* def_LPBlackfin.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
#ifndef _DEF_LPBLACKFIN_H
#define _DEF_LPBLACKFIN_H
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#endif /* _MISRA_RULES */
#if !defined(__ADSPLPBLACKFIN__)
#warning def_LPBlackfin.h should only be included for 532 compatible chips.
#endif
/* ensure macro params bracketed to avoid unexpected evaluations. (GA), MISRA Rule 19.10 */
#define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */
/*********************************************************************************** */
/* System Register Bits */
/*********************************************************************************** */
/*************************************************** */
/* ASTAT register */
/*************************************************** */
/* definitions of ASTAT bit positions */
#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */
#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */
#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */
#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0 */
#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */
#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1 */
#define ASTAT_V_P 0x00000018 /* Result of last ALU0 or MAC0 operation overflowed */
#define ASTAT_V_COPY_P 0x00000003 /* Result of last ALU0 or MAC0 operation overflowed */
#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V */
/* ** Masks */
#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */
#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */
#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */
#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */
#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU0 operation generated a carry */
#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */
#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */
#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */
#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */
#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Overflow Bit */
#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Overflow Bit */
/*************************************************** */
/* SEQSTAT register */
/*************************************************** */
/* ** Bit Positions */
#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */
#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
#define SEQSTAT_HWERRCAUSE5_P 0x00000013 /* Last hw error cause bit 5 */
#define SEQSTAT_HWERRCAUSE6_P 0x00000014 /* Last hw error cause bit 6 */
#define SEQSTAT_HWERRCAUSE7_P 0x00000015 /* Last hw error cause bit 7 */
/* ** Masks */
/* Exception cause */
#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE5_P ) )
/* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P )
/* Last hw error cause */
#define SEQSTAT_HWERRCAUSE ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) )
/*************************************************** */
/* SYSCFG register */
/*************************************************** */
/* ** Bit Positions */
#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */
#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
/* ** Masks */
#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P ) /* Supervisor single step, when set it forces an exception for each instruction executed */
#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P ) /* Enable cycle counter (=1) */
#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) /* Self Nesting Interrupt Enable */
/* Backward-compatibility for typos in prior releases */
#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
#define SYSCFG_CCCEN SYSCFG_CCEN
/*********************************************************************************** */
/* Core MMR Register Map */
/*********************************************************************************** */
/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection Lookaside Buffer 3 */
#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection Lookaside Buffer 4 */
#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection Lookaside Buffer 5 */
#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection Lookaside Buffer 6 */
#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection Lookaside Buffer 7 */
#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection Lookaside Buffer 8 */
#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection Lookaside Buffer 9 */
#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection Lookaside Buffer 10 */
#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection Lookaside Buffer 11 */
#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection Lookaside Buffer 12 */
#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection Lookaside Buffer 13 */
#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection Lookaside Buffer 14 */
#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection Lookaside Buffer 15 */
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */
#define DBGSTAT 0xFFE05008 /* Debug Status Register */
/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
#define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register */
#define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register 0 */
#define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register 1 */
#define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register 2 */
#define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register 3 */
#define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register 4 */
#define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register 5 */
#define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register 0 */
#define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register 1 */
#define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register 2 */
#define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register 3 */
#define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register 4 */
#define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register 5 */
#define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */
#define WPDA0 0xFFE07140 /* Watchpoint Data Address Register 0 */
#define WPDA1 0xFFE07144 /* Watchpoint Data Address Register 1 */
#define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register 0 */
#define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register 1 */
#define WPSTAT 0xFFE07200 /* Watchpoint Status Register */
/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */
#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */
#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */
/*********************************************************************************** */
/* Core MMR Register Bits */
/*********************************************************************************** */
/*************************************************** */
/* EVT registers (ILAT, IMASK, and IPEND). */
/*************************************************** */
/* ** Bit Positions */
#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
#define EVT_EVX_P 0x00000003 /* Exception bit position */
#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
/* ** Masks */
#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
/*************************************************** */
/* DMEM_CONTROL Register */
/*************************************************** */
/* ** Bit Positions */
#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */
#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
#define ENDCPLB_P 0x01 /* Enable DCPLBS */
#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
/* ** Masks */
#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */
#define ENDCPLB 0x00000002 /* Enable DCPLB */
#define ASRAM_BSRAM 0x00000000
#define ACACHE_BSRAM 0x00000008
#define ACACHE_BCACHE 0x0000000C
#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
/* IMEM_CONTROL Register */
/* ** Bit Positions */
#define ENIM_P 0x00 /* Enable L1 Code Memory */
#define IMCTL_ENIM_P 0x00 /* "" (older define) */
#define ENICPLB_P 0x01 /* Enable ICPLB */
#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
#define IMC_P 0x02 /* Enable */
#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */
#define ILOC0_P 0x03 /* Lock Way 0 */
#define ILOC1_P 0x04 /* Lock Way 1 */
#define ILOC2_P 0x05 /* Lock Way 2 */
#define ILOC3_P 0x06 /* Lock Way 3 */
#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */
/* ** Masks */
#define ENIM 0x00000001 /* Enable L1 Code Memory */
#define ENICPLB 0x00000002 /* Enable ICPLB */
#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
#define ILOC0 0x00000008 /* Lock Way 0 */
#define ILOC1 0x00000010 /* Lock Way 1 */
#define ILOC2 0x00000020 /* Lock Way 2 */
#define ILOC3 0x00000040 /* Lock Way 3 */
#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */
/* TCNTL Masks */
#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */
#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
#define TAUTORLD 0x00000004 /* Timer auto reload */
#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
/* TCNTL Bit Positions */
#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */
#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */
#define TAUTORLD_P 0x00000002 /* Timer auto reload */
#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
/* DCPLB_DATA and ICPLB_DATA Registers */
/*** Bit Positions */
#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */
/*** Masks */
#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
/*** ICPLB_DATA only */
#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
/*** DCPLB_DATA only */
#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */
/* 1= allocate cache lines on write-through writes. */
#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
/* ITEST_COMMAND and DTEST_COMMAND Registers */
/*** Masks */
#define TEST_READ 0x00000000 /* Read Access */
#define TEST_WRITE 0x00000002 /* Write Access */
#define TEST_TAG 0x00000000 /* Access TAG */
#define TEST_DATA 0x00000004 /* Access DATA */
#define TEST_DW0 0x00000000 /* Select Double Word 0 */
#define TEST_DW1 0x00000008 /* Select Double Word 1 */
#define TEST_DW2 0x00000010 /* Select Double Word 2 */
#define TEST_DW3 0x00000018 /* Select Double Word 3 */
#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
/* ensure macro params bracketed to avoid unexpected evaluations. (GA) MISRA Rule 19.10 */
#define TEST_SET(x) (((x) << 5) & 0x03E0) /* Set Index 0->31 */
#define TEST_WAY0 0x00000000 /* Access Way0 */
#define TEST_WAY1 0x04000000 /* Access Way1 */
/*** ITEST_COMMAND only */
#define TEST_WAY2 0x08000000 /* Access Way2 */
#define TEST_WAY3 0x0C000000 /* Access Way3 */
/*** DTEST_COMMAND only */
#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
#endif /* _DEF_LPBLACKFIN_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* defblackfin.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */
#ifndef _DEF_BLACKFIN_H
#define _DEF_BLACKFIN_H
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#endif /* _MISRA_RULES */
#if defined(__ADSPLPBLACKFIN__)
#warning defblackfin.h should only be included for 535 compatible chips.
#endif
/* Macro parameters should be enclosed in parantheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
#define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */
/*********************************************************************************** */
/* System Register Bits */
/*********************************************************************************** */
/*************************************************** */
/* ASTAT register */
/*************************************************** */
#if !defined(__ADSPLPBLACKFIN__)
/* ** Bit Positions */
#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */
#define ASTAT_V_COPY_P 0x00000003 /* Result of last DAG operation overflowed */
#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
#else /* !__ADSPLPBLACKFIN__ */
/* definitions of ASTAT bit positions for next revision of BLACKFIN */
#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */
#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */
#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0_P */
#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */
#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1_P */
#define ASTAT_V_P 0x00000018 /* Result of last op written to data register file. */
#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V_P */
#endif /* !__ADSPLPBLACKFIN__ */
/* ** Masks */
#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */
#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */
#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */
#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */
#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */
#if !defined(__ADSPLPBLACKFIN__)
#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */
#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Result of last DAG operation overflowed */
#else /* !__ADSPLPBLACKFIN__ */
#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */
#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */
#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU1 operation generated a carry */
#define ASTAT_AV0S MK_BMSK_(ASTAT_AV0S_P) /* Sticky version of ASTAT_AV0_P */
#define ASTAT_AV1S MK_BMSK_(ASTAT_AV1S_P) /* Sticky version of ASTAT_AV1_P */
#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Result of last op written to data register file. */
#define ASTAT_VS MK_BMSK_(ASTAT_VS_P) /* Sticky version of ASTAT_V_P */
#endif /* !__ADSPLPBLACKFIN__ */
/*************************************************** */
/* SEQSTAT register */
/*************************************************** */
/* ** Bit Positions */
#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
#define SEQSTAT_OMODE0_P 0x0000000A /* Operating mode: 00 user, 01 supervisor, 1x debug */
#define SEQSTAT_OMODE1_P 0x0000000B /* Operating mode: 00 user, 01 supervisor, 1x debug */
#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */
#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
/* ** Masks */
/* Exception cause */
#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
MK_BMSK_(SEQSTAT_EXCAUSE5_P) )
/* Operating mode: 00 user, 01 supervisor, 1x debug */
#define SEQSTAT_OMODE ( MK_BMSK_(SEQSTAT_OMODE0_P) | \
MK_BMSK_(SEQSTAT_OMODE1_P) )
/* Pending idle mode request, set by IDLE instruction */
#define SEQSTAT_IDLE_REQ MK_BMSK_(SEQSTAT_IDLE_REQ_P)
/* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P)
/* Last hw error cause */
#define SEQSTAT_HWERRCAUSE ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) )
/*************************************************** */
/* SYSCFG register */
/*************************************************** */
/* ** Bit Positions */
#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */
#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
#define SYSCFG_SNEN_P 0x00000002 /* Enable self-nesting interrupts (=1) */
/* ** Masks */
#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P) /* Supervisor single step, when set it forces an exception for each instruction executed */
#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P) /* Enable cycle counter (=1) */
#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) /* Enable self-nesting interrupts (=1) */
/* Backward-compatibility for typos in prior releases */
#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
#define SYSCFG_CCCEN SYSCFG_CCEN
/*********************************************************************************** */
/* Core MMR Register Map */
/*********************************************************************************** */
/* Cache & SRAM Memory */
#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address (Read Only) */
#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
#define MMR_TIMEOUT 0xFFE00010 /* Memory-Mapped Register Timeout Register */
#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
#define DTEST_INDEX 0xFFE00304 /* Data Test Index Register */
#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
#define DTEST_DATA2 0xFFE00408 /* Data Test Data Register */
#define DTEST_DATA3 0xFFE0040C /* Data Test Data Register */
#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cache Protection Lookaside Buffer 0 */
#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cache Protection Lookaside Buffer 1 */
#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cache Protection Lookaside Buffer 2 */
#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cache Protection Lookaside Buffer 3 */
#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cache Protection Lookaside Buffer 4 */
#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cache Protection Lookaside Buffer 5 */
#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cache Protection Lookaside Buffer 6 */
#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cache Protection Lookaside Buffer 7 */
#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cache Protection Lookaside Buffer 8 */
#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cache Protection Lookaside Buffer 9 */
#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cache Protection Lookaside Buffer 10 */
#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cache Protection Lookaside Buffer 11 */
#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cache Protection Lookaside Buffer 12 */
#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cache Protection Lookaside Buffer 13 */
#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cache Protection Lookaside Buffer 14 */
#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cache Protection Lookaside Buffer 15 */
#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
/* Event/Interrupt Registers */
#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
#define ILAT 0xFFE0210C /* Interrupt Latch Register */
/* Core Timer Registers */
#define TCNTL 0xFFE03000 /* Core Timer Control Register */
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
/* Debug/MP/Emulation Registers */
#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */
#define DBGCTL 0xFFE05004 /* Debug Control Register */
#define DBGSTAT 0xFFE05008 /* Debug Status Register */
#define EMUDAT 0xFFE0500C /* Emulator Data Register */
/* Trace Buffer Registers */
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
#define TBUF 0xFFE06100 /* Trace Buffer */
/* Watch Point Control Registers */
#define WPIACTL 0xFFE07000 /* Instruction Watch Point Control Register */
#define WPIA0 0xFFE07040 /* Instruction Watch Point Address 0 */
#define WPIA1 0xFFE07044 /* Instruction Watch Point Address 1 */
#define WPIA2 0xFFE07048 /* Instruction Watch Point Address 2 */
#define WPIA3 0xFFE0704C /* Instruction Watch Point Address 3 */
#define WPIA4 0xFFE07050 /* Instruction Watch Point Address 4 */
#define WPIA5 0xFFE07054 /* Instruction Watch Point Address 5 */
#define WPIACNT0 0xFFE07080 /* Instruction Watch Point Counter 0 */
#define WPIACNT1 0xFFE07084 /* Instruction Watch Point Counter 1 */
#define WPIACNT2 0xFFE07088 /* Instruction Watch Point Counter 2 */
#define WPIACNT3 0xFFE0708C /* Instruction Watch Point Counter 3 */
#define WPIACNT4 0xFFE07090 /* Instruction Watch Point Counter 4 */
#define WPIACNT5 0xFFE07094 /* Instruction Watch Point Counter 5 */
#define WPDACTL 0xFFE07100 /* Data Watch Point Control Register */
#define WPDA0 0xFFE07140 /* Data Watch Point Address 0 */
#define WPDA1 0xFFE07144 /* Data Watch Point Address 1 */
#define WPDACNT0 0xFFE07180 /* Data Watch Point Counter 0 */
#define WPDACNT1 0xFFE07184 /* Data Watch Point Counter 1 */
#define WPSTAT 0xFFE07200 /* Watch Point Status Register */
/* Performance Monitor Registers */
#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */
#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */
#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */
/*********************************************************************************** */
/* Core MMR Register Bits */
/*********************************************************************************** */
/*************************************************** */
/* EVT registers (ILAT, IMASK, and IPEND). */
/*************************************************** */
/* ** Bit Positions */
#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
#define EVT_EVX_P 0x00000003 /* Exception bit position */
#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
/* ** Masks */
#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
/*************************************************** */
/* DMEM_CONTROL register */
/*************************************************** */
/* ** Bit Positions */
#define ENDM_P 0x00 /* Enable Data Memory L1 */
#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
#define ENDCPLB_P 0x01 /* Enable DCPLBS */
#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
/* ** Masks */
#define ENDM MK_BMSK_(DMCTL_ENDM_P) /* Enable Data Memory L1 */
/* Bank A set as SRAM, Bank B set as SRAM */
#define ASRAM_BSRAM 0x00000000
/* Enable DCPLB */
#define ENDCPLB MK_BMSK_(DMCTL_ENDCPLB_P)
/* Bank A set as CACHE, Bank B set as SRAM */
#define ACACHE_BSRAM 0x00000008
/* Bank A set as CACHE, Bank B set as CACHE */
#define ACACHE_BCACHE 0x0000000C
#define DCBS 0x00000010 /* If HIGHBIT is 1, select L1 data memory B */
/* If HIGHBIT is 0, select L1 data memory A */
/* If LOWBIT is 1, select L1 memory bank B */
/* If LOWBIT is 0, select L1 memory bank A */
/* IMEM_CONTROL Masks */
#define ENIM 0x00000001 /* Enable L1 Code Memory */
#define ENICPLB 0x00000002 /* Enable ICPLB */
#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
/* TCNTL Masks */
#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */
#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
#define TAUTORLD 0x00000004 /* Timer auto reload */
#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
/* TCNTL Bit Positions */
#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */
#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */
#define TAUTORLD_P 0x00000002 /* Timer auto reload */
#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
/* DCPLB_DATA and ICPLB_DATA Masks */
#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
/* only applies to L1 data memory */
#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
#define CPLB_DA0ACC 0x00000040 /* 0=access allowed from either DAG, 1=access from DAG0 only */
/* only applies in L1 data memory controller */
#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
/* only applies in L1 data memory controller */
#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
/* only applies in L1 data memory controller in cache mode */
#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
/* DCPLB_DATA and ICPLB_DATA Bit Positions */
#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
#define CPLB_USER_RD_P 0x00000002 /* */
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
#if !defined(__ADSPLPBLACKFIN__)
#define ASTAT_AC0_P ASTAT_AC0_COPY_P
#define ASTAT_AC_P ASTAT_AC0_COPY_P
#define ASTAT_AV0_P ASTAT_V_COPY_P
#define ASTAT_AC MK_BMSK_(ASTAT_AC0_COPY_P)
#define ASTAT_AV1 MK_BMSK_(ASTAT_V_COPY_P)
#endif
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
#endif /* _DEF_BLACKFIN_H */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/*
** Include appropriate header file for platform.
** Copyright (C) 2008 Analog Devices, Inc.
*/
#ifndef __ADI_PLATFORM_H
#define __ADI_PLATFORM_H
#ifdef __ASSEMBLY__
#if defined (__ADSPBF531__)
#include <cdefBF531.h>
#elif defined (__ADSPBF532__)
#include <cdefBF532.h>
#elif defined (__ADSPBF533__)
#include <cdefBF533.h>
#elif defined (__ADSPBF534__)
#include <cdefBF534.h>
#elif defined (__ADSPBF535__)
#include <cdefBF535.h>
#elif defined (__ADSPBF536__)
#include <cdefBF536.h>
#elif defined (__ADSPBF537__)
#include <cdefBF537.h>
#elif defined (__ADSPBF538__)
#include <cdefBF538.h>
#elif defined (__ADSPBF539__)
#include <cdefBF539.h>
#elif defined (__ADSPBF561__)
#include <cdefBF561.h>
#elif defined (__AD6531__)
#include <cdefAD6531.h>
#elif defined (__AD6532__)
#include <cdefAD6532.h>
#elif defined (__AD6723__)
#include <cdefAD6723.h>
#elif defined (__AD6900__)
#include <cdefAD6900.h>
#elif defined (__AD6901__)
#include <cdefAD6901.h>
#elif defined (__AD6902__)
#include <cdefAD6902.h>
#elif defined (__AD6903__)
#include <cdefAD6903.h>
#elif defined (__AD6904__)
#include <cdefAD6904.h>
#elif defined (__ADSPBF522__)
#include <cdefBF522.h>
#elif defined (__ADSPBF525__)
#include <cdefBF525.h>
#elif defined (__ADSPBF527__)
#include <cdefBF527.h>
#elif defined (__ADSPBF542__) || defined (__ADSPBF541__)
#include <cdefBF542.h>
#elif defined (__ADSPBF544__)
#include <cdefBF544.h>
#elif defined (__ADSPBF547__)
#include <cdefBF547.h>
#elif defined (__ADSPBF548__)
#include <cdefBF548.h>
#elif defined (__ADSPBF549__)
#include <cdefBF549.h>
#else
#error Processor Type Not Supported
#endif
#else
#if defined (__ADSPBF531__)
#include <defBF531.h>
#elif defined (__ADSPBF532__)
#include <defBF532.h>
#elif defined (__ADSPBF533__)
#include <defBF533.h>
#elif defined (__ADSPBF534__)
#include <defBF534.h>
#elif defined (__ADSPBF535__)
#include <defBF535.h>
#elif defined (__ADSPBF536__)
#include <defBF536.h>
#elif defined (__ADSPBF537__)
#include <defBF537.h>
#elif defined (__ADSPBF538__)
#include <defBF538.h>
#elif defined (__ADSPBF539__)
#include <defBF539.h>
#elif defined (__ADSPBF561__)
#include <defBF561.h>
#elif defined (__AD6531__)
#include <defAD6531.h>
#elif defined (__AD6532__)
#include <defAD6532.h>
#elif defined (__AD6723__)
#include <defAD6723.h>
#elif defined (__AD6900__)
#include <defAD6900.h>
#elif defined (__AD6901__)
#include <defAD6901.h>
#elif defined (__AD6902__)
#include <defAD6902.h>
#elif defined (__AD6903__)
#include <defAD6903.h>
#elif defined (__AD6904__)
#include <defAD6904.h>
#elif defined (__ADSPBF522__)
#include <defBF522.h>
#elif defined (__ADSPBF525__)
#include <defBF525.h>
#elif defined (__ADSPBF527__)
#include <defBF527.h>
#elif defined (__ADSPBF542__) || defined (__ADSPBF541__)
#include <defBF542.h>
#elif defined (__ADSPBF544__)
#include <defBF544.h>
#elif defined (__ADSPBF547__)
#include <defBF547.h>
#elif defined (__ADSPBF548__)
#include <defBF548.h>
#elif defined (__ADSPBF549__)
#include <defBF549.h>
#else
#error Processor Type Not Supported
#endif
#endif /* __ASSEMBLY__ */
#endif /* __INC_BLACKFIN__ */

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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* anomaly_macros_rtl.h : $Revision$
*
* Copyright (C) 2008 Analog Devices, Inc.
*
* This file defines macros used within the run-time libraries to enable
* certain anomaly workarounds for the appropriate chips and silicon
* revisions. Certain macros are defined for silicon-revision none - this
* is to ensure behaviour is unchanged from libraries supplied with
* earlier tools versions, where a small number of anomaly workarounds
* were applied in all library flavours. __FORCE_LEGACY_WORKAROUNDS__
* is defined in this case.
*
* This file defines macros for a subset of all anomalies that may impact
* the run-time libraries.
*
************************************************************************/
#if !defined(__SILICON_REVISION__)
#define __FORCE_LEGACY_WORKAROUNDS__
#endif
/* 05-00-0096 - PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC
**
** ADSP-BF531/2/3 - revs 0.0-0.1,
** ADSP-BF561 - revs 0.0-0.1 (not supported in VDSP++ 4.0)
**
*/
#define WA_05000096 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || \
defined(__ADSPBF561__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x1)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0109 - Reserved bits in SYSCFG register not set at power on
**
** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3. 0.0, 0.1 not supported in VDSP++ 4.0)
**
** Changes to start code.
*/
#define WA_05000109 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || \
defined(__ADSPBF561__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0123 - DTEST_COMMAND initiated memory access may be incorrect if
** data cache or DMA is active.
**
** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
*/
#define WA_05000123 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || \
defined(__ADSPBF561__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0125 - Erroneous exception when enabling cache
**
** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
**
*/
#define WA_05000125 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || \
defined(__ADSPBF561__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0137 - DMEM_CONTROL<12> is not set on Reset
**
** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
**
** Changes to start code.
**
*/
#define WA_05000137 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0158 - "Boot fails when data cache enabled: Data from a Data Cache
** fill can be corrupted after or during instruction DMA if certain core
** stalls exist"
**
** Impacted:
** BF533/3/1 : 0.0-0.4 (fixed 0.5)
**
** The workaround we have only works for si-revisions >= 0.3. No workaround for
** ealier revisions.
*/
#define WA_05000158 \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
((defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || \
(__SILICON_REVISION__ >= 0x3 && \
__SILICON_REVISION__ < 0x5))) || \
defined(__FORCE_LEGACY_WORKAROUNDS__)))
/* 05-00-0204 - "Incorrect data read with write-through cache and
** allocate cache lines on reads only mode.
**
** This problem is cache related with high speed clocks. It apparently does
** not impact BF531 and BF532 because they cannot run at high enough clock
** to cause the anomaly. We build libs for BF532 though so that means we will
** need to do the workaround for BF532 and BF531 also.
**
** Also the 0.3 to 0.4 revision is not an inflexion for libs BF532 and BF561.
** This means a RT check may be required to avoid doing the WA for 0.4.
**
** Impacted:
** BF533 - 0.0-0.3 (fixed 0.4)
** BF534 - 0.0 (fixed 0.1)
** BF536 - 0.0 (fixed 0.1)
** BF537 - 0.0 (fixed 0.1)
** BF538 - 0.0 (fixed 0.1)
** BF539 - 0.0 (fixed 0.1)
** BF561 - 0.0-0.3 (fixed 0.4)
*/
#if defined(__ADI_LIB_BUILD__)
# define __BUILDBF53123 1 /* building one single library for BF531/2/3 */
#else
# define __BUILDBF53123 0
#endif
#define WA_05000204 \
((((__BUILDBF53123==1 && \
(defined(__ADSPBF531__) || defined(__ADSPBF532__))) || \
(defined(__ADSPBF533__) || defined(__ADSPBF561__))) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x3))) || \
((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0))))
#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || defined(__ADSPBF561__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x3)))
/* check at RT for 0.4 revs when doing 204 workaround */
# define WA_05000204_CHECK_AVOID_FOR_REV <=3
#elif ((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0)))
/* check at RT for 0.4 revs when doing 204 workaround */
# define WA_05000204_CHECK_AVOID_FOR_REV <1
#else
/* do not check at RT for 0.4 revs when doing 204 workaround */
#endif
/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of
* the ICPLB Data registers differ"
*
* When bit 9 and bit 12 of the ICPLB Data MMR differ, the cache may
* not update properly. For example, for a particular cache line,
* the cache tag may be valid while the contents of that cache line
* are not present in the cache.
*
* Impacted:
*
* BF531/2/3 - 0.0-0.4 (fixed 0.5)
* BF534/6/7/8/9 - 0.0-0.2 (fixed 0.3)
* BF561 - 0.0-0.4 (fixed 0.5)
* BF535/AD6532/AD6900 - all revs
*/
#define WA_05000258 \
defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || \
!defined(__ADSPLPBLACKFIN__) || \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
(__SILICON_REVISION__ <= 0x4)) || \
((defined(__ADSPBF534__) || \
defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || \
defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(__SILICON_REVISION__ <= 0x2)) || \
((defined(__ADSPBF561__)) && \
(__SILICON_REVISION__ <= 0x4)) || \
((defined(__ADSPBF561__)) && \
(__SILICON_REVISION__ < 0x1)))
/* 05-00-0259 - "Non-deterministic ICPLB descriptors delivered to
* hardware". Whenever ICPLBs are disabled via an MMR write, immediately
* follow this write with a CSYNC, and locate the MMR write and CSYNC
* within the same aligned 64 bit word.
*
* This problem impacts all revisions of Blackfins.
*/
#define WA_05000259 \
(defined(__ADSPBLACKFIN__) && defined(__SILICON_REVISION__))
/* 05-00-0261 - "DCPLB_FAULT_ADDR MMR may be corrupted".
* The DCPLB_FAULT_ADDR MMR may contain the fault address of a
* aborted memory access which generated both a protection exception
* and a stall.
*
* We work around this by initially ignoring a DCPLB miss exception
* on the assumption that the faulting address might be invalid.
* We return without servicing. The exception will be raised
* again when the faulting instruction is re-executed. The fault
* address is correct this time round so the miss exception can
* be serviced as normal. The only complication is we have to
* ensure that we are about to service the same miss rather than
* a miss raised within a higher-priority interrupt handler, where
* the fault address could again be invalid. We therefore record
* the last seen RETX and only service an exception when RETX and
* the last seen RETX are equal.
*
* This problem impacts:
* BF531/2/3 - rev 0.0-0.4 (fixed 0.5)
* BF534/6/7/8/9 - rev 0.0-0.2 (fixed 0.3)
* BF561 - rev 0.0-0.4 (fixed 0.5)
*
*/
#define WA_05000261 \
defined(__SILICON_REVISION__) && \
(__SILICON_REVISION__ == 0xffff || \
((defined(__ADSPBF531__) || \
defined(__ADSPBF532__) || \
defined(__ADSPBF533__)) && \
(__SILICON_REVISION__ <= 0x4)) || \
((defined(__ADSPBF534__) || \
defined(__ADSPBF536__) || \
defined(__ADSPBF537__) || \
defined(__ADSPBF538__) || \
defined(__ADSPBF539__)) && \
(__SILICON_REVISION__ <= 0x2)) || \
((defined(__ADSPBF561__)) && \
(__SILICON_REVISION__ <= 0x4)) || \
((defined(__ADSPBF561__)) && \
(__SILICON_REVISION__ < 0x1)))
/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers".
* When the SPI slave boot completes, the final DMA IRQ is cleared
* but the DMA5_CONFIG and SPI_CTL registers are not reset to their
* default states.
*
* We work around this by resetting the registers to their default
* values at the beginning of the CRT. The only issue would be when
* users boot from flash and make use of the DMA or serial port.
* In this case, users would need to modify the CRT.
*
* This problem impacts all revisions of ADSP-BF531/2/3/8/9
*/
#define WA_05000229 \
(defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \
(defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
defined(__ADSPBF533__) || defined(__ADSPBF538__) || \
defined(__ADSPBF539__)))
/* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a
* particular stage".
*
* Where an interrupt occurs killing a stalled system MMR write, and the ISR
* executes an SSYNC, execution execution may stall indefinitely".
*
* The workaround is to execute a mispredicted jump over a dummy MMR read,
* thus killing the read. Also to avoid a system MMR write in two slots
* after a not predicted conditional jump.
*
* This problem impacts:
* BF531/2/3 - all revs
* BF534/6/7/8/9 - all revs
* BF561/6 - all revs
*/
#define WA_05000283 \
defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)

93
libgloss/bfin/include/sys/excause.h Normal file
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@ -0,0 +1,93 @@
/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* excause.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
/*
** Definitions of constants for the four user-level bits in EXCAUSE,
** the field from SYSSTAT that is set when the EXCPT instruction is
** invoked.
*/
#ifndef _EXCAUSE_H
#define _EXCAUSE_H
/*
** Value 0x0 - exit program. (halt)
** R0 => exit status.
*/
#define EX_EXIT_PROG 0x0
/*
** Value 0x1 - abnormal exit (abort)
*/
#define EX_ABORT_PROG 0x1
/*
** Value 0x2 - invoke system service.
** R0 => command.
** R1 => first arg
** R2 => second arg
*/
#define EX_SYS_REQ 0x2
/*
** Available commands:
*/
#define EX_SYSREQ_NONE 0x00 /* Do nothing */
#define EX_SYSREQ_REG_ISR 0x01 /* Register an interrupt handler.
R1==EVT entry, R2==func ptr
Returns previous entry in R0. */
#define EX_SYSREQ_RAISE_INT 0x02 /* Cause an interrupt
R1 = int number */
/*
** Values 0x3 to 0x4 currently undefined.
*/
/*
** Value 0x5 - File I/O
** R0 => first arg
** R1 => second arg
** R2 => third arg
** R4 => command
** result => R0
*/
#define EX_FILE_IO 0x5
/*
** Available commands:
** XXX stdout/stderr are handled separately for writing.
*/
#define EX_FILEIO_OPEN 0x00 /* R0 => dev, R1=> path, R2=>mode */
#define EX_FILEIO_CLOSE 0x01 /* R0=> fid */
#define EX_FILEIO_WRITE 0x02 /* R0=>fid, R1=>data, R2=>length */
#define EX_FILEIO_READ 0x03 /* R0=>fid, R1=>data, R2=>length */
#define EX_FILEIO_SEEK 0x04 /* R0=>fid, R1=>offset, R2=>mode */
#define EX_FILEIO_DUP 0x05 /* R0=>fid */
/*
** Values 0x6 to 0xF currently undefined.
*/
#endif /* _EXCAUSE_H */

260
libgloss/bfin/include/sys/exception.h Normal file
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/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#pragma once
#ifndef __NO_BUILTIN
#pragma system_header /* exception.h */
#endif
/************************************************************************
*
* exception.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifndef _EXCEPTION_H
#define _EXCEPTION_H
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_5_7)
#pragma diag(suppress:misra_rule_6_3)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#pragma diag(suppress:misra_rule_19_10)
#pragma diag(suppress:misra_rule_19_13)
#endif /* _MISRA_RULES */
/*
** Definitions for user-friendly interrupt handling.
*/
/*
** Memory-Mapped Registers (MMRs) - these record what causes address
** exceptions.
*/
#define EX_DATA_FAULT_STATUS 0xFFE00008
#define EX_DATA_FAULT_ADDR 0xFFE0000C
#define EX_CODE_FAULT_STATUS 0xFFE01008
#define EX_CODE_FAULT_ADDR 0xFFE0100C
/*
** Event Vector Table
*/
#define EX_EVENT_VECTOR_TABLE 0xFFE02000
/*
** Meaning of the various bits in EXCAUSE field in SEQSTAT register.
*/
#define EX_BITS 0x3F /* All EXCAUSE bits */
#define EX_TYPE 0x30 /* The bits which define the type */
#define EX_DEBUG 0x10 /* If set, is a debug exception type */
#define EX_SYS 0x20 /* If set, is a system exception type */
/* If neither set, is from EXCPT instr */
#define EX_IS_DEBUG_EXCEPTION(E) (((E)&EX_TYPE)==EX_DEBUG)
#define EX_IS_SYSTEM_EXCEPTION(E) (((E)&EX_TYPE)==EX_SYS)
#define EX_IS_USER_EXCEPTION(E) (((E)&EX_TYPE)==0)
/*
** Service exceptions continue from the instruction after the one
** that raised the exception.
** Error exceptions restart the instruction that raised the exception.
*/
#define EX_IS_SERVICE_EXCEPTION(E) (!EX_IS_SYSTEM_EXCEPTION(E))
#define EX_IS_ERROR_EXCEPTION(E) (EX_IS_SYSTEM_EXCEPTION(E))
#define EX_DB_SINGLE_STEP 0x10 /* Processor is single-stepping */
#define EX_DB_EMTRCOVRFLW 0x11 /* Emulation Trace buffer overflowed */
#define EX_SYS_UNDEFINSTR 0x21 /* Undefined instruction */
#define EX_SYS_ILLINSTRC 0x22 /* Illegal instruction combination */
#define EX_SYS_DCPLBPROT 0x23 /* Data CPLB Protection violation */
#define EX_SYS_DALIGN 0x24 /* Data access misaligned address violation */
#define EX_SYS_UNRECEVT 0x25 /* Unrecoverable event */
#define EX_SYS_DCPLBMISS 0x26 /* Data access CPLB Miss */
#define EX_SYS_DCPLBMHIT 0x27 /* Data access CPLB Multiple Hits */
#define EX_SYS_EMWATCHPT 0x28 /* Emulation watch point match */
#define EX_SYS_CACCESSEX 0x29 /* Code fetch access exception */
#define EX_SYS_CALIGN 0x2A /* Attempted misaligned instr cache fetch */
#define EX_SYS_CCPLBPROT 0x2B /* Code fetch CPLB Protection */
#define EX_SYS_CCPLBMISS 0x2C /* CPLB miss on an instruction fetch */
#define EX_SYS_CCPLBMHIT 0x2D /* Code fetch CPLB Multiple Hits */
#define EX_SYS_ILLUSESUP 0x2E /* Illegal use of Supervisor Resource */
/*
** Meaning of the various bits in HWERRCAUSE in SEQSTAT
*/
#define EX_HWBITS (0x1F<<14) /* bits 18:14 */
#if !defined(__ADSPLPBLACKFIN__)
#define EX_HW_NOMEM1 (0x16<<14)
#define EX_HW_NOMEM2 (0x17<<14)
#else
#define EX_HW_SYSMMR (0x02<<14)
#define EX_HW_EXTMEM (0x03<<14)
#endif
#define EX_HW_DMAHIT (0x01<<14)
#define EX_HW_PERFMON (0x12<<14)
#define EX_HW_RAISE (0x18<<14)
/*
** Meaning of the bits in DATA_FAULT_STATUS and CODE_FAULT_STATUS
*/
#define EX_DATA_FAULT_ILLADDR (1<<19) /* non-existent memory */
#define EX_DATA_FAULT_DAG (1<<18) /* 0=>DAG0, 1=>DAG1 */
#define EX_DATA_FAULT_USERSUPV (1<<17) /* 0=>user mode, 1=> supervisor */
#define EX_DATA_FAULT_READWRITE (1<<16) /* 0=>read, 1=>write */
#define EX_DATA_FAULT_CPLB 0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */
#define EX_CODE_FAULT_ILLADDR (1<<19) /* non-existent memory */
#define EX_CODE_FAULT_USERSUPV (1<<17) /* 0=>user mode, 1=> supervisor */
#define EX_CODE_FAULT_CPLB 0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */
/*
** The kinds of interrupt that can occur. These are also the
** indices into the Event Vector Table.
*/
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ik_err=-1,
ik_emulation,
ik_reset,
ik_nmi,
ik_exception,
ik_global_int_enable,
ik_hardware_err,
ik_timer,
ik_ivg7,
ik_ivg8,
ik_ivg9,
ik_ivg10,
ik_ivg11,
ik_ivg12,
ik_ivg13,
ik_ivg14,
ik_ivg15,
num_interrupt_kind
} interrupt_kind;
/*
** Structure for recording details of an exception or interrupt
** that has occurred.
*/
typedef struct {
interrupt_kind kind; /* whether interrupt, exception, etc. */
int value; /* interrupt number, exception type, etc. */
void *pc; /* PC at point where exception occurred */
void *addr; /* if an address faulted, which one. */
unsigned status; /* if an address faulted, why. */
} interrupt_info;
/*
** Macro for defining an interrupt routine
*/
typedef void (*ex_handler_fn)();
#define EX_HANDLER(KIND,NAME) \
_Pragma(#KIND) \
void NAME ()
#define EX_HANDLER_PROTO(KIND, NAME) EX_HANDLER(KIND, NAME)
#define EX_INTERRUPT_HANDLER(NAME) EX_HANDLER(interrupt,NAME)
#define EX_EXCEPTION_HANDLER(NAME) EX_HANDLER(exception,NAME)
#define EX_NMI_HANDLER(NAME) EX_HANDLER(nmi,NAME)
#define EX_REENTRANT_HANDLER(NAME) \
_Pragma("interrupt_reentrant") \
EX_HANDLER(interrupt,NAME)
/*
** A convenience function for setting up the interrupt_info contents.
** Must be called from immediately with the interrupt handler.
*/
void get_interrupt_info(interrupt_kind int_kind, interrupt_info *int_info);
/*
** Diagnostics function for reporting unexpected events.
*/
void _ex_report_event(interrupt_info *int_info);
/*
** Register an interrupt handler within the EVT.
** Return previous value if there was one.
*/
ex_handler_fn register_handler(interrupt_kind int_kind, ex_handler_fn handler);
/*
** Some magic values for registering default and null handlers.
*/
#define EX_INT_DEFAULT ((ex_handler_fn)-1)
#define EX_INT_IGNORE ((ex_handler_fn)0)
/*
** Extended function to register an interrupt handler within the EVT.
** Returns the old handler.
**
** If enabled == EX_INT_ALWAYS_ENABLE, install fn (if fn != EX_INT_IGNORE
** and fn != EX_INT_DISABLE), and then enable the interrupt in IMASK then
** return
**
** If fn == EX_INT_IGNORE, disable the interrupt
** If fn == EX_INT_DEFAULT, delete the handler entry in the EVT and disable
** the interrupt in IMASK
** Otherwise, install the new interrupt handler. Then,
** If enabled == EX_INT_DISABLE, disable the interrupt in IMASK
** If enabled == EX_INT_ENABLE, enable the interrupt in IMASK
** otherwise leave the interrupt status alone.
*/
ex_handler_fn register_handler_ex(interrupt_kind kind, ex_handler_fn fn,
int enable);
/* Constants for the enabled parameter of register_handler_ex */
#define EX_INT_DISABLE 0
#define EX_INT_ENABLE 1
#define EX_INT_KEEP_IMASK -1
#define EX_INT_ALWAYS_ENABLE 2
/*
** Allow the user to raise exceptions from C.
*/
int raise_interrupt(interrupt_kind kind, int which,
int cmd, int arg1, int arg2);
#ifdef __cplusplus
} /* extern "C" */
#endif
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
#endif /* _EXCEPTION_H */

38
libgloss/bfin/include/sys/mc_typedef.h Normal file
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@ -0,0 +1,38 @@
/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#pragma once
#ifndef __NO_BUILTIN
#pragma system_header /* sys/mc_typedef.h */
#endif
/************************************************************************
*
* sys/mc_typedef.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
/* Define testset_t. */
#ifndef _SYS_MC_TYPEDEF_H
#define _SYS_MC_TYPEDEF_H
#if !defined(__ADSPLPBLACKFIN__)
typedef volatile unsigned char testset_t;
#elif defined(__WORKAROUND_TESTSET_ALIGN) /* require 32-bit aligned address */
typedef volatile unsigned int testset_t;
#else
typedef volatile unsigned short testset_t;
#endif
#endif /* _SYS_MC_TYPEDEF_H */

19
libgloss/bfin/include/sys/platform.h Normal file
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@ -0,0 +1,19 @@
/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#ifndef _PLATFORM_H
#define _PLATFORM_H
/* Generic Wrapper for platform specific header file.
Copyright (C) 2008 Analog Devices, Inc.
*/
#include <sys/_adi_platform.h>
#endif

84
libgloss/bfin/include/sys/pll.h Normal file
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@ -0,0 +1,84 @@
/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/************************************************************************
*
* pll.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
************************************************************************/
#ifdef __ASSEMBLY__
#pragma once
#pragma system_header
#endif
#ifndef _PLL_H
#define _PLL_H
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_6_3)
#endif /* _MISRA_RULES */
#define NO_STARTUP_SET 0
#define MAX_IN_STARTUP 1
#ifdef __ASSEMBLY__
enum clkctrl_t {
/* no modification of PLL rates in CRT startup - default */
no_startup_set=NO_STARTUP_SET,
/* CRT startup sets PLL rates to suitable maximum values */
max_in_startup=MAX_IN_STARTUP
};
/*
** Define __clk_ctrl to 1 to cause startup to set PLL rates for maximum
** speed performance rates. The default version defined in the runtime-
** libraries defines __clk_ctrl to 0 which disables the feature.
*/
extern enum clkctrl_t __clk_ctrl;
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ADSPLPBLACKFIN__)
/* Sets SSEL and CSEL bits in PLL_DIV to passed values.
** Returns -1 on failure.
*/
int pll_set_system_clocks(int _csel, int _ssel);
/*
** Sets MSEL and DF bits in PLL_CTL and LOCKCNT in PLL_LOCKCNT.
** Returns -1 on failure.
*/
int pll_set_system_vco(int _msel, int _df, int _lockcnt);
#endif /* __ADSPLPBLACKFIN__ */
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
#endif /* _PLL_H */

100
libgloss/bfin/include/sysreg.h Normal file
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@ -0,0 +1,100 @@
/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
/* This file must be used with compiler version 8.0.1.5 */
#ifdef __VERSIONNUM__
#if __VERSIONNUM__ != 0x08000105
#error The compiler version does not match the version of the sysreg.h include
#endif
#endif
/************************************************************************
*
* sysreg.h
*
* Copyright (C) 2008 Analog Devices, Inc.
*
***********************************************************************/
#pragma once
#ifndef __NO_BUILTIN
#pragma system_header /* sysreg.h */
#endif
/* sysreg definitions for use in sysreg_read and sysreg_write calls. */
#ifndef _SYSREG_H
#define _SYSREG_H
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_2_4)
#pragma diag(suppress:misra_rule_6_3)
#pragma diag(suppress:misra_rule_19_10)
#endif /* _MISRA_RULES */
enum {
/* the following can be used in word-sized sysreg reads and writes */
reg_I0,
reg_I1,
reg_I2,
reg_I3,
reg_M0,
reg_M1,
reg_M2,
reg_M3,
reg_B0,
reg_B1,
reg_B2,
reg_B3,
reg_L0,
reg_L1,
reg_L2,
reg_L3,
reg_LC0,
reg_LC1,
reg_LT0,
reg_LT1,
reg_LB0,
reg_LB1,
reg_RETS,
reg_RETI,
reg_RETX,
reg_RETN,
reg_RETE,
reg_SEQSTAT,
reg_SYSCFG,
reg_CYCLES,
reg_CYCLES2,
reg_A0W,
reg_A0X,
reg_A1W,
reg_A1X,
reg_FP,
reg_SP,
reg_ASTAT,
/* the following can be used in double-word sysreg reads and writes */
reg_A0,
reg_A1,
__num_SysRegs
};
#define STACKPOINTER reg_SP
#define FRAMEPOINTER reg_FP
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */
#endif /* _SYSREG_H */

11
libgloss/bfin/syscalls.c
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@ -32,13 +32,10 @@ register char *stack_ptr asm ("SP");
static inline int
do_syscall (int reason, void *arg)
{
int result;
asm volatile ("[--sp] = %1; [--sp] = %2; \
r1 = [sp++]; r0 = [sp++]; \
raise 0; %0 = r0;"
: "=r" (result)
: "r" (reason), "r" (arg)
: "R0", "R1", "memory", "cc");
register int r asm ("P0") = reason;
register void *a asm ("R0") = arg;
register int result asm ("R0");
asm volatile ("excpt 0;" : "=r" (result) : "a" (r), "r" (a) : "memory", "CC");
return result;
}

2
libgloss/libnosys/configure vendored
View File

@ -1948,6 +1948,8 @@ case "${target}" in
;;
strongarm-*-*)
;;
bfin-*-*)
;;
cris-*-* | crisv32-*-*)
;;
d10v*)

2
libgloss/libnosys/configure.in
View File

@ -51,6 +51,8 @@ case "${target}" in
;;
strongarm-*-*)
;;
bfin-*-*)
;;
cris-*-* | crisv32-*-*)
;;
d10v*)