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Annotate sparc objects with cpu hardware capabilities used.
bfd/ * elfxx-sparc.c (_bfd_sparc_elf_merge_private_bfd_data): New. * elfxx-sparc.h: Declare it. * elf32-sparc.c (elf32_sparc_merge_private_bfd_data): Call it. * elf64-sparc.c (elf64_sparc_merge_private_bfd_data): Likewise. binutils/ * readelf.c (display_sparc_hwcaps): New. (display_sparc_gnu_attribute): New. (process_sparc_specific): New. (process_arch_specific): When EM_SPARC, EM_SPARC32PLUS, or EM_SPARCV9 invoke process_sparc_specific. gas/ * config/tc-sparc.c (hwcap_seen): New bitmask, defined when not TE_SOLARIS. (sparc_ip): When not TE_SOLARIS, accumulate hwcap bits from sparc_opcode->flags of instruction into hwcap_seen. (sparc_md_end): Create Tag_GNU_Sparc_HWCAPS attribute if hwcap_seen is non-zero and not TE_SOLARIS. gas/testsuite/ * gas/sparc/hpcvis3.s: Update for fixed fchksum16 mnemonic. * gas/sparc/hpcvis3.d: Likewise. include/elf/ * sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute. (ELF_SPARC_HWCAP_*): New HWCAPS bitmask values. include/opcode/ * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. opcodes/ * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag bits. Fix "fchksm16" mnemonic.
This commit is contained in:
David S. Miller
parent
36b6320736
commit
7661a752ca
@ -1,3 +1,8 @@
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2011-09-21 David S. Miller <davem@davemloft.net>
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* sparc.h (Tag_GNU_Sparc_HWCAPS): New object attribute.
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(ELF_SPARC_HWCAP_*): New HWCAPS bitmask values.
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2011-08-12 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/13082
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@ -1,5 +1,6 @@
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/* SPARC ELF support for BFD.
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2008, 2010
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2008, 2010,
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2011
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Free Software Foundation, Inc.
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By Doug Evans, Cygnus Support, <dje@cygnus.com>.
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@ -185,4 +186,31 @@ END_RELOC_NUMBERS (R_SPARC_max)
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#define DT_SPARC_REGISTER 0x70000001
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/* Object attribute tags. */
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enum
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{
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/* 0-3 are generic. */
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Tag_GNU_Sparc_HWCAPS = 4,
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};
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/* These values match the AV_SPARC_* hwcap bits defined under Solaris. */
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#define ELF_SPARC_HWCAP_MUL32 0x00000001 /* umul/umulcc/smul/smulcc insns */
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#define ELF_SPARC_HWCAP_DIV32 0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
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#define ELF_SPARC_HWCAP_FSMULD 0x00000004 /* 'fsmuld' insn */
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#define ELF_SPARC_HWCAP_V8PLUS 0x00000008 /* v9 insns available to 32bit */
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#define ELF_SPARC_HWCAP_POPC 0x00000010 /* 'popc' insn */
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#define ELF_SPARC_HWCAP_VIS 0x00000020 /* VIS insns */
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#define ELF_SPARC_HWCAP_VIS2 0x00000040 /* VIS2 insns */
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#define ELF_SPARC_HWCAP_ASI_BLK_INIT \
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0x00000080 /* block init ASIs */
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#define ELF_SPARC_HWCAP_FMAF 0x00000100 /* fused multiply-add */
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#define ELF_SPARC_HWCAP_VIS3 0x00000400 /* VIS3 insns */
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#define ELF_SPARC_HWCAP_HPC 0x00000800 /* HPC insns */
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#define ELF_SPARC_HWCAP_RANDOM 0x00001000 /* 'random' insn */
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#define ELF_SPARC_HWCAP_TRANS 0x00002000 /* transaction insns */
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#define ELF_SPARC_HWCAP_FJFMAU 0x00004000 /* unfused multiply-add */
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#define ELF_SPARC_HWCAP_IMA 0x00008000 /* integer multiply-add */
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#define ELF_SPARC_HWCAP_ASI_CACHE_SPARING \
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0x00010000 /* cache sparing ASIs */
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#endif /* _ELF_SPARC_H */
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@ -1,3 +1,10 @@
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2011-09-21 David S. Miller <davem@davemloft.net>
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* sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
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(F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
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F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
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F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
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2011-08-09 Chao-ying Fu <fu@mips.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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@ -1,6 +1,6 @@
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/* Definitions for opcode table for the sparc.
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
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2003, 2005, 2010 Free Software Foundation, Inc.
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2003, 2005, 2010, 2011 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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@ -98,18 +98,37 @@ typedef struct sparc_opcode
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unsigned long lose; /* Bits that must not be set. */
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const char *args;
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/* This was called "delayed" in versions before the flags. */
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char flags;
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unsigned int flags;
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short architecture; /* Bitmask of sparc_opcode_arch_val's. */
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} sparc_opcode;
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#define F_DELAYED 1 /* Delayed branch. */
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#define F_ALIAS 2 /* Alias for a "real" instruction. */
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#define F_UNBR 4 /* Unconditional branch. */
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#define F_CONDBR 8 /* Conditional branch. */
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#define F_JSR 16 /* Subroutine call. */
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#define F_FLOAT 32 /* Floating point instruction (not a branch). */
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#define F_FBR 64 /* Floating point branch. */
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/* FIXME: Add F_ANACHRONISTIC flag for v9. */
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#define F_DELAYED 0x00000001 /* Delayed branch. */
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#define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */
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#define F_UNBR 0x00000004 /* Unconditional branch. */
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#define F_CONDBR 0x00000008 /* Conditional branch. */
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#define F_JSR 0x00000010 /* Subroutine call. */
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#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */
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#define F_FBR 0x00000040 /* Floating point branch. */
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#define F_MUL32 0x00000100 /* umul/umulcc/smul/smulcc insns */
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#define F_DIV32 0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */
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#define F_FSMULD 0x00000400 /* 'fsmuld' insn */
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#define F_V8PLUS 0x00000800 /* v9 insns available to 32bit */
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#define F_POPC 0x00001000 /* 'popc' insn */
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#define F_VIS 0x00002000 /* VIS insns */
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#define F_VIS2 0x00004000 /* VIS2 insns */
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#define F_ASI_BLK_INIT 0x00008000 /* block init ASIs */
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#define F_FMAF 0x00010000 /* fused multiply-add */
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#define F_VIS3 0x00020000 /* VIS3 insns */
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#define F_HPC 0x00040000 /* HPC insns */
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#define F_RANDOM 0x00080000 /* 'random' insn */
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#define F_TRANS 0x00100000 /* transaction insns */
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#define F_FJFMAU 0x00200000 /* unfused multiply-add */
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#define F_IMA 0x00400000 /* integer multiply-add */
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#define F_ASI_CACHE_SPARING \
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0x00800000 /* cache sparing ASIs */
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#define F_HWCAP_MASK 0x00ffff00
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/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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macro), which is 64 bits. It is handled as a special case.
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