include/opcode/
* mips.h (mips_decode_reg_operand): New function. (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): New macros. (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other macros to cover the gaps. (INSN2_MOD_SP): Replace with... (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): Delete. opcodes/ * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI): New macros. (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R) (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete. (mips_builtin_opcodes): Use the new position-based read-write flags instead of field-based ones. Use UDI for "udi..." instructions. * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete. (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags. (WR_SP, RD_16): New macros. (RD_SP): Redefine as an INSN2_* flag. (MOD_SP): Redefine in terms of RD_SP and WR_SP. (mips16_opcodes): Use the new position-based read-write flags instead of field-based ones. Use RD_16 for "nop". Move RD_SP to pinfo2 field. * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2): New macros. (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj) (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D) (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete. (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP. (micromips_opcodes): Use the new position-based read-write flags instead of field-based ones. * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand. (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead of field-based flags. gas/ * config/tc-mips.c (MAX_OPERANDS): New macro. (mips_operand_array): New structure. (mips_operands, mips16_operands, micromips_operands): New arrays. (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) (micromips_to_32_reg_q_map): Delete. (insn_operands, insn_opno, insn_extract_operand): New functions. (validate_mips_insn): Take a mips_operand_array as argument and use it to build up a list of operands. Extend to handle INSN_MACRO and MIPS16. (validate_mips16_insn): New function. (validate_micromips_insn): Take a mips_operand_array as argument. Handle INSN_MACRO. (md_begin): Initialize mips_operands, mips16_operands and micromips_operands. Call validate_mips_insn and validate_micromips_insn for macro instructions too. Call validate_mips16_insn for MIPS16 instructions. (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): New functions. (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use them. Handle INSN_UDI. (get_append_method): Use gpr_read_mask.
This commit is contained in:
Richard Sandiford
parent
304263c612
commit
762d970290
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@ -1,3 +1,29 @@
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h (mips_decode_reg_operand): New function.
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(INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
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(INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
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(INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
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New macros.
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(INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
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(INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
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(INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
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(INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
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(INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
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(INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
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(INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
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(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
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(INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
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(INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
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macros to cover the gaps.
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(INSN2_MOD_SP): Replace with...
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(INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
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(MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
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(MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
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(MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
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(MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
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Delete.
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2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
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* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
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@ -604,6 +604,17 @@ mips_decode_int_operand (const struct mips_int_operand *operand,
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return uval;
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}
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/* Return the register that OPERAND encodes as UVAL. */
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static inline int
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mips_decode_reg_operand (const struct mips_reg_operand *operand,
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unsigned int uval)
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{
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if (operand->reg_map)
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uval = operand->reg_map[uval];
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return uval;
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}
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/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
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Return the address that it encodes. */
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@ -836,71 +847,67 @@ struct mips_opcode
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/* These are the bits which may be set in the pinfo field of an
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instructions, if it is not equal to INSN_MACRO. */
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/* Modifies the general purpose register in OP_*_RD. */
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#define INSN_WRITE_GPR_D 0x00000001
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/* Modifies the general purpose register in OP_*_RT. */
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#define INSN_WRITE_GPR_T 0x00000002
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/* Writes to operand number N. */
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#define INSN_WRITE_SHIFT 0
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#define INSN_WRITE_1 0x00000001
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#define INSN_WRITE_2 0x00000002
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#define INSN_WRITE_ALL 0x00000003
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/* Reads from operand number N. */
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#define INSN_READ_SHIFT 2
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#define INSN_READ_1 0x00000004
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#define INSN_READ_2 0x00000008
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#define INSN_READ_3 0x00000010
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#define INSN_READ_4 0x00000020
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#define INSN_READ_ALL 0x0000003c
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/* Modifies general purpose register 31. */
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#define INSN_WRITE_GPR_31 0x00000004
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/* Modifies the floating point register in OP_*_FD. */
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#define INSN_WRITE_FPR_D 0x00000008
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/* Modifies the floating point register in OP_*_FS. */
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#define INSN_WRITE_FPR_S 0x00000010
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/* Modifies the floating point register in OP_*_FT. */
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#define INSN_WRITE_FPR_T 0x00000020
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/* Reads the general purpose register in OP_*_RS. */
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#define INSN_READ_GPR_S 0x00000040
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/* Reads the general purpose register in OP_*_RT. */
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#define INSN_READ_GPR_T 0x00000080
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/* Reads the floating point register in OP_*_FS. */
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#define INSN_READ_FPR_S 0x00000100
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/* Reads the floating point register in OP_*_FT. */
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#define INSN_READ_FPR_T 0x00000200
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/* Reads the floating point register in OP_*_FR. */
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#define INSN_READ_FPR_R 0x00000400
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#define INSN_WRITE_GPR_31 0x00000040
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/* Modifies coprocessor condition code. */
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#define INSN_WRITE_COND_CODE 0x00000800
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#define INSN_WRITE_COND_CODE 0x00000080
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/* Reads coprocessor condition code. */
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#define INSN_READ_COND_CODE 0x00001000
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#define INSN_READ_COND_CODE 0x00000100
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/* TLB operation. */
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#define INSN_TLB 0x00002000
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#define INSN_TLB 0x00000200
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/* Reads coprocessor register other than floating point register. */
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#define INSN_COP 0x00004000
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#define INSN_COP 0x00000400
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/* Instruction loads value from memory, requiring delay. */
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#define INSN_LOAD_MEMORY_DELAY 0x00008000
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#define INSN_LOAD_MEMORY_DELAY 0x00000800
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/* Instruction loads value from coprocessor, requiring delay. */
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#define INSN_LOAD_COPROC_DELAY 0x00010000
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#define INSN_LOAD_COPROC_DELAY 0x00001000
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/* Instruction has unconditional branch delay slot. */
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#define INSN_UNCOND_BRANCH_DELAY 0x00020000
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#define INSN_UNCOND_BRANCH_DELAY 0x00002000
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/* Instruction has conditional branch delay slot. */
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#define INSN_COND_BRANCH_DELAY 0x00040000
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#define INSN_COND_BRANCH_DELAY 0x00004000
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/* Conditional branch likely: if branch not taken, insn nullified. */
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#define INSN_COND_BRANCH_LIKELY 0x00080000
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#define INSN_COND_BRANCH_LIKELY 0x00008000
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/* Moves to coprocessor register, requiring delay. */
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#define INSN_COPROC_MOVE_DELAY 0x00100000
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#define INSN_COPROC_MOVE_DELAY 0x00010000
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/* Loads coprocessor register from memory, requiring delay. */
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#define INSN_COPROC_MEMORY_DELAY 0x00200000
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#define INSN_COPROC_MEMORY_DELAY 0x00020000
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/* Reads the HI register. */
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#define INSN_READ_HI 0x00400000
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#define INSN_READ_HI 0x00040000
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/* Reads the LO register. */
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#define INSN_READ_LO 0x00800000
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#define INSN_READ_LO 0x00080000
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/* Modifies the HI register. */
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#define INSN_WRITE_HI 0x01000000
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#define INSN_WRITE_HI 0x00100000
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/* Modifies the LO register. */
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#define INSN_WRITE_LO 0x02000000
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#define INSN_WRITE_LO 0x00200000
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/* Not to be placed in a branch delay slot, either architecturally
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or for ease of handling (such as with instructions that take a trap). */
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#define INSN_NO_DELAY_SLOT 0x04000000
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#define INSN_NO_DELAY_SLOT 0x00400000
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/* Instruction stores value into memory. */
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#define INSN_STORE_MEMORY 0x08000000
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#define INSN_STORE_MEMORY 0x00800000
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/* Instruction uses single precision floating point. */
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#define FP_S 0x10000000
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#define FP_S 0x01000000
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/* Instruction uses double precision floating point. */
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#define FP_D 0x20000000
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#define FP_D 0x02000000
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/* Instruction is part of the tx39's integer multiply family. */
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#define INSN_MULT 0x40000000
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/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
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#define INSN_WRITE_GPR_S 0x80000000
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#define INSN_MULT 0x04000000
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/* Reads general purpose register 24. */
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#define INSN_READ_GPR_24 0x08000000
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/* Writes to general purpose register 24. */
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#define INSN_WRITE_GPR_24 0x10000000
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/* A user-defined instruction. */
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#define INSN_UDI 0x20000000
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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#define INSN_MACRO 0xffffffff
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@ -922,62 +929,24 @@ struct mips_opcode
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only be set for macros. For instructions, FP_D in pinfo carries the
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same information. */
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#define INSN2_M_FP_D 0x00000010
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/* Modifies the general purpose register in OP_*_RZ. */
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#define INSN2_WRITE_GPR_Z 0x00000020
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/* Modifies the floating point register in OP_*_FZ. */
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#define INSN2_WRITE_FPR_Z 0x00000040
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/* Reads the general purpose register in OP_*_RZ. */
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#define INSN2_READ_GPR_Z 0x00000080
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/* Reads the floating point register in OP_*_FZ. */
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#define INSN2_READ_FPR_Z 0x00000100
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/* Reads the general purpose register in OP_*_RD. */
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#define INSN2_READ_GPR_D 0x00000200
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/* Instruction has a branch delay slot that requires a 16-bit instruction. */
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#define INSN2_BRANCH_DELAY_16BIT 0x00000400
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#define INSN2_BRANCH_DELAY_16BIT 0x00000020
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/* Instruction has a branch delay slot that requires a 32-bit instruction. */
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#define INSN2_BRANCH_DELAY_32BIT 0x00000800
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/* Reads the floating point register in MICROMIPSOP_*_FD. */
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#define INSN2_READ_FPR_D 0x00001000
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/* Modifies the general purpose register in MICROMIPSOP_*_MB. */
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#define INSN2_WRITE_GPR_MB 0x00002000
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/* Reads the general purpose register in MICROMIPSOP_*_MC. */
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#define INSN2_READ_GPR_MC 0x00004000
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/* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */
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#define INSN2_MOD_GPR_MD 0x00008000
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/* Reads the general purpose register in MICROMIPSOP_*_ME. */
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#define INSN2_READ_GPR_ME 0x00010000
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/* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */
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#define INSN2_MOD_GPR_MF 0x00020000
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/* Reads the general purpose register in MICROMIPSOP_*_MG. */
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#define INSN2_READ_GPR_MG 0x00040000
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/* Reads the general purpose register in MICROMIPSOP_*_MJ. */
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#define INSN2_READ_GPR_MJ 0x00080000
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/* Modifies the general purpose register in MICROMIPSOP_*_MJ. */
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#define INSN2_WRITE_GPR_MJ 0x00100000
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/* Reads the general purpose register in MICROMIPSOP_*_MP. */
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#define INSN2_READ_GPR_MP 0x00200000
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/* Modifies the general purpose register in MICROMIPSOP_*_MP. */
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#define INSN2_WRITE_GPR_MP 0x00400000
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/* Reads the general purpose register in MICROMIPSOP_*_MQ. */
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#define INSN2_READ_GPR_MQ 0x00800000
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/* Reads/Writes the stack pointer ($29). */
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#define INSN2_MOD_SP 0x01000000
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#define INSN2_BRANCH_DELAY_32BIT 0x00000040
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/* Writes to the stack pointer ($29). */
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#define INSN2_WRITE_SP 0x00000080
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/* Reads from the stack pointer ($29). */
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#define INSN2_READ_SP 0x00000100
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/* Reads the RA ($31) register. */
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#define INSN2_READ_GPR_31 0x02000000
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/* Reads the global pointer ($28). */
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#define INSN2_READ_GP 0x04000000
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#define INSN2_READ_GPR_31 0x00000200
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/* Reads the program counter ($pc). */
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#define INSN2_READ_PC 0x08000000
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#define INSN2_READ_PC 0x00000400
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/* Is an unconditional branch insn. */
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#define INSN2_UNCOND_BRANCH 0x10000000
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#define INSN2_UNCOND_BRANCH 0x00000800
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/* Is a conditional branch insn. */
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#define INSN2_COND_BRANCH 0x20000000
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/* Modifies the general purpose registers in MICROMIPSOP_*_MH. */
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#define INSN2_WRITE_GPR_MH 0x40000000
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/* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */
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#define INSN2_READ_GPR_MMN 0x80000000
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#define INSN2_COND_BRANCH 0x00001000
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/* Reads from $16. This is true of the MIPS16 0x6500 nop. */
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#define INSN2_READ_GPR_16 0x00002000
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/* Masks used to mark instructions to indicate which MIPS ISA level
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they were introduced in. INSN_ISA_MASK masks an enumeration that
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@ -1633,34 +1602,6 @@ extern int bfd_mips_num_opcodes;
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#define MIPS16_ALL_ARGS 0xe
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#define MIPS16_ALL_STATICS 0xb
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/* For the mips16, we use the same opcode table format and a few of
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the same flags. However, most of the flags are different. */
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/* Modifies the register in MIPS16OP_*_RX. */
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#define MIPS16_INSN_WRITE_X 0x00000001
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/* Modifies the register in MIPS16OP_*_RY. */
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#define MIPS16_INSN_WRITE_Y 0x00000002
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/* Modifies the register in MIPS16OP_*_RZ. */
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#define MIPS16_INSN_WRITE_Z 0x00000004
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/* Modifies the T ($24) register. */
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#define MIPS16_INSN_WRITE_T 0x00000008
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/* Modifies the RA ($31) register. */
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#define MIPS16_INSN_WRITE_31 0x00000020
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/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
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#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
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/* Reads the register in MIPS16OP_*_RX. */
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#define MIPS16_INSN_READ_X 0x00000080
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/* Reads the register in MIPS16OP_*_RY. */
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#define MIPS16_INSN_READ_Y 0x00000100
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/* Reads the register in MIPS16OP_*_MOVE32Z. */
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#define MIPS16_INSN_READ_Z 0x00000200
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/* Reads the T ($24) register. */
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#define MIPS16_INSN_READ_T 0x00000400
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/* Reads the SP ($29) register. */
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#define MIPS16_INSN_READ_SP 0x00000800
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/* Reads the general purpose register in MIPS16OP_*_REGR32. */
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#define MIPS16_INSN_READ_GPR_X 0x00004000
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/* The following flags have the same value for the mips16 opcode
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table:
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