mirror of
git://sourceware.org/git/newlib-cygwin.git
synced 2025-02-06 14:30:38 +08:00
2001-07-07 Ben Elliston <bje@redhat.com>
* m88k.h: Clean up and reformat. Remove unused code.
This commit is contained in:
Ben Elliston
parent
a761b473ad
commit
6e06cb0d32
@ -1,3 +1,7 @@
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2001-07-07 Ben Elliston <bje@redhat.com>
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* m88k.h: Clean up and reformat. Remove unused code.
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2001-06-14 Geoffrey Keating <geoffk@redhat.com>
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* cgen.h (cgen_keyword): Add nonalpha_chars field.
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@ -1,5 +1,5 @@
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/* Table of opcodes for the motorola 88k family.
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Copyright 1989, 1990, 1991, 1993 Free Software Foundation, Inc.
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/* Table of opcodes for the Motorola M88k family.
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Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc.
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This file is part of GDB and GAS.
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@ -34,22 +34,6 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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* pointer to the next instruction in the linked list. These pointers
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* are initialized by init_disasm().
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*
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* Structure Format
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*
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* struct INSTAB {
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* UPINT opcode;
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* char *mnemonic;
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* struct OPSPEC op1,op2,op3;
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* struct SIM_FLAGS flgs;
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* struct INSTAB *next;
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* }
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*
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* struct OPSPEC {
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* UPINT offset:5;
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* UPINT width:6;
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* UPINT type:5;
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* }
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*
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* Revision History
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*
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* Revision 1.0 11/08/85 Creation date
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@ -61,54 +45,52 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include <stdio.h>
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/* Define the number of bits in the primary opcode field of the instruction,
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the destination field, the source 1 and source 2 fields. */
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/*
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* This file contains the structures and constants needed to build the M88000
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* simulator. It is the main include file, containing all the
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* structures, macros and definitions except for the floating point
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* instruction set.
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*/
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/* Size of opcode field. */
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#define OP 8
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/*
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* The following flag informs the Simulator as to what type of byte ordering
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* will be used. For instance, a BOFLAG = 1 indicates a DEC VAX and IBM type
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* of ordering shall be used.
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*/
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/* Size of destination. */
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#define DEST 6
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/* # define BOFLAG 1 */ /* BYTE ORDERING FLAG */
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/* Size of source1. */
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#define SOURCE1 6
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/* define the number of bits in the primary opcode field of the instruction,
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* the destination field, the source 1 and source 2 fields.
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*/
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# define OP 8 /* size of opcode field */
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# define DEST 6 /* size of destination */
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# define SOURCE1 6 /* size of source1 */
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# define SOURCE2 6 /* size of source2 */
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/* Size of source2. */
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#define SOURCE2 6
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# define REGs 32 /* number of registers */
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/* Number of registers. */
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#define REGs 32
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/* Type definitions. */
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typedef unsigned int UINT;
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#define WORD long
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#define FLAG unsigned
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#define STATE short
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# define TRUE 1
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# define FALSE 0
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# define READ 0
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# define WRITE 1
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/* The next four equates define the priorities that the various classes
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* of instructions have regarding writing results back into registers and
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* signalling exceptions.
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*/
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* signalling exceptions. */
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/* PMEM is also defined in <sys/param.h> on Delta 88's. Sigh! */
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#undef PMEM
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# define PINT 0 /* Integer Priority */
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# define PFLT 1 /* Floating Point Priority */
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# define PMEM 2 /* Memory Priority */
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# define NA 3 /* Not Applicable, instruction doesnt write to regs */
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# define HIPRI 3 /* highest of these priorities */
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/* Integer priority. */
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#define PINT 0
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/* Floating point priority. */
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#define PFLT 1
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/* Memory priority. */
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#define PMEM 2
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/* Not applicable, instruction doesn't write to regs. */
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#define NA 3
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/* Highest of these priorities. */
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#define HIPRI 3
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/* The instruction registers are an artificial mechanism to speed up
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* simulator execution. In the real processor, an instruction register
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@ -122,91 +104,131 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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* Yes this wastes memory, but it executes much quicker.
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*/
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struct IR_FIELDS {
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struct IR_FIELDS
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{
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unsigned op:OP,
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dest: DEST,
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src1: SOURCE1,
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src2: SOURCE2;
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int ltncy,
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extime,
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wb_pri; /* writeback priority */
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unsigned imm_flags:2,/* immediate size */
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rs1_used:1, /* register source 1 used */
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rs2_used:1, /* register source 2 used */
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rsd_used:1, /* register source/dest. used */
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c_flag:1, /* complement */
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u_flag:1, /* upper half word */
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n_flag:1, /* execute next */
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wb_flag:1, /* uses writeback slot */
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dest_64:1, /* dest size */
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s1_64:1, /* source 1 size */
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s2_64:1, /* source 2 size */
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scale_flag:1, /* scaled register */
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/* Writeback priority. */
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wb_pri;
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/* Immediate size. */
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unsigned imm_flags:2,
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/* Register source 1 used. */
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rs1_used:1,
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/* Register source 2 used. */
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rs2_used:1,
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/* Register source/dest. used. */
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rsd_used:1,
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/* Complement. */
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c_flag:1,
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/* Upper half word. */
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u_flag:1,
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/* Execute next. */
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n_flag:1,
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/* Uses writeback slot. */
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wb_flag:1,
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/* Dest size. */
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dest_64:1,
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/* Source 1 size. */
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s1_64:1,
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/* Source 2 size. */
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s2_64:1,
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scale_flag:1,
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/* Scaled register. */
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brk_flg:1;
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};
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struct mem_segs {
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struct mem_wrd *seg; /* pointer (returned by calloc) to segment */
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unsigned long baseaddr; /* base load address from file headers */
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unsigned long endaddr; /* Ending address of segment */
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int flags; /* segment control flags (none defined 12/5/86) */
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struct mem_segs
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{
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/* Pointer (returned by calloc) to segment. */
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struct mem_wrd *seg;
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/* Base load address from file headers. */
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unsigned long baseaddr;
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/* Ending address of segment. */
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unsigned long endaddr;
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/* Segment control flags (none defined). */
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int flags;
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};
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#define MAXSEGS (10) /* max number of segment allowed */
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#define MEMSEGSIZE (sizeof(struct mem_segs))/* size of mem_segs structure */
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#if 0
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#define BRK_RD (0x01) /* break on memory read */
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#define BRK_WR (0x02) /* break on memory write */
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#define BRK_EXEC (0x04) /* break on execution */
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#define BRK_CNT (0x08) /* break on terminal count */
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#endif
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struct mem_wrd {
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struct IR_FIELDS opcode; /* simulator instruction break down */
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struct mem_wrd
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{
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/* Simulator instruction break down. */
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struct IR_FIELDS opcode;
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union {
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unsigned long l; /* memory element break down */
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/* Memory element break down. */
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unsigned long l;
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unsigned short s[2];
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unsigned char c[4];
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} mem;
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};
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#define MEMWRDSIZE (sizeof(struct mem_wrd)) /* size of each 32 bit memory model */
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/* External declarations */
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/* Size of each 32 bit memory model. */
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#define MEMWRDSIZE (sizeof (struct mem_wrd))
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extern struct mem_segs memory[];
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extern struct PROCESSOR m78000;
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struct PROCESSOR {
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struct PROCESSOR
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{
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unsigned WORD
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ip, /* execute instruction pointer */
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vbr, /* vector base register */
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psr; /* processor status register */
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/* Execute instruction pointer. */
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ip,
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/* Vector base register. */
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vbr,
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/* Processor status register. */
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psr;
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WORD S1bus, /* source 1 */
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S2bus, /* source 2 */
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Dbus, /* destination */
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DAbus, /* data address bus */
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/* Source 1. */
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WORD S1bus,
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/* Source 2. */
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S2bus,
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/* Destination. */
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Dbus,
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/* Data address bus. */
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DAbus,
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ALU,
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Regs[REGs], /* data registers */
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time_left[REGs], /* max clocks before reg is available */
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wb_pri[REGs], /* writeback priority of reg */
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SFU0_regs[REGs], /* integer unit control regs */
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SFU1_regs[REGs], /* floating point control regs */
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/* Data registers. */
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Regs[REGs],
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/* Max clocks before reg is available. */
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time_left[REGs],
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/* Writeback priority of reg. */
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wb_pri[REGs],
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/* Integer unit control regs. */
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SFU0_regs[REGs],
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/* Floating point control regs. */
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SFU1_regs[REGs],
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Scoreboard[REGs],
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Vbr;
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unsigned WORD scoreboard,
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Psw,
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Tpsw;
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FLAG jump_pending:1; /* waiting for a jump instr. */
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/* Waiting for a jump instruction. */
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FLAG jump_pending:1;
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};
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# define i26bit 1 /* size of immediate field */
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/* Size of immediate field. */
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#define i26bit 1
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#define i16bit 2
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#define i10bit 3
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/* Definitions for fields in psr */
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/* Definitions for fields in psr. */
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#define mode 31
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#define rbo 30
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@ -225,17 +247,7 @@ struct PROCESSOR {
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#define trm 1
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#define ovfm 0
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#define MODEMASK (1<<(mode-1))
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# define SILENT 0 /* simulate without output to crt */
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# define VERBOSE 1 /* simulate in verbose mode */
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# define PR_INSTR 2 /* only print instructions */
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# define RESET 16 /* reset phase */
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# define PHASE1 0 /* data path phases */
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# define PHASE2 1
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/* the 1 clock operations */
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/* The 1 clock operations. */
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#define ADDU 1
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#define ADDC 2
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@ -252,7 +264,7 @@ struct PROCESSOR {
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#define XOR ADD+7
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#define CMP ADD+8
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/* the LOADS */
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/* Loads. */
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#define LDAB CMP+1
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#define LDAH CMP+2
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@ -266,19 +278,20 @@ struct PROCESSOR {
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#define LDBU LDAD+5
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#define LDHU LDAD+6
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/* the STORES */
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/* Stores. */
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#define STB LDHU+1
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#define STH LDHU+2
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#define ST LDHU+3
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#define STD LDHU+4
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/* the exchange */
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/* Exchange. */
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#define XMEMBU LDHU+5
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#define XMEM LDHU+6
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/* the branches */
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/* Branches. */
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#define JSR STD+1
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#define BSR STD+2
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#define BR STD+3
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@ -288,14 +301,16 @@ struct PROCESSOR {
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#define RTN STD+7
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#define BCND STD+8
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/* the TRAPS */
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/* Traps. */
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#define TB1 BCND+1
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#define TB0 BCND+2
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#define TCND BCND+3
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#define RTE BCND+4
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#define TBND BCND+5
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/* the MISC instructions */
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/* Misc. */
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#define MUL TBND + 1
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#define DIV MUL +2
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#define DIVU MUL +3
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@ -309,7 +324,7 @@ struct PROCESSOR {
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#define MAK MUL +11
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#define ROT MUL +12
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/* control register manipulations */
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/* Control register manipulations. */
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#define LDCR ROT +1
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#define STCR ROT +2
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@ -319,10 +334,9 @@ struct PROCESSOR {
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#define FSTCR ROT +5
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#define FXCR ROT +6
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#define NOP XCR +1
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/* floating point instructions */
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/* Floating point instructions. */
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#define FADD NOP +1
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#define FSUB NOP +2
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@ -339,14 +353,18 @@ struct PROCESSOR {
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#define FSTC NOP +13
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#define FXC NOP +14
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# define UEXT(src,off,wid) ((((unsigned int)(src))>>(off)) & ((1<<(wid)) - 1))
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# define SEXT(src,off,wid) (((((int)(src))<<(32-((off)+(wid)))) >>(32-(wid))) )
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#define UEXT(src,off,wid) \
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((((unsigned int)(src)) >> (off)) & ((1 << (wid)) - 1))
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#define SEXT(src,off,wid) \
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(((((int)(src))<<(32 - ((off) + (wid)))) >>(32 - (wid))) )
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#define MAKE(src,off,wid) \
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((((unsigned int)(src)) & ((1 << (wid)) - 1)) << (off))
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#define opword(n) (unsigned long) (memaddr->mem.l)
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/* Constants and Masks */
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/* Constants and masks. */
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#define SFU0 0x80000000
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#define SFU1 0x84000000
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@ -360,64 +378,60 @@ struct PROCESSOR {
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#define CTRL 0x0000f000
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#define CTRLMASK 0xfc00f800
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/* Operands types */
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/* Operands types. */
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enum operand_type {
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enum operand_type
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{
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HEX = 1,
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REG = 2,
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CONT = 3,
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IND = 3,
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BF = 4,
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REGSC = 5 /* scaled register */,
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CRREG = 6 /* control register */,
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FCRREG = 7 /* floating point control register */,
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/* Scaled register. */
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REGSC = 5,
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/* Control register. */
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CRREG = 6,
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/* Floating point control register. */
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FCRREG = 7,
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PCREL = 8,
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CONDMASK = 9,
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XREG = 10, /* extended register */
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DEC = 11, /* decimal */
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/* Extended register. */
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XREG = 10,
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/* Decimal. */
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DEC = 11
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};
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/* Hashing Specification */
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/* Hashing specification. */
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#define HASHVAL 79
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/* Type definitions */
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||||
/* Structure templates. */
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typedef unsigned int UINT;
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/* Structure templates */
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#if never
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typedef struct {
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unsigned int offset:5;
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unsigned int width:6;
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||||
unsigned int type:5;
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} OPSPEC;
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#endif
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typedef struct {
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||||
typedef struct
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||||
{
|
||||
unsigned int offset;
|
||||
unsigned int width;
|
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enum operand_type type;
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} OPSPEC;
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struct SIM_FLAGS {
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int ltncy, /* latency (max number of clocks needed to execute) */
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extime, /* execution time (min number of clocks needed to execute) */
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wb_pri; /* writeback slot priority */
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unsigned op:OP, /* simulator version of opcode */
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imm_flags:2, /* 10,16 or 26 bit immediate flags */
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rs1_used:1, /* register source 1 used */
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rs2_used:1, /* register source 2 used */
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rsd_used:1, /* register source/dest used */
|
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c_flag:1, /* complement */
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u_flag:1, /* upper half word */
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n_flag:1, /* execute next */
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wb_flag:1, /* uses writeback slot */
|
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dest_64:1, /* double precision dest */
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s1_64:1, /* double precision source 1 */
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s2_64:1, /* double precision source 2 */
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||||
scale_flag:1; /* register is scaled */
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struct SIM_FLAGS
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{
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int ltncy, /* latency (max number of clocks needed to execute). */
|
||||
extime, /* execution time (min number of clocks needed to execute). */
|
||||
wb_pri; /* writeback slot priority. */
|
||||
unsigned op:OP, /* simulator version of opcode. */
|
||||
imm_flags:2, /* 10,16 or 26 bit immediate flags. */
|
||||
rs1_used:1, /* register source 1 used. */
|
||||
rs2_used:1, /* register source 2 used. */
|
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rsd_used:1, /* register source/dest used. */
|
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c_flag:1, /* complement. */
|
||||
u_flag:1, /* upper half word. */
|
||||
n_flag:1, /* execute next. */
|
||||
wb_flag:1, /* uses writeback slot. */
|
||||
dest_64:1, /* double precision dest. */
|
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s1_64:1, /* double precision source 1. */
|
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s2_64:1, /* double precision source 2. */
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scale_flag:1; /* register is scaled. */
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};
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|
||||
typedef struct INSTRUCTAB {
|
||||
|
||||
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Reference in New Issue
Block a user