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Fix 3 DV bugs, and a few minor cleanups.

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gas/
	* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
	postincrement modified registers.  Handle IA64_OPND_R3_2 addl
	source registers.
	(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
	* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
	* gas/ia64/dv-raw-err.l: Likewise.
	* gas/ia64/dv-waw-err.l: Update sed pattern.
	* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
	* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
	* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
	* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds.  Delete
	break, mov-immediate, nop.
	* ia64-opc-f.c: Delete fpsub instructions.
	* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
	address operand.  Rewrite using macros to avoid long lines.
	* ia64-opc.h (POSTINC): Define.
	* ia64-asmtab.c: Regenerate.
This commit is contained in:
Jim Wilson 2000-08-16 23:20:14 +00:00
parent 2768864a59
commit 6afcd43da0
2 changed files with 6 additions and 1 deletions
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4
include/opcode/ChangeLog
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@ -1,3 +1,7 @@
2000-08-16 Jim Wilson <wilson@cygnus.com>
* ia64.h (IA64_OPCODE_POSTINC): New.
2000-08-15 H.J. Lu <hjl@gnu.org> 2000-08-15 H.J. Lu <hjl@gnu.org>
* i386.h: Swap the Intel syntax "movsx"/"movzx" due to the * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the

3
include/opcode/ia64.h
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@ -300,7 +300,8 @@ struct ia64_opcode
#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ #define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ #define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ #define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ #define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
/* A macro to extract the major opcode from an instruction. */ /* A macro to extract the major opcode from an instruction. */
#define IA64_OP(i) (((i) >> 37) & 0xf) #define IA64_OP(i) (((i) >> 37) & 0xf)