gas/
* config/tc-mips.c (mips_set_options): Add ase_mcu. (mips_opts): Initialise ase_mcu to -1. (ISA_SUPPORTS_MCU_ASE): New macro. (MIPS_CPU_ASE_MCU): Likewise. (is_opcode_valid): Handle MCU. (macro_build, macro): Likewise. (validate_mips_insn, validate_micromips_insn): Likewise. (mips_ip): Likewise. (options): Add OPTION_MCU and OPTION_NO_MCU. (md_longopts): Add mmcu and mno-mcu. (md_parse_option): Handle OPTION_MCU and OPTION_NO_MCU. (mips_after_parse_args): Handle MCU. (s_mipsset): Likewise. (md_show_usage): Handle MCU options. * doc/as.texinfo: Document -mmcu and -mno-mcu options. * doc/c-mips.texi: Likewise, and document ".set mcu" and ".set nomcu" directives. gas/testsuite/ * gas/mips/micromips@mcu.d: New test. * gas/mips/mcu.d: Likewise. * gas/mips/mcu.s: New test source. * gas/mips/mips.exp: Run the new tests. include/opcode/ * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. (INSN_ASE_MASK): Add the MCU bit. (INSN_MCU): New macro. (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. opcodes/ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2" and "mips64r2". (print_insn_args, print_insn_micromips): Handle MCU. * micromips-opc.c (MC): New macro. (micromips_opcodes): Add "aclr", "aset" and "iret". * mips-opc.c (MC): New macro. (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
This commit is contained in:
Maciej W. Rozycki
parent
f9b846656d
commit
69f8cb36d3
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@ -1,3 +1,13 @@
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2011-08-09 Chao-ying Fu <fu@mips.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
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(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
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(INSN_ASE_MASK): Add the MCU bit.
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(INSN_MCU): New macro.
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(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
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(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
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2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
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* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
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@ -187,6 +187,12 @@
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#define OP_SH_MTACC_D 13
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#define OP_MASK_MTACC_D 0x3
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/* MIPS MCU ASE */
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#define OP_MASK_3BITPOS 0x7
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#define OP_SH_3BITPOS 12
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#define OP_MASK_OFFSET12 0xfff
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#define OP_SH_OFFSET12 0
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#define OP_OP_COP0 0x10
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#define OP_OP_COP1 0x11
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#define OP_OP_COP2 0x12
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@ -251,8 +257,6 @@
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#define OP_SH_CODE10 0
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#define OP_MASK_TRAP 0
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#define OP_SH_TRAP 0
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#define OP_MASK_OFFSET12 0
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#define OP_SH_OFFSET12 0
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#define OP_MASK_OFFSET10 0
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#define OP_SH_OFFSET10 0
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#define OP_MASK_RS3 0
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@ -473,6 +477,10 @@ struct mips_opcode
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"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
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"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
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MCU ASE usage:
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"~" 12 bit offset (OP_*_OFFSET12)
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"\" 3 bit position for aset and aclr (OP_*_3BITPOS)
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UDI immediates:
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"+1" UDI immediate bits 6-10
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"+2" UDI immediate bits 6-15
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@ -508,7 +516,7 @@ struct mips_opcode
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Characters used so far, for quick reference when adding more:
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"1234567890"
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"%[]<>(),+:'@!$*&"
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"%[]<>(),+:'@!$*&\~"
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"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
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"abcdefghijklopqrstuvwxz"
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@ -711,7 +719,7 @@ static const unsigned int mips_isa_table[] =
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#define INSN_OCTEON 0x00000800
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/* Masks used for MIPS-defined ASEs. */
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#define INSN_ASE_MASK 0x3c00f000
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#define INSN_ASE_MASK 0x3c00f010
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/* DSP ASE */
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#define INSN_DSP 0x00001000
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@ -760,6 +768,9 @@ static const unsigned int mips_isa_table[] =
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/* RMI Xlr instruction */
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#define INSN_XLR 0x00000020
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/* MCU (MicroController) ASE */
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#define INSN_MCU 0x00000010
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/* MIPS ISA defines, use instead of hardcoding ISA level. */
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#define ISA_UNKNOWN 0 /* Gas internal use. */
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@ -862,9 +873,13 @@ static const unsigned int mips_isa_table[] =
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enum
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{
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M_ABS,
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M_ACLR_AB,
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M_ACLR_OB,
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M_ADD_I,
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M_ADDU_I,
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M_AND_I,
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M_ASET_AB,
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M_ASET_OB,
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M_BALIGN,
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M_BC1FL,
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M_BC1TL,
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@ -1366,6 +1381,8 @@ extern const int bfd_mips16_num_opcodes;
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#define MICROMIPSOP_SH_SEL 11
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#define MICROMIPSOP_MASK_OFFSET12 0xfff
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#define MICROMIPSOP_SH_OFFSET12 0
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#define MICROMIPSOP_MASK_3BITPOS 0x7
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#define MICROMIPSOP_SH_3BITPOS 21
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#define MICROMIPSOP_MASK_STYPE 0x1f
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#define MICROMIPSOP_SH_STYPE 16
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#define MICROMIPSOP_MASK_OFFSET10 0x3ff
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@ -1591,6 +1608,7 @@ extern const int bfd_mips16_num_opcodes;
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"<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
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">" shift amount between 32 and 63, stored after subtracting 32
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(MICROMIPSOP_*_SHAMT)
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"\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
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"|" 4-bit trap code (MICROMIPSOP_*_TRAP)
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"~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
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"a" 26-bit target address (MICROMIPSOP_*_TARGET)
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@ -1680,7 +1698,7 @@ extern const int bfd_mips16_num_opcodes;
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Characters used so far, for quick reference when adding more:
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"1234567890"
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"<>(),+.|~"
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"<>(),+.\|~"
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"ABCDEFGHI KLMN RST V "
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"abcd f hijklmnopqrstuvw yz"
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