Add IBM 370 support.
This commit is contained in:
Alan Modra
parent
01cf5d0f5d
commit
58dabf5040
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@ -1,3 +1,8 @@
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2000-02-23 Linas Vepstas <linas@linas.org>
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* config.sub: Add support for Linux/IBM 370.
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* configure.in: Likewise.
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2000-02-22 Nick Clifton <nickc@cygnus.com>
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* configure.in: Add mips-pe, sh-pe and arm-wince-pe targets.
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@ -1,3 +1,8 @@
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2000-02-23 Linas Vepstas <linas@linas.org>
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* mh-i370pic: New file.
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* mt-i370pic: New file.
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2000-02-22 Nick Clifton <nickc@cygnus.com>
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* config/mt-wince: new file: Makefile fragment for WinCE targets.
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@ -0,0 +1 @@
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PICFLAG=-fPIC
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@ -0,0 +1 @@
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PICFLAG_FOR_TARGET=-fPIC
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@ -288,6 +288,9 @@ if [ x${shared} = xyes ]; then
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i[3456]86-*-*)
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host_makefile_frag="${host_makefile_frag} config/mh-x86pic"
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;;
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i370-*-*)
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host_makefile_frag="${host_makefile_frag} config/mh-i370pic"
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;;
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sparc64-*-*)
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host_makefile_frag="${host_makefile_frag} config/mh-sparcpic"
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;;
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@ -1,7 +1,11 @@
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2000-02-23 Linas Vepstas <linas@linas.org>
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* dis-asm.h (print_insn_i370): Declare.
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2000-02-22 Chandra Chavva <cchavva@cygnus.com>
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* opcode/d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation cannot
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be combined in parallel with ADD/SUBppp.
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* opcode/d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation
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cannot be combined in parallel with ADD/SUBppp.
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Tue Feb 22 15:19:54 2000 Andrew Cagney <cagney@b1.cygnus.com>
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@ -157,6 +157,7 @@ extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*));
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extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*));
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@ -1,3 +1,7 @@
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2000-02-23 Linas Vepstas <linas@linas.org>
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* i370.h: New file.
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2000-02-22 Nick Clifton <nickc@cygnus.com>
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* common.h (ELF_ST_OTHER): Remove definition.
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@ -0,0 +1,46 @@
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/* i370 ELF support for BFD.
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Copyright (C) 1995, 2000 Free Software Foundation, Inc.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* This file holds definitions specific to the i370 ELF ABI. Note
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that most of this is not actually implemented by BFD. */
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#ifndef _ELF_I370_H
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#define _ELF_I370_H
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/* Processor specific section headers, sh_type field */
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#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \
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entries in this section \
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based on the address \
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specified in the associated \
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symbol table entry. */
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#define EF_I370_RELOCATABLE 0x00010000 /* i370 -mrelocatable flag */
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#define EF_I370_RELOCATABLE_LIB 0x00008000 /* i370 -mrelocatable-lib flag */
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/* Processor specific section flags, sh_flags field */
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#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \
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this section from executable \
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and shared objects that it \
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builds when those objects \
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are not to be furhter \
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relocated. */
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#endif /* _ELF_I370_H */
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@ -1,3 +1,7 @@
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2000-02-23 Linas Vepstas <linas@linas.org>
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* i370.h: New file.
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2000-02-22 Andrew Haley <aph@cygnus.com>
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* mips.h: (OPCODE_IS_MEMBER): Add comment.
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@ -0,0 +1,265 @@
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/* i370.h -- Header file for S/390 opcode table
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Copyright 1994, 95, 98, 99, 2000 Free Software Foundation, Inc.
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PowerPC version written by Ian Lance Taylor, Cygnus Support
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Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef I370_H
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#define I370_H
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/* The opcode table is an array of struct i370_opcode. */
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typedef union
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{
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unsigned int i[2];
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unsigned short s[4];
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unsigned char b[8];
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} i370_insn_t;
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struct i370_opcode
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{
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/* The opcode name. */
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const char *name;
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/* the length of the instruction */
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char len;
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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i370_insn_t opcode;
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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i370_insn_t mask;
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/* One bit flags for the opcode. These are used to indicate which
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specific processors support the instructions. The defined values
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are listed below. */
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unsigned long flags;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[8];
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};
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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instructions. */
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extern const struct i370_opcode i370_opcodes[];
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extern const int i370_num_opcodes;
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/* Values defined for the flags field of a struct i370_opcode. */
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/* Opcode is defined for the original 360 architecture. */
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#define I370_OPCODE_360 (0x01)
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/* Opcode is defined for the 370 architecture. */
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#define I370_OPCODE_370 (0x02)
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/* Opcode is defined for the 370-XA architecture. */
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#define I370_OPCODE_370_XA (0x04)
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/* Opcode is defined for the ESA/370 architecture. */
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#define I370_OPCODE_ESA370 (0x08)
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/* Opcode is defined for the ESA/390 architecture. */
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#define I370_OPCODE_ESA390 (0x10)
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/* Opcode is defined for the ESA/390 w/ BFP facility. */
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#define I370_OPCODE_ESA390_BF (0x20)
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/* Opcode is defined for the ESA/390 w/ branch & set authority facility. */
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#define I370_OPCODE_ESA390_BS (0x40)
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/* Opcode is defined for the ESA/390 w/ checksum facility. */
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#define I370_OPCODE_ESA390_CK (0x80)
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/* Opcode is defined for the ESA/390 w/ compare & move extended facility. */
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#define I370_OPCODE_ESA390_CM (0x100)
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/* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */
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#define I370_OPCODE_ESA390_FX (0x200)
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/* Opcode is defined for the ESA/390 w/ HFP facility. */
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#define I370_OPCODE_ESA390_HX (0x400)
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/* Opcode is defined for the ESA/390 w/ immediate & relative facility. */
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#define I370_OPCODE_ESA390_IR (0x800)
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/* Opcode is defined for the ESA/390 w/ move-inverse facility. */
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#define I370_OPCODE_ESA390_MI (0x1000)
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/* Opcode is defined for the ESA/390 w/ program-call-fast facility. */
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#define I370_OPCODE_ESA390_PC (0x2000)
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/* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */
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#define I370_OPCODE_ESA390_PL (0x4000)
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/* Opcode is defined for the ESA/390 w/ square-root facility. */
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#define I370_OPCODE_ESA390_QR (0x8000)
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/* Opcode is defined for the ESA/390 w/ resume-program facility. */
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#define I370_OPCODE_ESA390_RP (0x10000)
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/* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */
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#define I370_OPCODE_ESA390_SA (0x20000)
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/* Opcode is defined for the ESA/390 w/ subspace group facility. */
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#define I370_OPCODE_ESA390_SG (0x40000)
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/* Opcode is defined for the ESA/390 w/ string facility. */
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#define I370_OPCODE_ESA390_SR (0x80000)
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/* Opcode is defined for the ESA/390 w/ trap facility. */
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#define I370_OPCODE_ESA390_TR (0x100000)
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#define I370_OPCODE_ESA390_SUPERSET (0x1fffff)
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/* The operands table is an array of struct i370_operand. */
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struct i370_operand
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{
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/* The number of bits in the operand. */
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int bits;
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/* How far the operand is left shifted in the instruction. */
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int shift;
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If it is NULL, execute
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i |= (op & ((1 << o->bits) - 1)) << o->shift;
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(i is the instruction which we are filling in, o is a pointer to
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this structure, and op is the opcode value; this assumes twos
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complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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i370_insn_t (*insert) PARAMS ((i370_insn_t instruction, long op,
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const char **errmsg));
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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op = ((i) >> o->shift) & ((1 << o->bits) - 1);
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if ((o->flags & I370_OPERAND_SIGNED) != 0
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&& (op & (1 << (o->bits - 1))) != 0)
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op -= 1 << o->bits;
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(i is the instruction, o is a pointer to this structure, and op
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is the result; this assumes twos complement arithmetic).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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long (*extract) PARAMS ((i370_insn_t instruction, int *invalid));
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/* One bit syntax flags. */
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unsigned long flags;
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/* name -- handy for debugging, otherwise pointless */
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char * name;
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};
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/* Elements in the table are retrieved by indexing with values from
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the operands field of the i370_opcodes table. */
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extern const struct i370_operand i370_operands[];
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/* Values defined for the flags field of a struct i370_operand. */
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/* This operand should be wrapped in parentheses rather than
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separated from the previous by a comma. This is used for S, RS and
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SS form instructions which want their operands to look like
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reg,displacement(basereg) */
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#define I370_OPERAND_SBASE (0x01)
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/* This operand is a base register. It may or may not appear next
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to an index register, i.e. either of the two forms
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reg,displacement(basereg)
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reg,displacement(index,basereg) */
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#define I370_OPERAND_BASE (0x02)
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/* This pair of operands should be wrapped in parentheses rather than
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separated from the last by a comma. This is used for the RX form
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instructions which want their operands to look like
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reg,displacement(index,basereg) */
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#define I370_OPERAND_INDEX (0x04)
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/* This operand names a register. The disassembler uses this to print
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register names with a leading 'r'. */
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#define I370_OPERAND_GPR (0x08)
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/* This operand names a floating point register. The disassembler
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prints these with a leading 'f'. */
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#define I370_OPERAND_FPR (0x10)
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/* This operand is a displacement. */
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#define I370_OPERAND_RELATIVE (0x20)
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/* This operand is a length, such as that in SS form instructions. */
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#define I370_OPERAND_LENGTH (0x40)
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/* This operand is optional, and is zero if omitted. This is used for
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the optional B2 field in the shift-left, shift-right instructions. The
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assembler must count the number of operands remaining on the line,
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and the number of operands remaining for the opcode, and decide
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whether this operand is present or not. The disassembler should
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print this operand out only if it is not zero. */
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#define I370_OPERAND_OPTIONAL (0x80)
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/* Define some misc macros. We keep them with the operands table
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for simplicity. The macro table is an array of struct i370_macro. */
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struct i370_macro
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{
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/* The macro name. */
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const char *name;
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/* The number of operands the macro takes. */
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unsigned int operands;
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/* One bit flags for the opcode. These are used to indicate which
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specific processors support the instructions. The values are the
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same as those for the struct i370_opcode flags field. */
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unsigned long flags;
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/* A format string to turn the macro into a normal instruction.
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Each %N in the string is replaced with operand number N (zero
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based). */
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const char *format;
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};
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extern const struct i370_macro i370_macros[];
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extern const int i370_num_macros;
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#endif /* I370_H */
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