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include/opcode/ 

* mips.h: Remove documentation of "+D" and "+T".

opcodes/
	* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
	* micromips-opc.c (micromips_opcodes): Likewise.
	* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
	and "+T" handling.  Check for a "0" suffix when deciding whether to
	use coprocessor 0 names.  In that case, also check for ",H" selectors.

gas/
	* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
	(mips_ip): Remove "+D" and "+T" handling.

gas/testsuite/
	* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
	for LWC0 and SWC0.
This commit is contained in:
Richard Sandiford 2013-07-07 09:32:54 +00:00
parent ddbe02c418
commit 579ba5dd46
2 changed files with 6 additions and 7 deletions
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4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Remove documentation of "+D" and "+T".
2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.

9
include/opcode/mips.h
View File

@ -448,8 +448,6 @@ struct mips_opcode
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
see also "k" above
"+D" Combined destination register ("G") and sel ("H") for CP0 ops,
for pretty-printing in disassembly only.
Macro instructions:
"A" General 32 bit expression
@ -489,7 +487,6 @@ struct mips_opcode
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
MCU ASE usage:
"~" 12 bit offset (OP_*_OFFSET12)
@ -543,7 +540,7 @@ struct mips_opcode
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234"
"ABCDEFGHIJPQSTXZ"
"ABCEFGHIJPQSXZ"
"abcjpstxz"
*/
@ -1816,8 +1813,6 @@ extern const int bfd_mips16_num_opcodes;
"E" 5-bit target register (MICROMIPSOP_*_RT)
"G" 5-bit source register (MICROMIPSOP_*_RS)
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
"+D" combined source register ("G") and sel ("H") for CP0 ops,
for pretty-printing in disassembly only
Macro instructions:
"A" general 32 bit expression
@ -1859,7 +1854,7 @@ extern const int bfd_mips16_num_opcodes;
following), for quick reference when adding more:
"j"
""
"ABCDEFGHI"
"ABCEFGHI"
""
Extension character sequences used so far ("m" followed by the