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riscv: Map between ieeefp.h exception bits and RISC-V FCSR bits
If we had architecture-specific exception bits, we could just set them to match the processor, but instead ieeefp.h is shared by all targets so we need to map between the public values and the register contents. Signed-off-by: Keith Packard <keithp@keithp.com>
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@ -40,6 +40,40 @@ frm_fp_rnd (unsigned frm)
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}
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}
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static fp_except
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frm_fp_except (unsigned except)
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{
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fp_except fp = 0;
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if (except & (1 << 0))
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fp |= FP_X_IMP;
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if (except & (1 << 1))
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fp |= FP_X_UFL;
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if (except & (1 << 2))
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fp |= FP_X_OFL;
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if (except & (1 << 3))
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fp |= FP_X_DX;
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if (except & (1 << 4))
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fp |= FP_X_INV;
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return fp;
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}
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static unsigned
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frm_except(fp_except fp)
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{
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unsigned except = 0;
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if (fp & FP_X_IMP)
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except |= (1 << 0);
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if (fp & FP_X_UFL)
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except |= (1 << 1);
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if (fp & FP_X_OFL)
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except |= (1 << 2);
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if (fp & FP_X_DX)
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except |= (1 << 3);
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if (fp & FP_X_INV)
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except |= (1 << 4);
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return except;
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}
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#endif /* __riscv_flen */
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fp_except
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@ -63,7 +97,7 @@ fp_except
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fpgetsticky(void)
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{
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#ifdef __riscv_flen
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return frsr () & 0x1f;
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return frm_fp_except(frsr ());
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#else
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return 0;
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#endif /* __riscv_flen */
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@ -102,8 +136,8 @@ fpsetsticky(fp_except sticky)
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{
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#ifdef __riscv_flen
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unsigned fsr = frsr ();
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fssr (sticky & 0x1f | fsr & ~0x1f);
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return fsr & 0x1f;
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fssr (frm_except(sticky) | (fsr & ~0x1f));
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return frm_fp_except(fsr);
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#else
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return -1;
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#endif /* __riscv_flen */
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