* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP instructions. (INSN_DSP): New define for DSP ASE.
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@ -1,3 +1,14 @@
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2005-08-25 Chao-ying Fu <fu@mips.com>
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* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
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OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
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OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
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OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
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OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
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Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
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instructions.
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(INSN_DSP): New define for DSP ASE.
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2005-08-18 Alan Modra <amodra@bigpond.net.au>
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* a29k.h: Delete.
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@ -148,6 +148,28 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
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#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
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#define OP_SH_EXTMSBD 11
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/* MIPS DSP ASE */
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#define OP_SH_DSPACC 11
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#define OP_MASK_DSPACC 0x3
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#define OP_SH_DSPACC_S 21
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#define OP_MASK_DSPACC_S 0x3
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#define OP_SH_DSPSFT 20
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#define OP_MASK_DSPSFT 0x3f
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#define OP_SH_DSPSFT_7 19
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#define OP_MASK_DSPSFT_7 0x7f
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#define OP_SH_SA3 21
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#define OP_MASK_SA3 0x7
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#define OP_SH_SA4 21
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#define OP_MASK_SA4 0xf
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#define OP_SH_IMM8 16
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#define OP_MASK_IMM8 0xff
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#define OP_SH_IMM10 16
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#define OP_MASK_IMM10 0x3ff
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#define OP_SH_WRDSP 11
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#define OP_MASK_WRDSP 0x3f
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#define OP_SH_RDDSP 16
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#define OP_MASK_RDDSP 0x3f
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#define OP_OP_COP0 0x10
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#define OP_OP_COP1 0x11
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#define OP_OP_COP2 0x12
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@ -296,6 +318,19 @@ struct mips_opcode
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"Y" MDMX source register (OP_*_FS)
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"Z" MDMX source register (OP_*_FT)
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DSP ASE usage:
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"3" 3 bit unsigned immediate (OP_*_SA3)
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"4" 4 bit unsigned immediate (OP_*_SA4)
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"5" 8 bit unsigned immediate (OP_*_IMM8)
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"6" 5 bit unsigned immediate (OP_*_RS)
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"7" 2 bit dsp accumulator register (OP_*_DSPACC)
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"8" 6 bit unsigned immediate (OP_*_WRDSP)
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"9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
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"0" 6 bit signed immediate (OP_*_DSPSFT)
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":" 7 bit signed immediate (OP_*_DSPSFT_7)
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"'" 6 bit unsigned immediate (OP_*_RDDSP)
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"@" 10 bit signed immediate (OP_*_IMM10)
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Other:
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"()" parens surrounding optional value
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"," separates operands
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@ -303,7 +338,8 @@ struct mips_opcode
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"+" Start of extension sequence.
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Characters used so far, for quick reference when adding more:
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"%[]<>(),+"
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"34567890"
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"%[]<>(),+:'@"
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"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
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"abcdefhijklopqrstuvwxz"
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@ -413,6 +449,8 @@ struct mips_opcode
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/* Masks used for MIPS-defined ASEs. */
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#define INSN_ASE_MASK 0x0000f000
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/* DSP ASE */
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#define INSN_DSP 0x00001000
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/* MIPS 16 ASE */
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#define INSN_MIPS16 0x00002000
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/* MIPS-3D ASE */
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