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libgloss/or1k: Correct the IMMU SXE and UXE flags

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These have been defined incorrectly, as per specification and CPU
implementations SXE is bit 6 and UXE is bit 7.  This was noticed when
tracking down our test suite mmu test failures.

 Test Suite: https://github.com/openrisc/or1k-tests/blob/master/native/or1k/or1k-mmu.c#L68-L72
 Spec: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.3-rev1.pdf

See section 8.4.8 Instruction Translation Lookaside Buffer Way y Translate
Registers where these are defined.

Signed-off-by: Stafford Horne <shorne@gmail.com>
This commit is contained in:
Stafford Horne 2021-07-02 06:24:57 +09:00 committed by Jeff Johnston
parent 5c9c31c52b
commit 43999b660f
1 changed files with 10 additions and 10 deletions
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20
libgloss/or1k/include/or1k-sprs.h
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@ -1797,17 +1797,17 @@
#define OR1K_SPR_IMMU_ITLBW_TR_D_GET(X) (((X) >> 5) & 0x1)
#define OR1K_SPR_IMMU_ITLBW_TR_D_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffdf)) | ((!!(Y)) << 5))
/* User Execute Enable */
#define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 6
#define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK 0x00000040
#define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 6) & 0x1)
#define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6))
/* Supervisor Execute Enable */
#define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 7
#define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK 0x00000080
#define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 7) & 0x1)
#define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7))
#define OR1K_SPR_IMMU_ITLBW_TR_SXE_OFFSET 6
#define OR1K_SPR_IMMU_ITLBW_TR_SXE_MASK 0x00000040
#define OR1K_SPR_IMMU_ITLBW_TR_SXE_GET(X) (((X) >> 6) & 0x1)
#define OR1K_SPR_IMMU_ITLBW_TR_SXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffffbf)) | ((!!(Y)) << 6))
/* User Execute Enable */
#define OR1K_SPR_IMMU_ITLBW_TR_UXE_OFFSET 7
#define OR1K_SPR_IMMU_ITLBW_TR_UXE_MASK 0x00000080
#define OR1K_SPR_IMMU_ITLBW_TR_UXE_GET(X) (((X) >> 7) & 0x1)
#define OR1K_SPR_IMMU_ITLBW_TR_UXE_SET(X, Y) (((X) & OR1K_UNSIGNED(0xffffff7f)) | ((!!(Y)) << 7))
/* Physical Page Number */
#define OR1K_SPR_IMMU_ITLBW_TR_PPN_LSB 13