Support R_SPARC_WDISP10 and R_SPARC_H34.
include/ * elf/sparc.h (R_SPARC_WDISP10): New reloc. * opcode/sparc.h: Define '=' as generating R_SPARC_WDISP10. opcodes/ * sparc-dis.c (X_DISP10): Define. (print_insn_sparc): Handle '='. bfd/ * reloc.c (BFD_RELOC_SPARC_H34, BFD_RELOC_SPARC_SIZE32, BFD_RELOC_SPARC_SIZE64, BFD_RELOC_SPARC_WDISP10): New relocs. * libbfd.h: Regenerate. * bfd-in2.h: Likewise. * elfxx-sparc.c (sparc_elf_wdisp10_reloc): New function. (_bfd_sparc_elf_howto_table): Add entries for R_SPARC_H34, R_SPARC_SIZE32, R_SPARC_64, and R_SPARC_WDISP10. (_bfd_sparc_elf_reloc_type_lookup): Handle new relocs. (_bfd_sparc_elf_check_relocs): Likewise. (_bfd_sparc_elf_gc_sweep_hook): Likewise. (_bfd_sparc_elf_relocate_section): Likewise. gas/ * config/tc-sparc.c (sparc_ip): Handle '=', "%h34", "%l34", and BFD_RELOC_SPARC_H34. (md_apply_fix): Handle BFD_RELOC_SPARC_WDISP10 and BFD_RELOC_SPARC_H34. (tc_gen_reloc): Likewise. gas/testsuite/ * gas/sparc/reloc64.s: Add abs34 code model tests. * gas/sparc/reloc64.d: Update. elfcpp/ * sparc.h (R_SPARC_WDISP10): New relocation. gold/ * sparc.cc (Reloc::wdisp10): New relocation method. (Reloc::h34): Likewise. (Target_sparc::Scan::check_non_pic): Handle R_SPARC_H34. (Target_sparc::Scan::get_reference_flags): Handle R_SPARC_H34 and R_SPARC_WDISP10. (Target_sparc::Scan::local): Likewise. (Target_sparc::Scan::global): Likewise. (Target_sparc::Relocate::relocate): Likewise.
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0c91015243
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@ -1,3 +1,8 @@
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2012-04-12 David S. Miller <davem@davemloft.net>
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* elf/sparc.h (R_SPARC_WDISP10): New reloc.
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* opcode/sparc.h: Define '=' as generating R_SPARC_WDISP10.
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2012-04-10 Tristan Gingold <gingold@adacore.com>
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* splay-tree.h: Conditionnaly includes stdint.h and inttypes.h
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@ -162,6 +162,7 @@ START_RELOC_NUMBERS (elf_sparc_reloc_type)
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RELOC_NUMBER (R_SPARC_H34, 85)
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RELOC_NUMBER (R_SPARC_SIZE32, 86)
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RELOC_NUMBER (R_SPARC_SIZE64, 87)
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RELOC_NUMBER (R_SPARC_WDISP10, 88)
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EMPTY_RELOC (R_SPARC_max_std)
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@ -208,7 +208,8 @@ typedef struct sparc_opcode
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0 32/64 bit immediate for set or setx (v9) insns
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_ Ancillary state register in rd (v9a)
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/ Ancillary state register in rs1 (v9a)
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( entire floating point state register (%efsr). */
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( entire floating point state register (%efsr)
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= 2+8 bit PC relative immediate. (v9) */
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#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
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#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
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