* configure.in: Add ms1 case.

* configure: Regenerate.
	* ms1/16-002.ld: New.
	* ms1/16-003.ld: New.
	* ms1/64-001.ld: New.
	* ms1/access.c: New.
	* ms1/chmod.c: New.
	* ms1/close.c: New.
	* ms1/configure: New.
	* ms1/configure.in: New.
	* ms1/crt0-16-002.S: New.
	* ms1/crt0-16-003.S: New.
	* ms1/crt0-64-001.S: New.
	* ms1/crt0.S: New.
	* ms1/exit-16-002.c: New.
	* ms1/exit-16-003.c: New.
	* ms1/exit-64-001.c: New.
	* ms1/exit.c: New.
	* ms1/fstat.c: New.
	* ms1/getpid.c: New.
	* ms1/gettime.c: New.
	* ms1/isatty.c: New.
	* ms1/kill.c: New.
	* ms1/lseek.c: New.
	* ms1/Makefile.in: New.
	* ms1/open.c: New.
	* ms1/read.c: New.
	* ms1/sbrk.c: New.
	* ms1/startup-16-002.S: New.
	* ms1/startup-16-003.S: New.
	* ms1/startup-64-001.S: New.
	* ms1/stat.c: New.
	* ms1/time.c: New.
	* ms1/times.c: New.
	* ms1/trap.h: New.
	* ms1/trap.S: New.
	* ms1/unlink.c: New.
	* ms1/utime.c: New.
	* ms1/write.c: New.
This commit is contained in:
Aldy Hernandez 2005-07-06 12:58:12 +00:00
parent 27eb5dbc70
commit 3f4df6211e
40 changed files with 4861 additions and 0 deletions

View File

@ -1,3 +1,45 @@
2005-06-24 Aldy Hernandez <aldyh@redhat.com>
* configure.in: Add ms1 case.
* configure: Regenerate.
* ms1/16-002.ld: New.
* ms1/16-003.ld: New.
* ms1/64-001.ld: New.
* ms1/access.c: New.
* ms1/chmod.c: New.
* ms1/close.c: New.
* ms1/configure: New.
* ms1/configure.in: New.
* ms1/crt0-16-002.S: New.
* ms1/crt0-16-003.S: New.
* ms1/crt0-64-001.S: New.
* ms1/crt0.S: New.
* ms1/exit-16-002.c: New.
* ms1/exit-16-003.c: New.
* ms1/exit-64-001.c: New.
* ms1/exit.c: New.
* ms1/fstat.c: New.
* ms1/getpid.c: New.
* ms1/gettime.c: New.
* ms1/isatty.c: New.
* ms1/kill.c: New.
* ms1/lseek.c: New.
* ms1/Makefile.in: New.
* ms1/open.c: New.
* ms1/read.c: New.
* ms1/sbrk.c: New.
* ms1/startup-16-002.S: New.
* ms1/startup-16-003.S: New.
* ms1/startup-64-001.S: New.
* ms1/stat.c: New.
* ms1/time.c: New.
* ms1/times.c: New.
* ms1/trap.h: New.
* ms1/trap.S: New.
* ms1/unlink.c: New.
* ms1/utime.c: New.
* ms1/write.c: New.
2005-05-19 Corinna Vinschen <vinschen@redhat.com>
* arm/elf-redboot.ld, iq2000/sim.ld, m68hc11/sim-valid-m68hc11.ld,

2
libgloss/configure vendored
View File

@ -792,6 +792,8 @@ case "${target}" in
mcore-*-*)
configdirs="${configdirs} mcore testsuite"
;;
ms1-*-*)
configdirs="${configdirs} ms1 testsuite";;
xstormy16-*-*)
configdirs="${configdirs} xstormy16 testsuite"
;;

View File

@ -103,6 +103,8 @@ case "${target}" in
mcore-*-*)
configdirs="${configdirs} mcore testsuite"
;;
ms1-*-*)
configdirs="${configdirs} ms1 testsuite";;
xstormy16-*-*)
configdirs="${configdirs} xstormy16 testsuite"
;;

248
libgloss/ms1/16-002.ld Normal file
View File

@ -0,0 +1,248 @@
OUTPUT_FORMAT("elf32-ms1", "elf32-ms1", "elf32-ms1")
OUTPUT_ARCH(ms1)
ENTRY(__boot_start)
SEARCH_DIR(/usr/local/mrisc1-elf/lib)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
MEMORY
{
ram (rwx) : ORIGIN = 0x0, LENGTH = 128K
frame-buffer (w) : ORIGIN = 0xde0000, LENGTH = 40K
ports (w) : ORIGIN = 0xfff000, LENGTH = 4K
dma-ram (w) : ORIGIN = 0x1000000, LENGTH = 16M-4K
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = 0x0;
PROVIDE(__executable_start = 0x0);
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro*) }
.rela.data.rel.ro : { *(.rela.data.rel.ro*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rel.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.startup : { *startup-16-002.o(.startup) } >ram =0
. = 0x40 ;
.init : { KEEP (*(.init)) } >ram =0
.plt : { *(.plt) } >ram
.text :
{
*startup-16-002.o(.text)
*(.text .stub .text.* .gnu.linkonce.t.*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} >ram =0
.fini : { KEEP (*(.fini)) } >ram =0
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >ram
.rodata1 : { *(.rodata1) } >ram
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) } >ram
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram
.eh_frame_hdr : { *(.eh_frame_hdr) } >ram
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >ram
.gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >ram
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(256) + (. & (256 - 1));
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >ram
.gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >ram
/* Thread Local Storage sections */
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >ram
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
be empty, which isn't pretty. */
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : { *(.preinit_array) } >ram
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : { *(.init_array) } >ram
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : { *(.fini_array) } >ram
PROVIDE (__fini_array_end = .);
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >ram
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >ram
.jcr : { KEEP (*(.jcr)) } >ram
.data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >ram
.dynamic : { *(.dynamic) } >ram
/* DJK - Re-align the data section from the read-only section. */
. = ALIGN(16) + (. & (16 - 1));
PROVIDE (_data = .);
.data :
{
*(.data .data.* .gnu.linkonce.d.*)
SORT(CONSTRUCTORS)
} >ram
.data1 : { *(.data1) } >ram
.got : { *(.got.plt) *(.got) } >ram
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata : { *(.sdata .sdata.* .gnu.linkonce.s.*) } >ram
_edata = .;
PROVIDE ( edata = . ) ;
.sbss :
{
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
} >ram
.bss :
{
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
} >ram
. = ALIGN(32 / 8);
__bss_start = ADDR ( .sbss ) ;
__bss_end = __bss_start + SIZEOF ( .sbss ) + SIZEOF ( .bss ) - 4 ;
_end = .;
PROVIDE (end = .);
/* DJK - Initialized frame buffer data is copied from RAM to FB. */
.auxbss : AT (ADDR(.bss) + SIZEOF(.bss)) { *(.auxbss) } >frame-buffer
.auxdata : AT (LOADADDR(.auxbss) + SIZEOF(.auxbss))
{
*(.auxdata)
} >frame-buffer
_fbbss_start = ADDR ( .auxbss );
_fbbss_end = _fbbss_start + SIZEOF ( .auxbss ) - 4;
_fbdata_start = LOADADDR ( .auxdata );
_fbdata_end = _fbdata_start + SIZEOF ( .auxdata ) ;
_fbdata_vma = ADDR ( .auxdata );
PROVIDE (__FRAME_BUFFER_START = ADDR(.auxbss) );
PROVIDE (__FRAME_BUFFER_SIZE = 0xa000);
PROVIDE (__FRAME_BUFFER_END = __FRAME_BUFFER_START + __FRAME_BUFFER_SIZE);
.dma : { _dma_start = .; *(.dma) _dma_end = .; } >dma-ram
.internal_io (NOLOAD) : { *(.internal_io) } >ports
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* In a multi-core environment, each core is given its own stack space
equal to __stack_size. */
PROVIDE (__stack = 0x1fff0);
PROVIDE (__stack_size = 0x800);
.stack (DEFINED(__stack) ? __stack : 0x007ffff0) :
{
__stack = .;
*(.stack)
LONG(0xdeaddead)
}
/DISCARD/ : { *(.note.GNU-stack) }
}

258
libgloss/ms1/16-003.ld Normal file
View File

@ -0,0 +1,258 @@
OUTPUT_FORMAT("elf32-ms1", "elf32-ms1", "elf32-ms1")
OUTPUT_ARCH(ms1)
ENTRY(__boot_start)
SEARCH_DIR(/usr/local/mrisc1-elf/lib)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
MEMORY
{
ram (rwx) : ORIGIN = 0x0, LENGTH = 608K
frame-buffer (w) : ORIGIN = 0xff000000, LENGTH = 80K
dma-ram (w) : ORIGIN = 0x1000000, LENGTH = 16M-4K
ports (w) : ORIGIN = 0xfffff000, LENGTH = 4K
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = 0x0;
PROVIDE(__executable_start = 0x0);
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro*) }
.rela.data.rel.ro : { *(.rela.data.rel.ro*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rel.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.startup : { *startup-16-003.o(.startup) } >ram =0
. = 0x40;
.init : { KEEP (*(.init)) } >ram =0
.plt : { *(.plt) } >ram
.text :
{
*startup-16-003.o(.text);
*(.text .stub .text.* .gnu.linkonce.t.*)
KEEP (*(.text.*personality*))
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} >ram =0
.fini : { KEEP (*(.fini)) } >ram =0
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >ram
.rodata1 : { *(.rodata1) } >ram
.sdata2 : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) } >ram
.sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >ram
.eh_frame_hdr : { *(.eh_frame_hdr) } >ram
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >ram
.gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >ram
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(256) + (. & (256 - 1));
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >ram
.gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >ram
/* Thread Local Storage sections */
.tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >ram
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
be empty, which isn't pretty. */
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : { *(.preinit_array) } >ram
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : { *(.init_array) } >ram
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : { *(.fini_array) } >ram
PROVIDE (__fini_array_end = .);
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >ram
.dtors :
{
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >ram
.jcr : { KEEP (*(.jcr)) } >ram
.data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } >ram
.dynamic : { *(.dynamic) } >ram
/* DJK - Re-align the data section from the read-only section. */
. = ALIGN(16) + (. & (16 - 1));
PROVIDE (_data = .);
.data :
{
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
} >ram
.data1 : { *(.data1) } >ram
.got : { *(.got.plt) *(.got) } >ram
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata : { *(.sdata .sdata.* .gnu.linkonce.s.*) } >ram
_edata = .;
PROVIDE ( edata = . );
.sbss :
{
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
} >ram
.bss :
{
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
} >ram
. = ALIGN(32 / 8);
__bss_start = ADDR ( .sbss ) ;
__bss_end = __bss_start + SIZEOF ( .sbss ) + SIZEOF ( .bss ) - 4 ;
_end = .;
PROVIDE (end = .);
/* DJK - Initialized frame buffer data is copied from RAM to FB. */
.auxbss : AT (ADDR(.bss) + SIZEOF(.bss)) { *(.auxbss) } >frame-buffer
.auxdata : AT (LOADADDR(.auxbss) + SIZEOF(.auxbss))
{
*(.auxdata.bank0)
. = ALIGN(0x4000);
*(.auxdata.bank1)
. = ALIGN(0x4000);
*(.auxdata.bank2)
. = ALIGN(0x4000);
*(.auxdata.bank3)
. = ALIGN(0x4000);
*(.auxdata.bank4)
*(.auxdata)
} >frame-buffer
_fbbss_start = ADDR ( .auxbss );
_fbbss_end = _fbbss_start + SIZEOF ( .auxbss ) - 4;
_fbdata_start = LOADADDR ( .auxdata );
_fbdata_end = _fbdata_start + SIZEOF ( .auxdata ) ;
_fbdata_vma = ADDR ( .auxdata );
PROVIDE (__FRAME_BUFFER_START = ADDR(.auxbss) );
PROVIDE (__FRAME_BUFFER_SIZE = 0x14000);
PROVIDE (__FRAME_BUFFER_END = __FRAME_BUFFER_START + __FRAME_BUFFER_SIZE);
.dma : { _dma_start = .; *(.dma) _dma_end = .; } >dma-ram
.internal_io (NOLOAD) : { *(.internal_io) } >ports
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* In a multi-core environment, each core is given its own stack space
equal to __stack_size, growing downwards. */
PROVIDE (__stack = 0x97ff0);
PROVIDE (__stack_size = 0x800);
.stack (DEFINED(__stack) ? __stack : 0x007ffff0) :
{
__stack = .;
*(.stack)
LONG(0xdeaddead)
}
/DISCARD/ : { *(.note.GNU-stack) }
}

282
libgloss/ms1/64-001.ld Normal file
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@ -0,0 +1,282 @@
OUTPUT_FORMAT("elf32-ms1", "elf32-ms1", "elf32-ms1")
OUTPUT_ARCH(ms1)
ENTRY(__boot_start)
SEARCH_DIR(/usr/local/mrisc1-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
MEMORY
{
rom (rx) : ORIGIN = 0x000000, LENGTH = 8M
frame-buffer (w) : ORIGIN = 0x800000, LENGTH = 64K
ram (w) : ORIGIN = 0xc00000, LENGTH = 4M
dma-ram (w) : ORIGIN = 0x1000000, LENGTH = 16M
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
PROVIDE (__executable_start = 0x0); . = 0x0;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.gnu.version : { *(.gnu.version) }
.gnu.version_d : { *(.gnu.version_d) }
.gnu.version_r : { *(.gnu.version_r) }
.rel.init : { *(.rel.init) }
.rela.init : { *(.rela.init) }
.rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
.rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
.rel.fini : { *(.rel.fini) }
.rela.fini : { *(.rela.fini) }
.rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
.rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
.rel.data.rel.ro : { *(.rel.data.rel.ro*) }
.rela.data.rel.ro : { *(.rel.data.rel.ro*) }
.rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
.rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
.rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
.rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
.rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
.rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
.rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
.rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
.rela.sbss : { *(.rela.sbss .rela.sbss.* .rel.gnu.linkonce.sb.*) }
.rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
.rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
.rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
.rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
.rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
.rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.startup : { *startup-64-001.o(.startup) } >rom =0
.init : { KEEP (*(.init)) } >rom =0
.plt : { *(.plt) } >rom
.text :
{
*startup-64-001.o(.text)
*(.text .stub .text.* .gnu.linkonce.t.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
} >rom =0
.fini :
{
KEEP (*(.fini))
} >rom =0
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >rom
.rodata1 : { *(.rodata1) } >rom
/* Data starting here needs to be copied from ROM to the frame buffer. */
/* Section .sdata2 is used as the beginning marker of the frame buffer
address as well as the start of the data that needs to be copied. */
.sdata2 : AT (ADDR(.rodata1) + SIZEOF(.rodata1))
{ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) } >frame-buffer
.sbss2 : AT (LOADADDR(.sdata2) + SIZEOF(.sdata2))
{ *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >frame-buffer
.eh_frame_hdr : AT (LOADADDR(.sbss2) + SIZEOF(.sbss2))
{ *(.eh_frame_hdr) } >frame-buffer
.eh_frame : AT (LOADADDR(.eh_frame_hdr) + SIZEOF(.eh_frame_hdr))
ONLY_IF_RO { KEEP (*(.eh_frame)) } >frame-buffer
.gcc_except_table : AT (LOADADDR(.eh_frame) + SIZEOF(.eh_frame))
ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >frame-buffer
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = ALIGN(256) + (. & (256 - 1));
/* Exception handling */
.eh_frame : AT (LOADADDR(.eh_frame_hdr) + SIZEOF(.eh_frame_hdr))
ONLY_IF_RW { KEEP (*(.eh_frame)) } >frame-buffer
.gcc_except_table : AT (LOADADDR(.eh_frame) + SIZEOF(.eh_frame))
ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } >frame-buffer
/* Thread Local Storage sections */
.tdata : AT (LOADADDR(.gcc_except_table) + SIZEOF(.gcc_except_table))
{ *(.tdata .tdata.* .gnu.linkonce.td.*) } >frame-buffer
.tbss : AT (LOADADDR(.tdata) + SIZEOF(.tdata))
{ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >frame-buffer
/* Ensure the __preinit_array_start label is properly aligned. We
could instead move the label definition inside the section, but
the linker would then create the section even if it turns out to
be empty, which isn't pretty. */
. = ALIGN(32 / 8);
PROVIDE (__preinit_array_start = .);
.preinit_array : AT (LOADADDR(.tbss) + SIZEOF(.tbss))
{ *(.preinit_array) } >frame-buffer
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : AT (LOADADDR(.preinit_array) + SIZEOF(.preinit_array))
{ *(.init_array) } >frame-buffer
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : AT (LOADADDR(.init_array) + SIZEOF(.init_array))
{ *(.fini_array) } >frame-buffer
PROVIDE (__fini_array_end = .);
.ctors : AT (LOADADDR(.fini_array) + SIZEOF(.fini_array))
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin*.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >frame-buffer
.dtors : AT (LOADADDR(.ctors) + SIZEOF(.ctors))
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >frame-buffer
.jcr : AT (LOADADDR(.dtors) + SIZEOF(.dtors))
{ KEEP (*(.jcr)) } >frame-buffer
.data.rel.ro : AT (LOADADDR(.jcr) + SIZEOF(.jcr))
{ *(.data.rel.ro.local) *(.data.rel.ro*) } >frame-buffer
.dynamic : AT (LOADADDR(.data.rel.ro) + SIZEOF(.data.rel.ro))
{ *(.dynamic) } >frame-buffer
/* DJK - Re-align the data section from the read-only section. */
. = ALIGN(16) + (. & (16 - 1));
PROVIDE (_data = .);
.data : AT (LOADADDR(.dynamic) + SIZEOF(.dynamic))
{
*(.data .data.* .gnu.linkonce.d.*)
KEEP (*(.gnu.linkonce.d.*personality*))
SORT(CONSTRUCTORS)
} >frame-buffer
.data1 : AT (LOADADDR(.data) + SIZEOF(.data))
{ *(.data1) } >frame-buffer
.got : AT (LOADADDR(.data1) + SIZEOF(.data1))
{ *(.got.plt) *(.got) }
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata : AT (LOADADDR(.got) + SIZEOF(.got))
{ *(.sdata .sdata.* .gnu.linkonce.s.*) } >frame-buffer
_edata = .;
PROVIDE ( edata = . ) ;
_fbdata_start = LOADADDR(.sdata2) ;
_fbdata_end = LOADADDR(.sdata) + SIZEOF(.sdata) - 4 ;
PROVIDE (__FRAME_BUFFER_START = ADDR(.sdata2));
PROVIDE (__FRAME_BUFFER_SIZE = 0x10000);
PROVIDE (__FRAME_BUFFER_END = __FRAME_BUFFER_START + __FRAME_BUFFER_SIZE);
.sbss : AT (LOADADDR(.sdata) + SIZEOF(.sdata))
{
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
} >frame-buffer
.bss : AT (LOADADDR(.sbss) + SIZEOF(.sbss))
{
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
} >frame-buffer
. = ALIGN(32 / 8);
__bss_start = ADDR(.sbss) ;
__bss_end = __bss_start + SIZEOF(.sbss) + SIZEOF(.bss) - 4 ;
_end = .;
PROVIDE (end = .);
PROVIDE ( _extdata_start = ADDR(.bss) + SIZEOF(.bss));
.extdata : AT ( LOADADDR(.bss) + SIZEOF(.bss))
{
*(.extdata)
} >ram
PROVIDE (_extdata_end = _extdata_start + SIZEOF(.extdata) - 4 );
.extbss : AT ( LOADADDR(.extdata) + SIZEOF(.extdata))
{
_extbss_start = .;
*(.extbss);
. = ALIGN(4);
_extbss_end = .;
} >ram
. = ALIGN(4);
PROVIDE (__EXTERNAL_MEMORY_START = 0xc00000);
.dma :
{
_dma_start = .;
*(.dma)
_dma_end = .;
} >dma-ram
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
PROVIDE (__stack = 0x80fff0);
.stack (DEFINED(__stack) ? __stack : 0x7FFFF0) :
{
__stack = .;
*(.stack)
LONG(0xdeaddead)
}
/DISCARD/ : { *(.note.GNU-stack) }
}

127
libgloss/ms1/Makefile.in Normal file
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# Copyright (c) 2001 Red Hat, Inc.
#
# The authors hereby grant permission to use, copy, modify, distribute,
# and license this software and its documentation for any purpose, provided
# that existing copyright notices are retained in all copies and that this
# notice is included verbatim in any distributions. No written agreement,
# license, or royalty fee is required for any of the authorized uses.
# Modifications to this software may be copyrighted by their authors
# and need not follow the licensing terms described here, provided that
# the new terms are clearly indicated on the first page of each file where
# they apply.
# Makefile for libgloss/ms1. This is the board support for the Morpho ms1.
VPATH = @srcdir@ @srcdir@/..
srcdir = @srcdir@
objdir = .
srcroot = $(srcdir)/../..
objroot = $(objdir)/../..
prefix = @prefix@
exec_prefix = @exec_prefix@
host_alias = @host_alias@
target_alias = @target_alias@
bindir = @bindir@
libdir = @libdir@
tooldir = $(exec_prefix)/$(target_alias)
# Multilib support variables.
# TOP is used instead of MULTI{BUILD,SRC}TOP.
MULTIDIRS =
MULTISUBDIR =
MULTIDO = true
MULTICLEAN = true
INSTALL = @INSTALL@
INSTALL_PROGRAM = @INSTALL_PROGRAM@
INSTALL_DATA = @INSTALL_DATA@
SHELL = /bin/sh
CC = @CC@
AS = @AS@
AR = @AR@
LD = @LD@
RANLIB = @RANLIB@
AR_FLAGS = rc
OBJDUMP = `if [ -f ${objroot}/../binutils/objdump ] ; \
then echo ${objroot}/../binutils/objdump ; \
else t='$(program_transform_name)'; echo objdump | sed -e $$t ; fi`
OBJCOPY = `if [ -f ${objroot}/../binutils/objcopy ] ; \
then echo ${objroot}/../binutils/objcopy ; \
else t='$(program_transform_name)'; echo objcopy | sed -e $$t ; fi`
SCRIPTS = 16-002.ld 16-003.ld 64-001.ld
CRT0 = crt0.o crt0-64-001.o crt0-16-002.o crt0-16-003.o \
startup-64-001.o startup-16-002.o startup-16-003.o \
exit.o exit-64-001.o exit-16-002.o exit-16-003.o
SIM_BSP = libsim.a
SIM_OBJS = access.o chmod.o close.o \
fstat.o getpid.o gettime.o isatty.o kill.o lseek.o open.o \
read.o sbrk.o stat.o time.o times.o trap.o unlink.o utime.o write.o
#### Host specific Makefile fragment comes in here.
@host_makefile_frag@
all: $(CRT0) $(SIM_BSP)
$(SIM_BSP): $(SIM_OBJS)
$(AR) $(ARFLAGS) $@ $?
$(RANLIB) $@
access.o: $(srcdir)/access.c
chmod.o: $(srcdir)/chmod.c
close.o: $(srcdir)/close.c
fstat.o: $(srcdir)/fstat.c
getpid.o: $(srcdir)/getpid.c
gettime.o: $(srcdir)/gettime.c
isatty.o: $(srcdir)/isatty.c
kill.o: $(srcdir)/kill.c
lseek.o: $(srcdir)/lseek.c
open.o: $(srcdir)/open.c
read.o: $(srcdir)/read.c
sbrk.o: $(srcdir)/sbrk.c
stat.o: $(srcdir)/stat.c
time.o: $(srcdir)/time.c
times.o: $(srcdir)/times.c
unlink.o: $(srcdir)/unlink.c
utime.o: $(srcdir)/utime.c
write.o: $(srcdir)/write.c
crt0.o: $(srcdir)/crt0.S
crt0-16-002.o: $(srcdir)/crt0-16-002.S
crt0-16-003.o: $(srcdir)/crt0-16-003.S
crt0-64-001.o: $(srcdir)/crt0-64-001.S
trap.o: $(srcdir)/trap.S
install: $($(CPU)_INSTALL)
for c in $(CRT0); do \
$(INSTALL_DATA) $$c $(tooldir)/lib${MULTISUBDIR}/$$c ; \
done;
$(INSTALL_DATA) $(SIM_BSP) $(tooldir)/lib${MULTISUBDIR}/$(SIM_BSP)
for c in $(SCRIPTS); do \
$(INSTALL_DATA) $(srcdir)/$$c $(tooldir)/lib/$$c ; \
done;
clean mostlyclean:
rm -f *.o *.a
distclean maintainer-clean realclean: clean
rm -f Makefile config.cache config.log config.status
.PHONY: info dvi doc install-info clean-info
info doc dvi:
install-info:
clean-info:
Makefile: Makefile.in config.status @host_makefile_frag_path@
$(SHELL) config.status
config.status: configure
$(SHELL) config.status --recheck

34
libgloss/ms1/access.c Normal file
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@ -0,0 +1,34 @@
/* This is file ACCESS.C */
/*
** Copyright (C) 1993 DJ Delorie, 24 Kirsten Ave, Rochester NH 03867-2954
**
** This file is distributed under the terms listed in the document
** "copying.dj", available from DJ Delorie at the address above.
** A copy of "copying.dj" should accompany this file; if not, a copy
** should be available from where this file was obtained. This file
** may not be distributed without a verbatim copy of "copying.dj".
**
** This file is distributed WITHOUT ANY WARRANTY; without even the implied
** warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*/
#include <fcntl.h>
#include <sys/stat.h>
#include <unistd.h>
int access(const char *fn, int flags)
{
struct stat s;
if (stat(fn, &s))
return -1;
if (s.st_mode & S_IFDIR)
return 0;
if (flags & W_OK)
{
if (s.st_mode & S_IWRITE)
return 0;
return -1;
}
return 0;
}

11
libgloss/ms1/chmod.c Normal file
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@ -0,0 +1,11 @@
#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
int
chmod (const char *path, mode_t mode)
{
return TRAP0 (SYS_chmod, path, mode, 0);
}

11
libgloss/ms1/close.c Normal file
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@ -0,0 +1,11 @@
#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
int
close (int file)
{
return TRAP0 (SYS_close, file, 0, 0);
}

1204
libgloss/ms1/configure vendored Executable file

File diff suppressed because it is too large Load Diff

90
libgloss/ms1/configure.in Normal file
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dnl Process this file with autoconf to produce a configure script.
AC_PREREQ(2.5)dnl
AC_INIT(crt0.S)
if test "${enable_shared}" = "yes" ; then
echo "Shared libraries not supported for cross compiling, ignored"
fi
if test "$srcdir" = "." ; then
if test "${with_target_subdir}" != "." ; then
libgloss_topdir="${srcdir}/${with_multisrctop}../../.."
else
libgloss_topdir="${srcdir}/${with_multisrctop}../.."
fi
else
libgloss_topdir="${srcdir}/../.."
fi
AC_CONFIG_AUX_DIR($libgloss_topdir)
AC_CANONICAL_SYSTEM
AC_ARG_PROGRAM
AC_PROG_INSTALL
# FIXME: We temporarily define our own version of AC_PROG_CC. This is
# copied from autoconf 2.12, but does not call AC_PROG_CC_WORKS. We
# are probably using a cross compiler, which will not be able to fully
# link an executable. This should really be fixed in autoconf
# itself.
AC_DEFUN(LIB_AC_PROG_CC,
[AC_BEFORE([$0], [AC_PROG_CPP])dnl
AC_CHECK_PROG(CC, gcc, gcc)
if test -z "$CC"; then
AC_CHECK_PROG(CC, cc, cc, , , /usr/ucb/cc)
test -z "$CC" && AC_MSG_ERROR([no acceptable cc found in \$PATH])
fi
AC_PROG_CC_GNU
if test $ac_cv_prog_gcc = yes; then
GCC=yes
dnl Check whether -g works, even if CFLAGS is set, in case the package
dnl plays around with CFLAGS (such as to build both debugging and
dnl normal versions of a library), tasteless as that idea is.
ac_test_CFLAGS="${CFLAGS+set}"
ac_save_CFLAGS="$CFLAGS"
CFLAGS=
AC_PROG_CC_G
if test "$ac_test_CFLAGS" = set; then
CFLAGS="$ac_save_CFLAGS"
elif test $ac_cv_prog_cc_g = yes; then
CFLAGS="-g -O2"
else
CFLAGS="-O2"
fi
else
GCC=
test "${CFLAGS+set}" = set || CFLAGS="-g"
fi
])
LIB_AC_PROG_CC
AS=${AS-as}
AC_SUBST(AS)
AR=${AR-ar}
AC_SUBST(AR)
LD=${LD-ld}
AC_SUBST(LD)
AC_PROG_RANLIB
host_makefile_frag=${srcdir}/../config/default.mh
dnl We have to assign the same value to other variables because autoconf
dnl doesn't provide a mechanism to substitute a replacement keyword with
dnl arbitrary data or pathnames.
dnl
host_makefile_frag_path=$host_makefile_frag
AC_SUBST(host_makefile_frag_path)
AC_SUBST_FILE(host_makefile_frag)
AC_OUTPUT(Makefile,
. ${libgloss_topdir}/config-ml.in,
srcdir=${srcdir}
target=${target}
ac_configure_args="${ac_configure_args} --enable-multilib"
CONFIG_SHELL=${CONFIG_SHELL-/bin/sh}
libgloss_topdir=${libgloss_topdir}
)

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libgloss/ms1/crt0-16-002.S Normal file
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; crt0_2.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
; Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
;
; The authors hereby grant permission to use, copy, modify, distribute,
; and license this software and its documentation for any purpose, provided
; that existing copyright notices are retained in all copies and that this
; notice is included verbatim in any distributions. No written agreement,
; license, or royalty fee is required for any of the authorized uses.
; Modifications to this software may be copyrighted by their authors
; and need not follow the licensing terms described here, provided that
; the new terms are clearly indicated on the first page of each file where
; they apply.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0

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; crt0.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
;
; Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
;
; The authors hereby grant permission to use, copy, modify, distribute,
; and license this software and its documentation for any purpose, provided
; that existing copyright notices are retained in all copies and that this
; notice is included verbatim in any distributions. No written agreement,
; license, or royalty fee is required for any of the authorized uses.
; Modifications to this software may be copyrighted by their authors
; and need not follow the licensing terms described here, provided that
; the new terms are clearly indicated on the first page of each file where
; they apply.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext1
or r0, r0, r0
.Lcpy0:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy0
or r0, r0, r0 ; nop
.Lnext1:
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(_fbdata_vma)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(_fbdata_vma)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the frame buffer bss section
ldui r9, #%hi16(_fbbss_start)
ori r9, r9, #%lo16(_fbbss_start)
ldui r10, #%hi16(_fbbss_end)
ori r10, r10, #%lo16(_fbbss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy2
or r0, r0, r0
.Lnext3:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #%lo16(_DEBUG_HALT_REG)
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0

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libgloss/ms1/crt0-64-001.S Normal file
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; crt0_2.s - Startup code for the mrisc1. This code initializes the C
; run-time model.
;
; 12Nov01 (DJK) - The return code from main was not being passed to exit().
; Now it is passed as a parameter in R1.
;
; 10Sep01 (DJK) - The function exit() does not return. However, in the
; the case of device error (if the halt bit does not
; function properly, for instance), then a catch loop
; has been added.
;
;
; Copyright 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
;
; Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.equ HALT_REG, 0x300
.section .text
.global _start
_start:
;; Initialize the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Copy data from ROM to Frame Buffer (on-chip memory)
ldui r9, #%hi16(_fbdata_start)
ori r9, r9, #%lo16(_fbdata_start)
ldui r10, #%hi16(_fbdata_end)
ori r10, r10, #%lo16(_fbdata_end)
ldui r11, #%hi16(__FRAME_BUFFER_START)
brle r10, r9, .Lnext1
ori r11, r11, #%lo16(__FRAME_BUFFER_START)
.Lcpy0:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy0
addi r11, r11, #$4
.Lnext1:
;; Copy data from ROM to External Memory (off-chip memory)
ldui r9, #%hi16(_extdata_start)
ori r9, r9, #%lo16(_extdata_start)
ldui r10, #%hi16(_extdata_end)
ori r10, r10, #%lo16(_extdata_end)
ldui r11, #%hi16(__EXTERNAL_MEMORY_START)
brle r10, r9, .Lnext2
ori r11, r11, #%lo16(__EXTERNAL_MEMORY_START)
.Lcpy1:
ldw r5, r9, #$0
addi r9, r9, #$4
stw r5, r11, #$0
brlt r9, r10, .Lcpy1
addi r11, r11, #$4
.Lnext2:
;; Zero the bss space
ldui r9, #%hi16(__bss_start)
addui r9, r9, #%lo16(__bss_start)
ldui r10, #%hi16(__bss_end)
addui r10, r10, #%lo16(__bss_end)
or r0, r0, r0
brle r10, r9, .Lnext3
or r0, r0, r0
.Lcpy2:
stw r0, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .Lcpy2
or r0, r0, r0 ; nop
.Lnext3:
;; Zero the external memory bss section
ldui r9, #%hi16(_extbss_start)
ori r9, r9, #%lo16(_extbss_start)
ldui r10, #%hi16(_extbss_end)
ori r10, r10, #%lo16(_extbss_end)
or r0, r0, r0
brle r10, r9, .Lnext4
or r0, r0, r0
.Lcpy3:
stw r0, r9, #$0
addi r9, r9, #$4
or r0, r0, r0
brle r9, r10, .Lcpy3
or r0, r0, r0
.Lnext4:
;; Call global and static constructors
ldui r10, #%hi16(_init)
ori r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Setup destructors to be called from exit.
;; (Just in case main never returns....)
ldui r10, #%hi16(atexit)
ori r10, r10, #%lo16(atexit)
ldui r1, #%hi16(_fini)
ori r1, r1, #%lo16(_fini)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Initialise argc, argv and envp to empty
addi r1, r0, #0
addi r2, r0, #0
addi r3, r0, #0
;; Call main
ldui r10, #%hi16(main)
ori r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; DJK - Added 12Nov01. Pass main's return value to exit.
or r1, r11, r0
;; Jump to exit
ldui r10, #%hi16(exit)
ori r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Exit does not return, however, this code is to catch an
;; error if it does. Set the processor into sleep mode.
ori r1, r0, #$1
stw r1, r0, #HALT_REG
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
.Lend:
jmp .Lend
or r0, r0, r0

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libgloss/ms1/crt0.S Normal file
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# Startup Code for the Morpho ms1
# Create a label for the start of the eh_frame section.
.section .eh_frame
__eh_frame_begin:
.section .text
.global _start
_start:
;; Initialise the stack pointer
ldui sp, #%hi16(__stack)
addui sp, sp, #%lo16(__stack)
or fp, sp, sp
;; Zero the data space
ldui r9, #%hi16(_edata)
addui r9, r9, #%lo16(_edata)
ldui r10, #%hi16(_end)
addui r10, r10, #%lo16(_end)
addi r5, r0, #0
.L0:
stw r5, r9, #0
addi r9, r9, #4
or r0, r0, r0 ; nop
brle r9, r10, .L0
or r0, r0, r0 ; nop
;; Call global and static constructors
ldui r10, #%hi16(_init)
addui r10, r10, #%lo16(_init)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Setup destructors to be called from exit.
;; (Just in case main never returns....)
ldui r10, #%hi16(atexit)
addui r10, r10, #%lo16(atexit)
ldui r1, #%hi16(_fini)
addui r1, r1, #%lo16(_fini)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Initialise argc, argv and envp to empty
addi r1, r0, #0
addi r2, r0, #0
addi r3, r0, #0
;; Call main
ldui r10, #%hi16(main)
addui r10, r10, #%lo16(main)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop
;; Jump to exit
ldui r10, #%hi16(exit)
addui r10, r10, #%lo16(exit)
or r0, r0, r0 ; nop
jal r14, r10
or r0, r0, r0 ; nop

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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
void _exit (n)
{
/* Set bit #0 in the _DEBUG_HALT_REG to trigger program exit to
the simulator. (The simulator will return a SIGQUIT signal.) */
asm("ori r1, r0, #$1\n");
asm("stw r1, r0, #$fffff300\n");
}

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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
void _exit (n)
{
/* Set bit #0 in the _DEBUG_HALT_REG to trigger program exit to
the simulator. (The simulator will return a SIGQUIT signal.) */
asm("ori r1, r0, #$1\n");
asm("stw r1, r0, #$fffff300\n");
}

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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
void _exit (n)
{
/* Set bit #0 in the _DEBUG_HALT_REG to trigger program exit to
the simulator. (The simulator will return a SIGQUIT signal.) */
asm("ori r1, r0, #$1\n");
asm("stw r1, r0, #$300\n");
}

10
libgloss/ms1/exit.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
void _exit (n)
{
TRAP0 (SYS_exit, n, 0, 0);
}

14
libgloss/ms1/fstat.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
int
fstat (int file,
struct stat *st)
{
st->st_mode = S_IFCHR;
st->st_blksize = 4096;
return 0;
}

10
libgloss/ms1/getpid.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
getpid (n)
{
return 1;
}

12
libgloss/ms1/gettime.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
#include "sys/time.h"
int
_gettimeofday (struct timeval *tp, void *tzp)
{
return TRAP0 (SYS_gettimeofday, tp, tzp, 0);
}

11
libgloss/ms1/isatty.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
isatty (fd)
int fd;
{
return 1;
}

11
libgloss/ms1/kill.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
kill (n, m)
{
return TRAP0 (SYS_exit, 0xdead, 0, 0);
}

14
libgloss/ms1/lseek.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/unistd.h>
#include "trap.h"
off_t
lseek (int file,
off_t ptr,
int dir)
{
return TRAP0 (SYS_lseek, file, ptr, dir);
}

11
libgloss/ms1/open.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
int
open (const char *path, int flags, int mode)
{
return TRAP0 (SYS_open, path, flags, mode);
}

12
libgloss/ms1/read.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
read (int file,
char *ptr,
size_t len)
{
return TRAP0 (SYS_read, file, ptr, len);
}

24
libgloss/ms1/sbrk.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
caddr_t
sbrk (size_t incr)
{
extern char end; /* Defined by the linker */
static char *heap_end;
char *prev_heap_end;
char *sp = (char *) &sp;
if (heap_end == 0)
{
heap_end = &end;
}
prev_heap_end = heap_end;
heap_end += incr;
return (caddr_t) prev_heap_end;
}

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/*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
*
*/
.section .startup, "a", @progbits
.global __boot_start
__boot_start:
_INTERRUPT_VECTOR_TABLE:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; The illegal instruction trap is not implemented.
_RESERVED1_IVEC:
jmp _RESERVED1_IVEC ; Vector for illegal instruction
or r0,r0,r0
jmp _OVFIVEC ; Vector for overflow exception
or r0,r0,r0
_RESERVED2_IVEC:
jmp _RESERVED2_IVEC
or r0,r0,r0
_RESERVED3_IVEC:
jmp _RESERVED3_IVEC
or r0,r0,r0
_RESERVED4_IVEC:
jmp _RESERVED4_IVEC
or r0,r0,r0
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
; Statically initialized data must be copied from ROM to RAM.
; This is done in the C run-time start-up code (crt0.o).
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x00031C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0 ; SYS_call is handled by simulator here...
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
; Handler for BREAK instruction. This handler triggers the simulator
; to send a SIGTRAP signal to gdb by writing to the I/O register at
; address $40005, setting bit #0 (0x1).
;
; The above address has been changed to 0x000304 and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
ldw r10, sp, #$0
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
; The documentation is lacking in the specification of the Overflow
; Exception generation. The address of the instruction causing the
; overflow is placed into R15 and the overflow exception interrupt
; is triggered. So, to continue execution, return to the address
; of the next instruction (i.e., R15 + one instruction).
_OVFIVEC:
addi r15, r15, #$4
or r0, r0, r0
reti r15
or r0, r0, r0
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
.section .internal_io, "a", @progbits
.fill 256 ; Fill the first page.
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
;.org 0xfff100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_REG
_DEV8_INTERRUPT_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_REG
_DEV9_INTERRUPT_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_REG
_DEV10_INTERRUPT_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_REG
_DEV11_INTERRUPT_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_REG
_DEV12_INTERRUPT_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_REG
_DEV13_INTERRUPT_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_REG
_DEV14_INTERRUPT_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_REG
_DEV15_INTERRUPT_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_REG
_DEV16_INTERRUPT_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_REG
_DEV17_INTERRUPT_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_REG
_DEV18_INTERRUPT_REG:
.word 0x00000000
; 128 bytes minus ten registers (four bytes per register)
.fill (128 - 19 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
; 128 bytes minus one register (four bytes per register)
.fill (128 - 1 * 4)
;.org 0xfff200
; MorphoSys Decoder Registers
.global _MS_DEC_CIRC_BUFF_SEL_REG
_MS_DEC_CIRC_BUFF_SEL_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERM_REG
_MS_DEC_CUSTOM_PERM_REG:
.word 0x00000000
.global _MS_DEC_CTXT_BASE_REG
_MS_DEC_CTXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TBL_REG
_MS_DEC_LOOKUP_TBL_REG:
.word 0x00000000
.global _MS_CIRC_BUFF0_END_REG
_MS_CIRC_BUFF0_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF0_SIZE_REG
_MS_CIRC_BUFF0_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK0_END_REG
_MS_DATA_BLK0_END_REG:
.word 0x00000000
.global _MS_DATA_BLK0_SIZE_REG
_MS_DATA_BLK0_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF1_END_REG
_MS_CIRC_BUFF1_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF1_SIZE_REG
_MS_CIRC_BUFF1_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK1_END_REG
_MS_DATA_BLK1_END_REG:
.word 0x00000000
.global _MS_DATA_BLK1_SIZE_REG
_MS_DATA_BLK1_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF2_END_REG
_MS_CIRC_BUFF2_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF2_SIZE_REG
_MS_CIRC_BUFF2_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK2_END_REG
_MS_DATA_BLK2_END_REG:
.word 0x00000000
.global _MS_DATA_BLK2_SIZE_REG
_MS_DATA_BLK2_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF3_END_REG
_MS_CIRC_BUFF3_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF3_SIZE_REG
_MS_CIRC_BUFF3_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK3_END_REG
_MS_DATA_BLK3_END_REG:
.word 0x00000000
.global _MS_DATA_BLK3_SIZE_REG
_MS_DATA_BLK3_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF4_END_REG
_MS_CIRC_BUFF4_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF4_SIZE_REG
_MS_CIRC_BUFF4_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK4_END_REG
_MS_DATA_BLK4_END_REG:
.word 0x00000000
.global _MS_DATA_BLK4_SIZE_REG
_MS_DATA_BLK4_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF5_END_REG
_MS_CIRC_BUFF5_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF5_SIZE_REG
_MS_CIRC_BUFF5_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK5_END_REG
_MS_DATA_BLK5_END_REG:
.word 0x00000000
.global _MS_DATA_BLK5_SIZE_REG
_MS_DATA_BLK5_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF6_END_REG
_MS_CIRC_BUFF6_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF6_SIZE_REG
_MS_CIRC_BUFF6_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK6_END_REG
_MS_DATA_BLK6_END_REG:
.word 0x00000000
.global _MS_DATA_BLK6_SIZE_REG
_MS_DATA_BLK6_SIZE_REG:
.word 0x00000000
.global _MS_CIRC_BUFF7_END_REG
_MS_CIRC_BUFF7_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF7_SIZE_REG
_MS_CIRC_BUFF7_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLK7_END_REG
_MS_DATA_BLK7_END_REG:
.word 0x00000000
.global _MS_DATA_BLK7_SIZE_REG
_MS_DATA_BLK7_SIZE_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC0_REG
_MS_DEC_AUTO_INC0_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC1_REG
_MS_DEC_AUTO_INC1_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC2_REG
_MS_DEC_AUTO_INC2_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC3_REG
_MS_DEC_AUTO_INC3_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC4_REG
_MS_DEC_AUTO_INC4_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC5_REG
_MS_DEC_AUTO_INC5_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC6_REG
_MS_DEC_AUTO_INC6_REG:
.word 0x00000000
.global _MS_DEC_AUTO_INC7_REG
_MS_DEC_AUTO_INC7_REG:
.word 0x00000000
; 256 bytes minus forty-five registers (four bytes per register)
.fill (256 - 45 * 4)
;.org 0xfff300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
; There are five reserved registers.
.fill (5 * 4)
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
;.org 0xfff400
; Sequence Generator Registers
.global _SEQ_GEN_CTRL_REG
_SEQ_GEN_CTRL_REG:
.word 0x00000000
.global _SEQ_GEN_MASK_REGS
_SEQ_GEN_MASK_REGS:
; The mask registers consume two pages (less one control register).
; 512 bytes minus one register (four bytes per register).
.fill (256 + 256 - 1 * 4)
;.org 0xfff600
; Timer Registers
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER3_VAL_REG
_TIMER3_VAL_REG:
.word 0x00000000
; 256 bytes minus four registers (four bytes per register)
.fill (256 - 4 * 4)
;.org 0xfff700
; Output Line Control Registers
.global _OUTPUT0_CTRL
_OUTPUT0_CTRL:
.word 0x00000000
.global _OUTPUT1_CTRL
_OUTPUT1_CTRL:
.word 0x00000000
.global _OUTPUT2_CTRL
_OUTPUT2_CTRL:
.word 0x00000000
.global _OUTPUT3_CTRL
_OUTPUT3_CTRL:
.word 0x00000000
.global _OUTPUT4_CTRL
_OUTPUT4_CTRL:
.word 0x00000000
.global _OUTPUT5_CTRL
_OUTPUT5_CTRL:
.word 0x00000000
.global _OUTPUT6_CTRL
_OUTPUT6_CTRL:
.word 0x00000000
.global _OUTPUT7_CTRL
_OUTPUT7_CTRL:
.word 0x00000000
.global _OUTPUT8_CTRL
_OUTPUT8_CTRL:
.word 0x00000000
.global _OUTPUT9_CTRL
_OUTPUT9_CTRL:
.word 0x00000000
.global _OUTPUT10_CTRL
_OUTPUT10_CTRL:
.word 0x00000000
;; 128 bytes minus eleven registers (four bytes per register)
;.fill (128 - 11 * 4)
.global _INPUT0_CTRL
_INPUT0_CTRL:
.word 0x00000000
;; 128 bytes minus one register (four bytes per register)
;.fill (128 - 1 * 4)
; 256 bytes minus twelve registers (four bytes per register)
.fill (256 - 12 * 4)
;.org 0xfff800
; IQ Buffer Registers
.global _IQ_BUFF_CTRL_REG
_IQ_BUFF_CTRL_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER1_REG
_IQ_BUFF_PARAMETER1_REG:
.word 0x00000000
.global _IQ_BUFF_DATA_SIZE1_REG
_IQ_BUFF_DATA_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE1_REG
_IQ_BUFF_TRANSFER_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_ADDR1_REG
_IQ_BUFF_FB_ADDR1_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER2_REG
_IQ_BUFF_PARAMETER2_REG:
.word 0x00000000
.global _IQ_BUFF_DATA_SIZE2_REG
_IQ_BUFF_DATA_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE2_REG
_IQ_BUFF_TRANSFER_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_ADDR2_REG
_IQ_BUFF_FB_ADDR2_REG:
.word 0x00000000
; 256 bytes minus nine registers (four bytes per register)
.fill (256 - 9 * 4)
;.org 0xfff900
; Reserved memory-mapped space.
.fill (0x1000 - 0x900)

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@ -0,0 +1,838 @@
/*
* $Header$
*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
* 09Jan04 (DJK) Modified internal I/O port definitions for the
* MS1-16-003.
*
* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
* space is now reserved for memory-mapped I/O devices.
* (There is over 2K unused, reserved space in this area.)
*
* 26Sep01 (DJK) The memory map is changed and the device interrupts are
* now memory-mapped.
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
*
*/
.section .startup, "a", @progbits
.global __boot_start
__boot_start:
_INTERRUPT_VECTOR_TABLE:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; The illegal instruction trap is not implemented.
;jmp _ILLIVEC ; Vector for illegal instruction
or r0,r0,r0
or r0,r0,r0
_RESERVED1_IVEC:
jmp _RESERVED1_IVEC
or r0,r0,r0
_RESERVED2_IVEC:
jmp _RESERVED2_IVEC
or r0,r0,r0
_RESERVED3_IVEC:
jmp _RESERVED3_IVEC
or r0,r0,r0
_RESERVED4_IVEC:
jmp _RESERVED4_IVEC
or r0,r0,r0
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
; Statically initialized data must be copied from ROM to RAM.
; This is done in the C run-time start-up code (crt0.o).
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x00031C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
; SYS_call is handled by simulator here...
or r0, r0, r0
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
or r0, r0, r0
ldw r10, sp, #$0
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
.if 0
; Handler for illegal instruction.
.global _ILLIVEC
_ILLIVEC:
reti r15
or r0, r0, r0
.endif
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0
.section .internal_io, "a", @progbits
.fill 256 ; Fill the first page.
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
;.org 0xfffff100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_REG
_DEV8_INTERRUPT_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_REG
_DEV9_INTERRUPT_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_REG
_DEV10_INTERRUPT_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_REG
_DEV11_INTERRUPT_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_REG
_DEV12_INTERRUPT_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_REG
_DEV13_INTERRUPT_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_REG
_DEV14_INTERRUPT_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_REG
_DEV15_INTERRUPT_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_REG
_DEV16_INTERRUPT_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_REG
_DEV17_INTERRUPT_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_REG
_DEV18_INTERRUPT_REG:
.word 0x00000000
; 128 bytes minus nineteen registers (four bytes per register)
.fill (128 - 19 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
.global _INTERRUPT_PENDING_REG
_INTERRUPT_PENDING_REG:
.word 0x00000000
; 16 bytes minus two registers (four bytes per register)
.fill (16 - 2 * 4)
.global _DEV0_INTERRUPT_LEVEL_REG
_DEV0_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_LEVEL_REG
_DEV1_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_LEVEL_REG
_DEV2_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_LEVEL_REG
_DEV3_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_LEVEL_REG
_DEV4_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_LEVEL_REG
_DEV5_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_LEVEL_REG
_DEV6_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_LEVEL_REG
_DEV7_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV8_INTERRUPT_LEVEL_REG
_DEV8_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV9_INTERRUPT_LEVEL_REG
_DEV9_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV10_INTERRUPT_LEVEL_REG
_DEV10_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV11_INTERRUPT_LEVEL_REG
_DEV11_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV12_INTERRUPT_LEVEL_REG
_DEV12_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV13_INTERRUPT_LEVEL_REG
_DEV13_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV14_INTERRUPT_LEVEL_REG
_DEV14_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV15_INTERRUPT_LEVEL_REG
_DEV15_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV16_INTERRUPT_LEVEL_REG
_DEV16_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV17_INTERRUPT_LEVEL_REG
_DEV17_INTERRUPT_LEVEL_REG:
.word 0x00000000
.global _DEV18_INTERRUPT_LEVEL_REG
_DEV18_INTERRUPT_LEVEL_REG:
.word 0x00000000
; 128 bytes minus twenty-three registers (four bytes per register)
.fill (128 - 23 * 4)
;.org 0xfffff200
; MorphoSys Decoder Registers
.global _MS_DEC_CIRC_BUFF_SEL_REG
_MS_DEC_CIRC_BUFF_SEL_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERM_REG
_MS_DEC_CUSTOM_PERM_REG:
.word 0x00000000
.global _MS_DEC_CTXT_BASE_REG
_MS_DEC_CTXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TBL_REG
_MS_DEC_LOOKUP_TBL_REG:
.word 0x00000000
.global _MS_CIRC_BUFF0_I_REG
_MS_CIRC_BUFF0_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF0_P_REG
_MS_CIRC_BUFF0_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF0_B_REG
_MS_DATA_BUFF0_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF0_S_REG
_MS_DATA_BUFF0_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF1_I_REG
_MS_CIRC_BUFF1_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF1_P_REG
_MS_CIRC_BUFF1_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF1_B_REG
_MS_DATA_BUFF1_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF1_S_REG
_MS_DATA_BUFF1_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF2_I_REG
_MS_CIRC_BUFF2_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF2_P_REG
_MS_CIRC_BUFF2_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF2_B_REG
_MS_DATA_BUFF2_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF2_S_REG
_MS_DATA_BUFF2_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF3_I_REG
_MS_CIRC_BUFF3_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF3_P_REG
_MS_CIRC_BUFF3_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF3_B_REG
_MS_DATA_BUFF3_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF3_S_REG
_MS_DATA_BUFF3_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF4_I_REG
_MS_CIRC_BUFF4_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF4_P_REG
_MS_CIRC_BUFF4_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF4_B_REG
_MS_DATA_BUFF4_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF4_S_REG
_MS_DATA_BUFF4_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF5_I_REG
_MS_CIRC_BUFF5_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF5_P_REG
_MS_CIRC_BUFF5_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF5_B_REG
_MS_DATA_BUFF5_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF5_S_REG
_MS_DATA_BUFF5_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF6_I_REG
_MS_CIRC_BUFF6_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF6_P_REG
_MS_CIRC_BUFF6_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF6_B_REG
_MS_DATA_BUFF6_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF6_S_REG
_MS_DATA_BUFF6_S_REG:
.word 0x00000000
.global _MS_CIRC_BUFF7_I_REG
_MS_CIRC_BUFF7_I_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRC_BUFF7_P_REG
_MS_CIRC_BUFF7_P_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BUFF7_B_REG
_MS_DATA_BUFF7_B_REG:
.word 0x00000000
.global _MS_DATA_BUFF7_S_REG
_MS_DATA_BUFF7_S_REG:
.word 0x00000000
.global _MS_OMEGA_PERM1_REG
_MS_OMEGA_PERM1_REG:
.word 0x00000000
.global _MS_WRITE_FB_ADDR_REG
_MS_WRITE_FB_ADDR_REG:
.word 0x00000000
.global _MS_OMEGA_PERM2_REG
_MS_OMEGA_PERM2_REG:
.word 0x00000000
; 256 bytes minus forty registers (four bytes per register)
.fill (256 - 40 * 4)
;.org 0xfffff300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
.global _DEBUG_CRITICAL_REG
_DEBUG_OWNERSHIP_REG:
.word 0x00000000
.global _DEBUG_KERNEL_ID_REG
_DEBUG_KERNEL_ID_REG:
.word 0x00000000
.global _DEBUG_IRQ_STATUS_REG
_DEBUG_IRQ_STATUS_REG:
.word 0x00000000
; There are two reserved registers.
.fill (2 * 4)
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 128 bytes minus eight registers (four bytes per register)
.fill (128 - 8 * 4)
.global _EXTENDED_GP0_REG
_EXTENDED_GP0_REG:
.word 0x00000000
.global _EXTENDED_GP1_REG
_EXTENDED_GP1_REG:
.word 0x00000000
.global _EXTENDED_GP2_REG
_EXTENDED_GP2_REG:
.word 0x00000000
.global _EXTENDED_GP3_REG
_EXTENDED_GP3_REG:
.word 0x00000000
.global _EXTENDED_GP4_REG
_EXTENDED_GP4_REG:
.word 0x00000000
.global _EXTENDED_GP5_REG
_EXTENDED_GP5_REG:
.word 0x00000000
.global _EXTENDED_GP6_REG
_EXTENDED_GP6_REG:
.word 0x00000000
.global _EXTENDED_GP7_REG
_EXTENDED_GP7_REG:
.word 0x00000000
.global _MEM_CTRL_EN_NC_MEM_REG
_MEM_CTRL_EN_NC_MEM_REG:
.word 0x00000000
.global _MEM_CTRL_BASE0_ADDR_REG
_MEM_CTRL_BASE0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK0_ADDR_REG
_MEM_CTRL_MASK0_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE1_ADDR_REG
_MEM_CTRL_BASE1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK1_ADDR_REG
_MEM_CTRL_MASK1_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE2_ADDR_REG
_MEM_CTRL_BASE2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK2_ADDR_REG
_MEM_CTRL_MASK2_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_BASE3_ADDR_REG
_MEM_CTRL_BASE3_ADDR_REG:
.word 0x00000000
.global _MEM_CTRL_MASK3_ADDR_REG
_MEM_CTRL_MASK3_ADDR_REG:
.word 0x00000000
; 128 bytes minus seventeen registers (four bytes per register)
.fill (128 - 17 * 4)
; Reserved memory-map space
.fill (256 + 256)
;.org 0xfffff600
; Timer Registers
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER3_VAL_REG
_TIMER3_VAL_REG:
.word 0x00000000
; 256 bytes minus four registers (four bytes per register)
.fill (256 - 4 * 4)
;.org 0xfffff700
; Output Line Control Registers
.global _OUTPUT0_CTRL
_OUTPUT0_CTRL:
.word 0x00000000
.global _OUTPUT1_CTRL
_OUTPUT1_CTRL:
.word 0x00000000
.global _OUTPUT2_CTRL
_OUTPUT2_CTRL:
.word 0x00000000
.global _OUTPUT3_CTRL
_OUTPUT3_CTRL:
.word 0x00000000
.global _OUTPUT4_CTRL
_OUTPUT4_CTRL:
.word 0x00000000
.global _OUTPUT5_CTRL
_OUTPUT5_CTRL:
.word 0x00000000
.global _OUTPUT6_CTRL
_OUTPUT6_CTRL:
.word 0x00000000
; 128 bytes minus seven registers (four bytes per register)
.fill (128 - 7 * 4)
.global _INPUT0_CTRL
_INPUT0_CTRL:
.word 0x00000000
; 128 bytes minus one register (four bytes per register)
.fill (128 - 1 * 4)
;.org 0xfffff800
; IQ Buffer Registers
.global _IQ_BUFF_CTRL_REG
_IQ_BUFF_CTRL_REG:
.word 0x00000000
.global _IQ_BUFF_STATUS_REG
_IQ_BUFF_STATUS_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER1_REG
_IQ_BUFF_PARAMETER1_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE1_REG
_IQ_BUFF_TRANSFER_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE1_REG
_IQ_BUFF_FB_BASE1_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE1_REG
_IQ_BUFF_FB_SIZE1_REG:
.word 0x00000000
.global _IQ_BUFF_PARAMETER2_REG
_IQ_BUFF_PARAMETER2_REG:
.word 0x00000000
.global _IQ_BUFF_TRANSFER_SIZE2_REG
_IQ_BUFF_TRANSFER_SIZE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_BASE2_REG
_IQ_BUFF_FB_BASE2_REG:
.word 0x00000000
.global _IQ_BUFF_FB_SIZE2_REG
_IQ_BUFF_FB_SIZE2_REG:
.word 0x00000000
; 256 bytes minus ten registers (four bytes per register)
.fill (256 - 10 * 4)
;.org 0xfffff900
; DMA Controller
.global _DMA_CTRL_REG
_DMA_CTRL_REG:
.word 0x00000000
.global _DMA_STATUS_REG
_DMA_STATUS_REG:
.word 0x00000000
.global _DMA_CH0_EADDR_REG
_DMA_CH0_EADDR_REG:
.word 0x00000000
.global _DMA_CH0_IADDR_REG
_DMA_CH0_IADDR_REG:
.word 0x00000000
.global _DMA_CH0_SIZE_REG
_DMA_CH0_SIZE_REG:
.word 0x00000000
.global _DMA_CH1_EADDR_REG
_DMA_CH1_EADDR_REG:
.word 0x00000000
.global _DMA_CH1_IADDR_REG
_DMA_CH1_IADDR_REG:
.word 0x00000000
.global _DMA_CH1_SIZE_REG
_DMA_CH1_SIZE_REG:
.word 0x00000000
.global _DMA_CH2_EADDR_REG
_DMA_CH2_EADDR_REG:
.word 0x00000000
.global _DMA_CH2_IADDR_REG
_DMA_CH2_IADDR_REG:
.word 0x00000000
.global _DMA_CH2_SIZE_REG
_DMA_CH2_SIZE_REG:
.word 0x00000000
.global _DMA_CH3_EADDR_REG
_DMA_CH3_EADDR_REG:
.word 0x00000000
.global _DMA_CH3_IADDR_REG
_DMA_CH3_IADDR_REG:
.word 0x00000000
.global _DMA_CH3_SIZE_REG
_DMA_CH3_SIZE_REG:
.word 0x00000000
; 256 bytes minus fourteen registers (four bytes per register)
.fill (256 - 14 * 4)
;.org 0xfffffa00
; Sequence Generator
.global _SEQ_GEN_CTRL_STATUS_REG
_SEQ_GEN_CTRL_STATUS_REG:
.word 0x00000000
.global _SEQ_GEN_MASK_REGS
_SEQ_GEN_MASK_REGS:
.fill (302 * 4)
.global _SEQ_GEN_SHIFT_REG
_SEQ_GEN_SHIFT_REG:
.word 0x00000000
; 256 bytes minus seven registers (four bytes per register)
.fill (256 - 48 * 4)
; Reserved memory-map space
.fill (0x1000 - 0xf00)

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@ -0,0 +1,378 @@
/*
* $Header$
*
* interrupt_vectors.s -- the interrupt handler jump table.
*
*
* There are a total of 32 interrupt vector possible, however, only
* 11 of those are currently used (the others are reserved). The
* order of vectors is as follows:
*
* 1. Boot Vector. Vector for power-on/reset.
* 2. Software Vector. Vector for handling the SI instruction (an
* explicit interrupt caused by software).
* 3. Break Vector. Vector for handling the Break instruction.
* 4. Device 0 Vector. Service vector for device zero.
* 5. Device 1 Vector. Service vector for device one.
* 6. Device 2 Vector. Service vector for device two.
* 7. Device 3 Vector. Service vector for device three.
* 8. Device 4 Vector. Service vector for device four.
* 9. Device 5 Vector. Service vector for device five.
* 10. Device 6 Vector. Service vector for device six.
* 11. Device 7 Vector. Service vector for device seven.
*
* The rest of the interrupt vectors are reserved for future use.
*
*
* Each jump table entry consists of the following two instructions:
*
* jmp Label ; Label as appropriate
* nop ; implemented as or r0,r0,r0
*
* The following labels are reserved for the vectors named above,
* respectively:
*
* _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
* _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
*
*
* 26Sep01 (DJK) The memory map is changed and the device interrupts are
* now memory-mapped.
*
* 10Oct01 (DJK) The memory map is finalized and the first 4K of address
* space is now reserved for memory-mapped I/O devices.
* (There is over 2K unused, reserved space in this area.)
*
* 27Jul02 (DJK) Fixed the address for the interrupt mask register. Old
* documentation stated the port address as 0x140, but
* the implementation uses 0x13c.
*
* 30Jul02 (DJK) Added support for printf. This only supports output to
* stderr and stdout. Using the message box interface,
* a (newly defined) message or series of messages is
* passed to the controller to output bytes as text to
* the debug console. These messages are constructed in
* the interrupt handler for the SI instruction.
* With this implementation, the user is unable to
* utilize the message box interface in applications as
* specialized interrupt handlers for the external
* interrupts are necessary.
*
*
*
* Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
*
*/
.section .startup, "a", @progbits
.global __boot_start
_INTERRUPT_VECTOR_TABLE:
__boot_start:
jmp _BOOTIVEC ; Boot vector
or r0, r0, r0
jmp _SOFTIVEC ; Vector for SI instruction
or r0,r0,r0
jmp _BRKIVEC ; Vector for Break instruction
or r0,r0,r0
; This is the memory-mapped I/O region.
; Hardware Interrupt Registers
.org 0x100
.global _DEV0_INTERRUPT_REG
_DEV0_INTERRUPT_REG:
.word 0x00000000
.global _DEV1_INTERRUPT_REG
_DEV1_INTERRUPT_REG:
.word 0x00000000
.global _DEV2_INTERRUPT_REG
_DEV2_INTERRUPT_REG:
.word 0x00000000
.global _DEV3_INTERRUPT_REG
_DEV3_INTERRUPT_REG:
.word 0x00000000
.global _DEV4_INTERRUPT_REG
_DEV4_INTERRUPT_REG:
.word 0x00000000
.global _DEV5_INTERRUPT_REG
_DEV5_INTERRUPT_REG:
.word 0x00000000
.global _DEV6_INTERRUPT_REG
_DEV6_INTERRUPT_REG:
.word 0x00000000
.global _DEV7_INTERRUPT_REG
_DEV7_INTERRUPT_REG:
.word 0x00000000
; 60 bytes minus eight registers (four bytes per register)
.fill (60 - 8 * 4)
.global _INTERRUPT_MASK_REG
_INTERRUPT_MASK_REG:
.word 0x00000000
; 256 bytes minus sixteen registers (four bytes per register)
.fill (256 - 16 * 4)
.org 0x200
; MorphoSys Decoder Registers
.global _MS_DEC_AUTO_INCREMENT_REG
_MS_DEC_AUTO_INCREMENT_REG:
.word 0x00000000
.global _MS_DEC_SKIP_FACTOR_REG
_MS_DEC_SKIP_FACTOR_REG:
.word 0x00000000
.global _MS_DEC_CUSTOM_PERMUTATION_REG
_MS_DEC_CUSTOM_PERMUTATION_REG:
.word 0x00000000
.global _MS_DEC_CONTEXT_BASE_REG
_MS_DEC_CONTEXT_BASE_REG:
.word 0x00000000
.global _MS_DEC_LOOKUP_TABLE_BASE_REG
_MS_DEC_LOOKUP_TABLE_BASE_REG:
.word 0x00000000
.global _MS_CIRCULAR_BUFFER_END_REG
_MS_CIRCULAR_BUFFER_END_REG:
.word (__FRAME_BUFFER_END)
.global _MS_CIRCULAR_BUFFER_SIZE_REG
_MS_CIRCULAR_BUFFER_SIZE_REG:
.word __FRAME_BUFFER_SIZE
.global _MS_DATA_BLOCK_END_REG
_MS_DATA_BLOCK_END_REG:
.word 0x00000000
.global _MS_DATA_BLOCK_SIZE_REG
_MS_DATA_BLOCK_SIZE_REG:
.word 0x00000000
; 256 bytes minus nine registers (four bytes per register)
.fill (256 - 9 * 4)
.org 0x300
; Debug Registers
.global _DEBUG_HALT_REG
_DEBUG_HALT_REG:
.word 0x00000000
.global _DEBUG_BREAK_REG
_DEBUG_BREAK_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED0_REG
_DEBUG_HW_RESERVED0_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED1_REG
_DEBUG_HW_RESERVED1_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED2_REG
_DEBUG_HW_RESERVED2_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED3_REG
_DEBUG_HW_RESERVED3_REG:
.word 0x00000000
.global _DEBUG_HW_RESERVED4_REG
_DEBUG_HW_RESERVED4_REG:
.word 0x00000000
.global _DEBUG_SW_SYSREQ_REG
_DEBUG_SW_SYSREQ_REG:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
.org 0x400
; Sequence Generator Registers
_SEQ_GEN_REGS:
.fill 256
.org 0x500
_RESERVED_SEQ_GEN_REGS:
.fill 256
.org 0x600
.global _TIMER0_VAL_REG
_TIMER0_VAL_REG:
.word 0x00000000
.global _TIMER0_CTRL_REG
_TIMER0_CTRL_REG:
.word 0x00000000
.global _TIMER1_VAL_REG
_TIMER1_VAL_REG:
.word 0x00000000
.global _TIMER1_CTRL_REG
_TIMER1_CTRL_REG:
.word 0x00000000
.global _TIMER2_VAL_REG
_TIMER2_VAL_REG:
.word 0x00000000
.global _TIMER2_CTRL_REG
_TIMER2_CTRL_REG:
.word 0x00000000
; 256 bytes minus six registers (four bytes per register)
.fill (256 - 6 * 4)
.org 0x700
.global _OUTPUT0_CONTROL
_OUTPUT0_CONTROL:
.word 0x00000000
.global _OUTPUT1_CONTROL
_OUTPUT1_CONTROL:
.word 0x00000000
.global _OUTPUT2_CONTROL
_OUTPUT2_CONTROL:
.word 0x00000000
.global _OUTPUT3_CONTROL
_OUTPUT3_CONTROL:
.word 0x00000000
.global _OUTPUT4_CONTROL
_OUTPUT4_CONTROL:
.word 0x00000000
.global _OUTPUT5_CONTROL
_OUTPUT5_CONTROL:
.word 0x00000000
.global _OUTPUT6_CONTROL
_OUTPUT6_CONTROL:
.word 0x00000000
.global _OUTPUT7_CONTROL
_OUTPUT7_CONTROL:
.word 0x00000000
; 256 bytes minus eight registers (four bytes per register)
.fill (256 - 8 * 4)
.org 0x800
; Reserved memory-mapped space.
.fill (0x1000 - 0x800)
.text
.equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
.equ SI_IOPORT_BIT, 0x1
.equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
.equ BRK_IOPORT_BIT, 0x1
.global _BOOTIVEC
_BOOTIVEC:
; Initialize the interrupt controller's interrupt vector registers
; for devices zero through seven.
ldui r1, #%hi16(_IVEC_DEFAULT)
ori r1, r1, #%lo16(_IVEC_DEFAULT)
stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
; Jump to the beginning of the application and enable interrupts.
jmp _start
ei
; Handler for the SI instruction. To perform a system call, the
; C model uses a trapping mechanism which executes an SI instruction.
; The Morpho Technologies simulator simply performs a branch to
; this vector to simulate the SI instruction (this is as the hardware
; behaves). In order to trigger the simulator that a system call
; is needed, a write into the I/O register at address $40005 to
; set bit #2 (0x4) is necessary.
;
; The above address has been changed to 0x31C and the bit number
; is zero. (The manifest constants have been changed to reflect this.)
;
.global _SOFTIVEC
_SOFTIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(SI_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(SI_IOPORT_ADR)
ori r10, r0, #SI_IOPORT_BIT
stw r10, r9, #$0
; SYS_call is handled by simulator here...
or r0, r0, r0
ldw r10, sp, #$0
or r0, r0, r0
ldw r9, sp, #$4
reti r14
addi sp, sp, #$8
.global _BRKIVEC
_BRKIVEC:
; Build a frame to save registers.
subi sp, sp, #$8
stw r9, sp, #$4
ldui r9, #%hi16(BRK_IOPORT_ADR)
stw r10, sp, #$0
ori r9, r9, #%lo16(BRK_IOPORT_ADR)
ori r10, r0, #BRK_IOPORT_BIT
stw r10, r9, #$0
or r0, r0, r0
ldw r10, sp, #$0
subi r15, r15, #$4 ; Backup to address of break
ldw r9, sp, #$4
reti r15
addi sp, sp, #$8
.global _IVEC_DEFAULT
_IVEC_DEFAULT:
reti r15
or r0, r0, r0

12
libgloss/ms1/stat.c Normal file
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@ -0,0 +1,12 @@
#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
int
stat (const char *path, struct stat *st)
{
return TRAP0 (SYS_stat, path, st, 0);
}

11
libgloss/ms1/time.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
time_t
time (time_t *tloc)
{
return TRAP0 (SYS_time, tloc, 0, 0);
}

12
libgloss/ms1/times.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
#include "sys/times.h"
clock_t
times (struct tms *buffer)
{
return TRAP0 (SYS_times, buffer, 0, 0);
}

34
libgloss/ms1/trap.S Normal file
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;;
;; The errno will be in r5 if r11 is -1.
;;
.text
.global __trap0
__trap0:
;; non-leaf function so need to create stack frame to
;; store ra and fp
subi sp, sp, #16
stw ra, sp, #12
or r0, r0, r0 ;; nop
stw fp, sp, #8
or fp, sp, sp
stw r5, sp, #4
or r0, r0, r0 ;; nop
stw r6, sp, #0
addi r6, r0, #$-1
si r14
or r0, r0, r0 ;; nop
brne r11, r6, .L0
ldui r6, #%hi16(errno)
addui r6, r6, #%lo16(errno)
stw r5, r6, #0
or r0, r0, r0 ;; nop
.L0:
ldw r6, sp, #0
or r0, r0, r0 ;; nop
ldw r5, sp, #4
or r0, r0, r0 ;; nop
ldw ra, sp, #12
or r0, r0, r0 ;; nop
ldw fp, sp, #8
jal r0, r14
addi sp, sp, #16

5
libgloss/ms1/trap.h Normal file
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#include "syscall.h"
int __trap0 ();
#define TRAP0(f, p1, p2, p3) __trap0(f, (p1), (p2), (p3))

11
libgloss/ms1/unlink.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
int
unlink ()
{
return -1;
}

13
libgloss/ms1/utime.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
int
utime (path, times)
const char *path;
char *times;
{
return TRAP0 (SYS_utime, path, times, 0);
}

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libgloss/ms1/write.c Normal file
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#include <_ansi.h>
#include <sys/types.h>
#include <sys/stat.h>
#include "trap.h"
int
write ( int file,
char *ptr,
size_t len)
{
return TRAP0 (SYS_write, file, ptr, len);
}