Update function declarations to ISO C90 formatting
This commit is contained in:
Nick Clifton
parent
371e383f89
commit
310932f740
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@ -1,3 +1,7 @@
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2005-07-01 Nick Clifton <nickc@redhat.com>
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* sparc.h: Add typedefs to structure declarations.
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2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
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PR 1013
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@ -1,24 +1,24 @@
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/* Definitions for opcode table for the sparc.
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Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
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2003 Free Software Foundation, Inc.
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2003, 2005 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
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the GNU Binutils.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS/GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GAS/GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 51 Franklin Street - Fifth Floor,
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Boston, MA 02110-1301, USA. */
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#include "ansidecl.h"
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@ -37,17 +37,18 @@ Boston, MA 02110-1301, USA. */
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The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
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Don't change this without updating sparc-opc.c. */
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enum sparc_opcode_arch_val {
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enum sparc_opcode_arch_val
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{
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SPARC_OPCODE_ARCH_V6 = 0,
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SPARC_OPCODE_ARCH_V7,
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SPARC_OPCODE_ARCH_V8,
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SPARC_OPCODE_ARCH_SPARCLET,
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SPARC_OPCODE_ARCH_SPARCLITE,
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/* v9 variants must appear last */
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/* V9 variants must appear last. */
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SPARC_OPCODE_ARCH_V9,
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SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */
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SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */
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SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */
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SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
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SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
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SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
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};
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/* The highest architecture in the table. */
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@ -62,14 +63,15 @@ enum sparc_opcode_arch_val {
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/* Table of cpu variants. */
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struct sparc_opcode_arch {
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typedef struct sparc_opcode_arch
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{
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const char *name;
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/* Mask of sparc_opcode_arch_val's supported.
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EG: For v7 this would be
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(SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
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These are short's because sparc_opcode.architecture is. */
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short supported;
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};
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} sparc_opcode_arch;
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extern const struct sparc_opcode_arch sparc_opcode_archs[];
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@ -82,44 +84,43 @@ extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
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/* Non-zero if ARCH1 conflicts with ARCH2.
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IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
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#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
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(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
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&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
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&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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!= SPARC_OPCODE_SUPPORTED (ARCH2)))
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/* Structure of an opcode table entry. */
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struct sparc_opcode {
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typedef struct sparc_opcode
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{
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const char *name;
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unsigned long match; /* Bits that must be set. */
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unsigned long lose; /* Bits that must not be set. */
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unsigned long match; /* Bits that must be set. */
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unsigned long lose; /* Bits that must not be set. */
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const char *args;
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/* This was called "delayed" in versions before the flags. */
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/* This was called "delayed" in versions before the flags. */
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char flags;
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short architecture; /* Bitmask of sparc_opcode_arch_val's. */
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};
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} sparc_opcode;
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#define F_DELAYED 1 /* Delayed branch */
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#define F_ALIAS 2 /* Alias for a "real" instruction */
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#define F_UNBR 4 /* Unconditional branch */
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#define F_CONDBR 8 /* Conditional branch */
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#define F_JSR 16 /* Subroutine call */
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#define F_FLOAT 32 /* Floating point instruction (not a branch) */
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#define F_FBR 64 /* Floating point branch */
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#define F_DELAYED 1 /* Delayed branch. */
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#define F_ALIAS 2 /* Alias for a "real" instruction. */
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#define F_UNBR 4 /* Unconditional branch. */
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#define F_CONDBR 8 /* Conditional branch. */
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#define F_JSR 16 /* Subroutine call. */
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#define F_FLOAT 32 /* Floating point instruction (not a branch). */
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#define F_FBR 64 /* Floating point branch. */
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/* FIXME: Add F_ANACHRONISTIC flag for v9. */
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/*
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/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
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macro), which is 64 bits. It is handled as a special case.
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All sparc opcodes are 32 bits, except for the `set' instruction (really a
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macro), which is 64 bits. It is handled as a special case.
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The match component is a mask saying which bits must match a particular
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opcode in order for an instruction to be an instance of that opcode.
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The match component is a mask saying which bits must match a particular
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opcode in order for an instruction to be an instance of that opcode.
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The args component is a string containing one character for each operand of the
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instruction.
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The args component is a string containing one character for each operand of the
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instruction.
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Kinds of operands:
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Kinds of operands:
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# Number used by optimizer. It is ignored.
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1 rs1 register.
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2 rs2 register.
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@ -187,37 +188,35 @@ Kinds of operands:
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_ Ancillary state register in rd (v9a)
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/ Ancillary state register in rs1 (v9a)
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The following chars are unused: (note: ,[] are used as punctuation)
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[45]
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The following chars are unused: (note: ,[] are used as punctuation)
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[45]. */
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*/
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#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
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#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
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#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
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#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
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#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
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#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
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#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
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#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
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#define F1(x) (OP (x))
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#define DISP30(x) ((x) & 0x3fffffff)
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#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
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#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
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#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
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#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
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#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
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#define ASI_RS2(x) (SIMM13 (x))
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#define MEMBAR(x) ((x) & 0x7f)
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#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
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#define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */
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#define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */
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#define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */
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#define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */
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#define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */
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#define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
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#define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */
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#define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */
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#define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
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#define F1(x) (OP(x))
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#define DISP30(x) ((x)&0x3fffffff)
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#define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */
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#define RS2(x) ((x)&0x1f) /* rs2 field */
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#define SIMM13(x) ((x)&0x1fff) /* simm13 field */
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#define RD(x) (((x)&0x1f) << 25) /* destination register field */
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#define RS1(x) (((x)&0x1f) << 14) /* rs1 field */
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#define ASI_RS2(x) (SIMM13(x))
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#define MEMBAR(x) ((x)&0x7f)
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#define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */
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#define ANNUL (1<<29)
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#define BPRED (1<<19) /* v9 */
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#define IMMED F3I(1)
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#define RD_G0 RD(~0)
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#define RS1_G0 RS1(~0)
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#define RS2_G0 RS2(~0)
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#define ANNUL (1 << 29)
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#define BPRED (1 << 19) /* V9. */
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#define IMMED F3I (1)
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#define RD_G0 RD (~0)
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#define RS1_G0 RS1 (~0)
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#define RS2_G0 RS2 (~0)
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extern const struct sparc_opcode sparc_opcodes[];
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extern const int sparc_num_opcodes;
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@ -231,11 +230,8 @@ extern const char *sparc_decode_prefetch (int);
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extern int sparc_encode_sparclet_cpreg (const char *);
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extern const char *sparc_decode_sparclet_cpreg (int);
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/*
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* Local Variables:
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* fill-column: 131
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* comment-column: 0
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* End:
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*/
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/* Local Variables:
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fill-column: 131
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comment-column: 0
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End: */
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/* end of sparc.h */
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