libs/newlib-cygwin
libs/newlib-cygwin
4
0
Fork 0
mirror of git://sourceware.org/git/newlib-cygwin.git synced 2025-01-19 04:49:25 +08:00
Code Issues Projects Releases Wiki Activity

Add MIPS SB1 machine

Browse Source
This commit is contained in:
Nick Clifton 2000-12-02 01:10:33 +00:00
parent f9fe8a8ead
commit 294f81d78d
4 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/elf/ChangeLog
View File

@ -6,6 +6,8 @@
* mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions. * mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions.
* mips.h (E_MIPS_MACH_SB1): New constant.
2000-11-30 Jan Hubicka <jh@suse.cz> 2000-11-30 Jan Hubicka <jh@suse.cz>
* common.h (EM_X86_64): New macro. * common.h (EM_X86_64): New macro.

1
include/elf/mips.h
View File

@ -163,6 +163,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
#define E_MIPS_MACH_4650 0x00850000 #define E_MIPS_MACH_4650 0x00850000
#define E_MIPS_MACH_4111 0x00880000 #define E_MIPS_MACH_4111 0x00880000
#define E_MIPS_MACH_MIPS32_4K 0x00890000 #define E_MIPS_MACH_MIPS32_4K 0x00890000
#define E_MIPS_MACH_SB1 0x008a0000
/* Processor specific section indices. These sections do not actually /* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these exist. Symbols with a st_shndx field corresponding to one of these

2
include/opcode/ChangeLog
View File

@ -28,6 +28,8 @@
* mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New
definitions. definitions.
* mips.h (CPU_SB1): New constant.
2000-10-20 Jakub Jelinek <jakub@redhat.com> 2000-10-20 Jakub Jelinek <jakub@redhat.com>
* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.

5
include/opcode/mips.h
View File

@ -359,9 +359,10 @@ struct mips_opcode
#define CPU_R10000 10000 #define CPU_R10000 10000
#define CPU_MIPS16 16 #define CPU_MIPS16 16
#define CPU_MIPS32 32 #define CPU_MIPS32 32
#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */ #define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K'. */
#define CPU_MIPS5 5 #define CPU_MIPS5 5
#define CPU_MIPS64 64 #define CPU_MIPS64 64
#define CPU_SB1 12310201 /* octal 'SB', 01. */
/* Test for membership in an ISA including chip specific ISAs. /* Test for membership in an ISA including chip specific ISAs.
INSN is pointer to an element of the opcode table; ISA is the INSN is pointer to an element of the opcode table; ISA is the
@ -369,7 +370,7 @@ struct mips_opcode
to test, or zero if no CPU specific ISA test is desired. to test, or zero if no CPU specific ISA test is desired.
The gp32 arg is set when you need to force 32-bit register usage on The gp32 arg is set when you need to force 32-bit register usage on
a machine with 64-bit registers; see the documentation under -mgp32 a machine with 64-bit registers; see the documentation under -mgp32
in the MIPS gas docs. */ in the MIPS gas docs. */
#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \ #define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
((((insn)->membership & isa) != 0 \ ((((insn)->membership & isa) != 0 \