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libgloss: arm: Clean up assembly syntax for clang compatibility
* Use mrc p15 co-processor instruction syntax. * Align register_names so that we can use ADR rather than ADRL. Change-Id: I005cd5a1fc55ec8eba90929c6c70d6a202b0746d
This commit is contained in:
Volodymyr Turanskyy
Richard Earnshaw
parent
8cc55d819b
commit
214d0b65dd
@ -60,7 +60,7 @@
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_rdimon_hw_init_hook:
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@ Only run the code on CPU 0 - otherwise spin
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mrc 15, 0, r4, cr0, cr0, 5 @ Read MPIDR
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mrc p15, 0, r4, cr0, cr0, 5 @ Read MPIDR
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ands r4, r4, #15
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spin:
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bne spin
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@ -70,15 +70,15 @@ spin:
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#ifdef __ARMEB__
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@ Setup for Big Endian
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setend be
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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mrc p15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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orr r4, r4, #(1<<25) @ Switch to Big Endian (Set SCTLR.EE)
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mcr p15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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#else
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@ Setup for Little Endian
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setend le
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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mrc p15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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bic r4, r4, #(1<<25) @ Switch to LE (unset SCTLR.EE)
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mcr p15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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#endif
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bl is_a15_a7
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@ -87,44 +87,44 @@ spin:
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@ Write zero into the ACTLR to turn everything on.
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itt eq
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moveq r4, #0
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mcreq 15, 0, r4, c1, c0, 1
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mcreq p15, 0, r4, c1, c0, 1
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isb
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@ For Cortex-A15 and Cortex-A7 only:
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@ Set ACTLR:SMP bit before enabling the caches and MMU,
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@ or performing any cache and TLB maintenance operations.
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ittt eq
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mrceq 15, 0, r4, c1, c0, 1 @ Read ACTLR
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mrceq p15, 0, r4, c1, c0, 1 @ Read ACTLR
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orreq r4, r4, #(1<<6) @ Enable ACTLR:SMP
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mcreq 15, 0, r4, c1, c0, 1 @ Write ACTLR
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mcreq p15, 0, r4, c1, c0, 1 @ Write ACTLR
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isb
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@ Setup for exceptions being taken to Thumb/ARM state
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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mrc p15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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#if defined(__thumb__)
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orr r4, r4, #(1 << 30) @ Enable SCTLR.TE
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#else
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bic r4, r4, #(1 << 30) @ Disable SCTLR.TE
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#endif
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mcr p15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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bl __reset_caches
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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mrc p15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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orr r4, r4, #(1<<22) @ Enable unaligned mode
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bic r4, r4, #2 @ Disable alignment faults
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bic r4, r4, #1 @ Disable MMU
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mcr p15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mov r4, #0
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mcr 15, 0, r4, cr8, cr7, 0 @ Write TLBIALL - Invaliidate unified
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mcr p15, 0, r4, cr8, cr7, 0 @ Write TLBIALL - Invaliidate unified
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@ TLB
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@ Setup MMU Primary table P=V mapping.
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mvn r4, #0
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mcr 15, 0, r4, cr3, cr0, 0 @ Write DACR
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mcr p15, 0, r4, cr3, cr0, 0 @ Write DACR
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mov r4, #0 @ Always use TTBR0, no LPAE
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mcr 15, 0, r4, cr2, cr0, 2 @ Write TTBCR
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mcr p15, 0, r4, cr2, cr0, 2 @ Write TTBCR
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adr r4, page_table_addr @ Load the base for vectors
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ldr r4, [r4]
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mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
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@ -138,17 +138,17 @@ spin:
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addne r4, r4, #0x58
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add r4, r4, #1
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mcr 15, 0, r4, cr2, cr0, 0 @ Write TTBR0
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mcr p15, 0, r4, cr2, cr0, 0 @ Write TTBR0
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mov r0, #34 @ 0x22 @ TR0 and TR1 - normal memory
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orr r0, r0, #(1 << 19) @ Shareable
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mcr 15, 0, r0, cr10, cr2, 0 @ Write PRRR
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mcr p15, 0, r0, cr10, cr2, 0 @ Write PRRR
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movw r0, #0x33
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movt r0, #0x33
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mcr 15, 0, r0, cr10, cr2, 1 @ Write NMRR
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mrc 15, 0, r0, cr1, cr0, 0 @ Read SCTLR
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mcr p15, 0, r0, cr10, cr2, 1 @ Write NMRR
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mrc p15, 0, r0, cr1, cr0, 0 @ Read SCTLR
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bic r0, r0, #(1 << 28) @ Clear TRE bit
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mcr 15, 0, r0, cr1, cr0, 0 @ Write SCTLR
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mcr p15, 0, r0, cr1, cr0, 0 @ Write SCTLR
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@ Now install the vector code - we move the Vector code from where it is
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@ in the image to be based at _rdimon_vector_base. We have to do this copy
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@ -166,25 +166,25 @@ copy_loop: @ Do the copy
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subs r7, r7, #4
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bne copy_loop
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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mrc p15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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bic r4, r4, #0x1000 @ Disable I Cache
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bic r4, r4, #4 @ Disable D Cache
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orr r4, r4, #1 @ Enable MMU
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bic r4, r4, #(1 << 28) @ Clear TRE bit
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mrc 15, 0, r4, cr1, cr0, 2 @ Read CPACR
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mcr p15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mrc p15, 0, r4, cr1, cr0, 2 @ Read CPACR
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orr r4, r4, #0x00f00000 @ Turn on VFP Co-procs
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bic r4, r4, #0x80000000 @ Clear ASEDIS bit
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mcr 15, 0, r4, cr1, cr0, 2 @ Write CPACR
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mcr p15, 0, r4, cr1, cr0, 2 @ Write CPACR
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isb
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mov r4, #0
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mcr 15, 0, r4, cr7, cr5, 4 @ Flush prefetch buffer
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mrc 15, 0, r4, cr1, cr0, 2 @ Read CPACR
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mcr p15, 0, r4, cr7, cr5, 4 @ Flush prefetch buffer
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mrc p15, 0, r4, cr1, cr0, 2 @ Read CPACR
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ubfx r4, r4, #20, #4 @ Extract bits [20, 23)
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cmp r4, #0xf @ If not all set then the CPU does not
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itt eq @ have FP or Advanced SIMD.
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moveq r4, #0x40000000 @ Enable FP and Advanced SIMD
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mcreq 10, 7, r4, cr8, cr0, 0 @ vmsr fpexc, r4
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mcreq p10, 7, r4, cr8, cr0, 0 @ vmsr fpexc, r4
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skip_vfp_enable:
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bl __enable_caches @ Turn caches on
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bx r10 @ Return to CRT startup routine
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@ -285,8 +285,9 @@ vector_common_2:
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bl out_string
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bl out_nl
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@ Dump the registers
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adrl r6, register_names
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@ Dump the registers, these are 4-byte aligned so we can reach them
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@ with a simple ADR here.
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adr r6, register_names
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mov r7, #0
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dump_r_loop:
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mov r0, r6
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@ -362,6 +363,8 @@ vector_names:
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.asciz "irq "
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.asciz "fiq "
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@ 4-byte aligned so that we can reach this with a simple ADR above.
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.p2align 2
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register_names:
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.asciz "apsr "
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.asciz "spsr "
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@ -386,14 +389,14 @@ register_names:
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@ Enable the caches
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__enable_caches:
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mov r0, #0
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mcr 15, 0, r0, cr8, cr7, 0 @ Invalidate all unified-TLB
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mcr p15, 0, r0, cr8, cr7, 0 @ Invalidate all unified-TLB
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mov r0, #0
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mcr 15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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mcr p15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor
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mrc p15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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orr r4, r4, #0x800 @ Enable branch predictor
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mcr 15, 0, r4, cr1, cr0, 0 @ Set SCTLR
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mcr p15, 0, r4, cr1, cr0, 0 @ Set SCTLR
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mov r5, lr @ Save LR as we're going to BL
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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mrc p15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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bl init_cpu_client_enable_icache
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cmp r0, #0
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it ne
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@ -402,24 +405,24 @@ __enable_caches:
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cmp r0, #0
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it ne
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orrne r4, r4, #4
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mcr 15, 0, r4, cr1, cr0, 0 @ Enable D-Cache
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mcr p15, 0, r4, cr1, cr0, 0 @ Enable D-Cache
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bx r5 @ Return
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__reset_caches:
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mov ip, lr @ Save LR
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mov r0, #0
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mcr 15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor
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mrc 15, 0, r6, cr1, cr0, 0 @ Read SCTLR
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mrc 15, 0, r0, cr1, cr0, 0 @ Read SCTLR!
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mcr p15, 0, r0, cr7, cr5, 6 @ Invalidate branch predictor
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mrc p15, 0, r6, cr1, cr0, 0 @ Read SCTLR
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mrc p15, 0, r0, cr1, cr0, 0 @ Read SCTLR!
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bic r0, r0, #0x1000 @ Disable I cache
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mcr 15, 0, r0, cr1, cr0, 0 @ Write SCTLR
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mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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mcr p15, 0, r0, cr1, cr0, 0 @ Write SCTLR
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mrc p15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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tst r0, #3 @ Harvard Cache?
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mov r0, #0
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it ne
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mcrne 15, 0, r0, cr7, cr5, 0 @ Invalidate Instruction Cache?
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mcrne p15, 0, r0, cr7, cr5, 0 @ Invalidate Instruction Cache?
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mrc 15, 0, r1, cr1, cr0, 0 @ Read SCTLR (again!)
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mrc p15, 0, r1, cr1, cr0, 0 @ Read SCTLR (again!)
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orr r1, r1, #0x800 @ Enable branch predictor
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@ If we're not enabling caches we have
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@ -436,25 +439,25 @@ __reset_caches:
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cmpeq r0, #0
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beq Finished1
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mcr 15, 0, r1, cr1, cr0, 0 @ Write SCTLR (turn on Branch predictor & I-cache)
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mcr p15, 0, r1, cr1, cr0, 0 @ Write SCTLR (turn on Branch predictor & I-cache)
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mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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mrc p15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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ands r3, r0, #0x7000000
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lsr r3, r3, #23 @ Total cache levels << 1
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beq Finished1
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mov lr, #0 @ lr = cache level << 1
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Loop11:
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mrc 15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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mrc p15, 1, r0, cr0, cr0, 1 @ Read CLIDR
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add r2, lr, lr, lsr #1 @ r2 holds cache 'set' position
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lsr r1, r0, r2 @ Bottom 3-bits are Ctype for this level
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and r1, r1, #7 @ Get those 3-bits alone
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cmp r1, #2
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blt Skip1 @ No cache or only I-Cache at this level
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mcr 15, 2, lr, cr0, cr0, 0 @ Write CSSELR
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mcr p15, 2, lr, cr0, cr0, 0 @ Write CSSELR
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mov r1, #0
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isb sy
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mrc 15, 1, r1, cr0, cr0, 0 @ Read CCSIDR
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mrc p15, 1, r1, cr0, cr0, 0 @ Read CCSIDR
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and r2, r1, #7 @ Extract line length field
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add r2, r2, #4 @ Add 4 for the line length offset (log2 16 bytes)
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movw r0, #0x3ff
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@ -469,8 +472,8 @@ Loop31:
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orr r1, r1, r5, lsl r2 @ factor in set number
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tst r6, #4 @ D-Cache on?
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ite eq
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mcreq 15, 0, r1, cr7, cr6, 2 @ No - invalidate by set/way
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mcrne 15, 0, r1, cr7, cr14, 2 @ yes - clean + invalidate by set/way
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mcreq p15, 0, r1, cr7, cr6, 2 @ No - invalidate by set/way
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mcrne p15, 0, r1, cr7, cr14, 2 @ yes - clean + invalidate by set/way
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subs r7, r7, #1 @ Decrement way number
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bge Loop31
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subs r5, r5, #1 @ Decrement set number
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@ -481,18 +484,18 @@ Skip1:
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bgt Loop11
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Finished1:
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@ Now we know the caches are clean we can:
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mrc 15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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mrc p15, 0, r4, cr1, cr0, 0 @ Read SCTLR
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bic r4, r4, #4 @ Disable D-Cache
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mcr 15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mcr p15, 0, r4, cr1, cr0, 0 @ Write SCTLR
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mov r4, #0
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mcr 15, 0, r4, cr7, cr5, 6 @ Write BPIALL
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mcr p15, 0, r4, cr7, cr5, 6 @ Write BPIALL
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bx ip @ Return
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@ Set Z if this is a Cortex-A15 or Cortex_A7
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@ Other flags corrupted
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is_a15_a7:
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mrc 15, 0, r8, c0, c0, 0
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mrc p15, 0, r8, c0, c0, 0
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movw r9, #0xfff0
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movt r9, #0xff0f
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and r8, r8, r9
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