[ bfd/ChangeLog ]
2002-12-30 Chris Demetriou <cgd@broadcom.com> * aoutx.h (NAME(aout,machine_type)): Add bfd_mach_mipsisa32r2 case. * archures.c (bfd_mach_mipsisa32r2): New define. * bfd-in2.h: Regenerate. * cpu-mips.c (I_mipsisa32r2): New enum value. (arch_info_struct): Add entry for I_mipsisa32r2. * elfxx-mips.c (elf_mips_isa, _bfd_elf_mips_mach) (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_32R2. (_bfd_mips_elf_final_write_processing): Add bfd_mach_mipsisa32r2 case. (_bfd_mips_elf_merge_private_bfd_data): Handle merging of binaries marked as using MIPS32 Release 2. [ binutils/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * doc/binutils.texi (objdump): Note MIPS HWR (Hardware Register) changes in MIPS -M options. [ gas/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * configure.in: Recognize mipsisa32r2, mipsisa32r2el, and CPU variants. * configure: Regenerate. * config/tc-mips.c (ISA_HAS_DROR, ISA_HAS_ROR): New defines. (macro_build): Handle "K" operand. (macro2): Use ISA_HAS_DROR and ISA_HAS_ROR in the places where CPU_HAS_DROR and CPU_HAS_ROR are currently used. (mips_ip): New variable "lastpos", and implement "+A", "+B", and "+C" operands for MIPS32 Release 2 ins/ext instructions. Implement "K" operand for MIPS32 Release 2 rdhwr instruction. (validate_mips_insn): Implement "+" as a way to extend the allowed operands, and implement "K", "+A", "+B", and "+C" operands. (OPTION_MIPS32R2): New define. (md_longopts): Add entry for OPTION_MIPS32R2. (OPTION_ELF_BASE): Adjust to accomodate OPTIONS_MIPS32R2. (md_parse_option): Handle OPTION_MIPS32R2. (s_mipsset): Reimplement handling of ".set mipsN" options and add support for ".set mips32r2". (mips_cpu_info_table): Add entry for "mips32r2" (MIPS32 Release 2). (md_show_usage): Document "-mips32r2" option. * doc/as.texinfo: Document "-mips32r2" option. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * gas/mips/cp0-names-mips32r2.d: New test. * gas/mips/hwr-names-mips32r2.d: New test. * gas/mips/hwr-names-numeric.d: New test. * gas/mips/hwr-names.s: New test source file. * gas/mips/mips32r2.d: New test. * gas/mips/mips32r2.s: New test source file. * gas/mips/mips32r2-ill.l: New test. * gas/mips/mips32r2-ill.s: New test source file. * gas/mips/mips.exp: Add mips32r2 architecture data array entry. Run new tests mentioned above. [ include/elf/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips.h (E_MIPS_ARCH_32R2): New define. [ include/opcode/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips.h: Document "+" as the start of two-character operand type names, and add new "K", "+A", "+B", and "+C" operand types. (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB) (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New defines. [ opcodes/ChangeLog ] 2002-12-30 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric) (mips_hwr_names_mips3264r2): New arrays. (mips_arch_choice): New "hwr_names" member. (mips_arch_choices): Adjust for structure change, and add a new entry for "mips32r2" ISA. (mips_hwr_names): New variable. (set_default_mips_dis_options): Set mips_hwr_names. (parse_mips_dis_option): New "hwr-names" option which sets mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names. (print_insn_arg): Change return type to "int" and use that to indicate number of characters consumed. Add support for "+" operand extension character, "+A", "+B", "+C", and "K" operands. (print_insn_mips): Adjust for changes to print_insn_arg. (print_mips_disassembler_options): Adjust for "hwr-names" addition and "reg-names" change. * mips-opc (I33): New define (shorthand for INSN_ISA32R2). (mips_builtin_opcodes): Note that "nop" and "ssnop" are special forms of "sll". Add new MIPS32 Release 2 instructions: ehb, di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2, rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh. Note that hardware rotate instructions (ror, rorv) can be used on MIPS32 Release 2, and add the official mnemonics for them (rotr, rotrv) and the similar "rotl" mnemonic for left-rotate.
This commit is contained in:
Chris Demetriou
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7332684662
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1de386c0a1
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@ -1,3 +1,7 @@
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2002-12-30 Chris Demetriou <cgd@broadcom.com>
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* mips.h (E_MIPS_ARCH_32R2): New define.
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2002-12-24 Dmitry Diky <diwil@mail.ru>
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* common.h: Define msp430 machine numbers.
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@ -145,6 +145,9 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
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/* -mips64 code. */
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#define E_MIPS_ARCH_64 0x60000000
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/* -mips32r2 code. */
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#define E_MIPS_ARCH_32R2 0x70000000
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/* The ABI of the file. Also see EF_MIPS_ABI2 above. */
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#define EF_MIPS_ABI 0x0000F000
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@ -1,3 +1,11 @@
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2002-12-30 Chris Demetriou <cgd@broadcom.com>
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* mips.h: Document "+" as the start of two-character operand
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type names, and add new "K", "+A", "+B", and "+C" operand types.
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(OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB)
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(OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New
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defines.
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2002-12-24 Dmitry Diky <diwil@mail.ru>
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* msp430.h: New file. Defines msp430 opcodes.
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@ -142,6 +142,10 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_SH_VECBYTE 22
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#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
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#define OP_SH_VECALIGN 21
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#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
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#define OP_SH_INSMSB 11
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#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
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#define OP_SH_EXTMSBD 11
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#define OP_OP_COP0 0x10
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#define OP_OP_COP1 0x11
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@ -228,6 +232,12 @@ struct mips_opcode
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"J" 19 bit wait function code (OP_*_CODE19)
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"x" accept and ignore register name
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"z" must be zero register
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"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
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"+A" 5 bit ins/ext position/lsb (OP_*_SHAMT)
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"+B" 5 bit "ins" size spec (OP_*_INSMSB). Requires that "+A"
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occur first!
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"+C" 5 bit "ext" msbd spec (OP_*_EXTMSBD). Requires that "+A"
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occur first!
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Floating point instructions:
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"D" 5 bit destination register (OP_*_FD)
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@ -268,11 +278,16 @@ struct mips_opcode
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"()" parens surrounding optional value
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"," separates operands
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"[]" brackets around index for vector-op scalar operand specifier (vr5400)
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"+" Start of extension sequence.
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Characters used so far, for quick reference when adding more:
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"%[]<>(),"
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"ABCDEFGHIJLMNOPQRSTUVWXYZ"
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"%[]<>(),+"
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"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
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"abcdefhijklopqrstuvwxz"
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Extension character sequences used so far ("+" followed by the
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following), for quick reference when adding more:
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"ABC"
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*/
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/* These are the bits which may be set in the pinfo field of an
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@ -364,6 +379,7 @@ struct mips_opcode
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#define INSN_ISA5 0x00000100
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#define INSN_ISA32 0x00000200
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#define INSN_ISA64 0x00000400
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#define INSN_ISA32R2 0x00000800
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/* Masks used for MIPS-defined ASEs. */
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#define INSN_ASE_MASK 0x0000f000
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@ -406,9 +422,12 @@ struct mips_opcode
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#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
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#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
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#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
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#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
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#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
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#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
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/* CPU defines, use instead of hardcoding processor number. Keep this
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in sync with bfd/archures.c in order for machine selection to work. */
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#define CPU_UNKNOWN 0 /* Gas internal use. */
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@ -432,6 +451,7 @@ struct mips_opcode
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#define CPU_R12000 12000
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#define CPU_MIPS16 16
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#define CPU_MIPS32 32
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#define CPU_MIPS32R2 33
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#define CPU_MIPS5 5
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#define CPU_MIPS64 64
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#define CPU_SB1 12310201 /* octal 'SB', 01. */
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