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libgloss: bfin: sync headers to VDSP 5.0 Update 8 

A new release of VDSP means syncing random updates to the libgloss headers.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Michael Frysinger 2010-10-17 23:52:49 +00:00
parent 0e66e62668
commit 1cfc2fea73
83 changed files with 952 additions and 405 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
libgloss/ChangeLog
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@ -1,3 +1,48 @@
2010-10-17 Mike Frysinger <vapier@gentoo.org>
* bfin/include/blackfin.h, bfin/include/builtins.h,
bfin/include/ccblkfn.h, bfin/include/cdefBF512.h,
bfin/include/cdefBF514.h, bfin/include/cdefBF516.h,
bfin/include/cdefBF518.h, bfin/include/cdefBF51x_base.h,
bfin/include/cdefBF522.h, bfin/include/cdefBF523.h,
bfin/include/cdefBF524.h, bfin/include/cdefBF525.h,
bfin/include/cdefBF526.h, bfin/include/cdefBF527.h,
bfin/include/cdefBF52x_base.h, bfin/include/cdefBF531.h,
bfin/include/cdefBF532.h, bfin/include/cdefBF533.h,
bfin/include/cdefBF534.h, bfin/include/cdefBF535.h,
bfin/include/cdefBF536.h, bfin/include/cdefBF537.h,
bfin/include/cdefBF538.h, bfin/include/cdefBF539.h,
bfin/include/cdefBF53x.h, bfin/include/cdefBF542.h,
bfin/include/cdefBF542M.h, bfin/include/cdefBF544.h,
bfin/include/cdefBF544M.h, bfin/include/cdefBF547.h,
bfin/include/cdefBF547M.h, bfin/include/cdefBF548.h,
bfin/include/cdefBF548M.h, bfin/include/cdefBF549.h,
bfin/include/cdefBF549M.h, bfin/include/cdefBF54x_base.h,
bfin/include/cdefBF561.h, bfin/include/cdef_LPBlackfin.h,
bfin/include/cdefblackfin.h, bfin/include/cplb.h,
bfin/include/cplbtab.h, bfin/include/defBF512.h,
bfin/include/defBF514.h, bfin/include/defBF516.h,
bfin/include/defBF518.h, bfin/include/defBF51x_base.h,
bfin/include/defBF522.h, bfin/include/defBF523.h,
bfin/include/defBF524.h, bfin/include/defBF525.h,
bfin/include/defBF526.h, bfin/include/defBF527.h,
bfin/include/defBF52x_base.h, bfin/include/defBF531.h,
bfin/include/defBF532.h, bfin/include/defBF533.h,
bfin/include/defBF534.h, bfin/include/defBF535.h,
bfin/include/defBF536.h, bfin/include/defBF537.h,
bfin/include/defBF538.h, bfin/include/defBF539.h,
bfin/include/defBF542.h, bfin/include/defBF542M.h,
bfin/include/defBF544.h, bfin/include/defBF544M.h,
bfin/include/defBF547.h, bfin/include/defBF547M.h,
bfin/include/defBF548.h, bfin/include/defBF548M.h,
bfin/include/defBF549.h, bfin/include/defBF549M.h,
bfin/include/defBF54x_base.h, bfin/include/defBF561.h,
bfin/include/defblackfin.h, bfin/include/sysreg.h,
bfin/include/sys/anomaly_macros_rtl.h, bfin/include/sys/excause.h,
bfin/include/sys/exception.h, bfin/include/sys/mc_typedef.h,
bfin/include/sys/platform.h, bfin/include/sys/pll.h:
Update to Visual DSP 5.0 Update 8.
2010-10-16 Mike Frysinger <vapier@gentoo.org>
* bfin/Makefile.in (BOARD_SCRIPTS): Add bf592.ld.

2
libgloss/bfin/include/blackfin.h
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@ -1,6 +1,4 @@
/*
* Copyright (C) 2008 Analog Devices, Inc.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this

295
libgloss/bfin/include/builtins.h Normal file
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@ -0,0 +1,295 @@
/*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply.
*/
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_2_4)
#pragma diag(suppress:misra_rule_5_3)
#pragma diag(suppress:misra_rule_6_3)
#pragma diag(suppress:misra_rule_8_1)
#pragma diag(suppress:misra_rule_8_8)
#pragma diag(suppress:misra_rule_8_5)
#pragma diag(suppress:misra_rule_19_7)
#pragma diag(suppress:misra_rule_19_15)
#pragma diag(suppress:misra_rule_20_2)
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(__NO_BUILTIN)
/* VDSP -> GCC glue */
#define __builtin_NOP() __asm__ __volatile__ ("NOP;")
#define __builtin_cli() ({ unsigned int __rval; __asm__ __volatile__ ("cli %0;" : "=r"(__rval)); __rval; })
#define __builtin_sti(x) __asm__ __volatile__ ("sti %0;" : : "r"(x))
#define __builtin_idle() __asm__ __volatile__ ("IDLE;")
#define __builtin_raise(x) __asm__ __volatile__ ("raise %0;" : : "r"(x))
#define __builtin_excpt(x) __asm__ __volatile__ ("excpt %0;" : : "r"(x))
#define __builtin_prefetch(x) __asm__ __volatile__ ("PREFETCH[%0];" : : "p"(x))
#define __builtin_prefetchmodup(x) ({ void *__p = &(x); __asm__ __volatile__ ("PREFETCH[%0++];" : "+p"(__p)); __p; })
#define __builtin_flushinv(x) __asm__ __volatile__ ("FLUSHINV[%0];" : : "p"(x))
#define __builtin_flushinvmodup(x) ({ void *__p = &(x); __asm__ __volatile__ ("FLUSHINV[%0++];" : "+p"(__p)); __p; })
#define __builtin_flush(x) __asm__ __volatile__ ("FLUSH[%0];" : : "p"(x))
#define __builtin_flushmodup(x) ({ void *__p = &(x); __asm__ __volatile__ ("FLUSH[%0++];" : "+p"(__p)); __p; })
#define __builtin_iflush(x) __asm__ __volatile__ ("IFLUSH[%0];" : : "p"(x))
#define __builtin_iflushmodup(x) ({ void *__p = &(x); __asm__ __volatile__ ("IFLUSH[%0++];" : "+p"(__p)); __p; })
#define __builtin_csync() __builtin_bfin_csync()
#define __builtin_ssync() __builtin_bfin_ssync()
#endif /* __NO_BUILTIN */
#if !defined(__NO_BUILTIN) && !defined(__NO_SHORTNAMES)
#if (!defined(__DEFINED_NOP) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_NOP)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_NOP))))
#define __DEFINED_NOP
/* Insert a normal 16 bit NOP, which is treated as volatile.
*/
#pragma inline
#pragma always_inline
static void NOP(void) {
__builtin_NOP();
}
#endif /* __DEFINED_NOP */
#if (!defined(__DEFINED_CLI) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_CLI)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_CLI))))
#define __DEFINED_CLI
#pragma inline
#pragma always_inline
static unsigned int cli(void) {
unsigned int __rval = __builtin_cli();
return __rval;
}
#endif /* __DEFINED_CLI */
#if (!defined(__DEFINED_STI) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_STI)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_STI))))
#define __DEFINED_STI
#pragma inline
#pragma always_inline
static void sti(unsigned int __a) {
__builtin_sti(__a);
}
#endif /* __DEFINED_STI */
#if (!defined(__DEFINED_IDLE) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_IDLE)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_IDLE))))
#define __DEFINED_IDLE
#pragma inline
#pragma always_inline
static void idle(void) {
__builtin_idle();
}
#endif /* __DEFINED_IDLE */
#if (!defined(__DEFINED_RAISE_INTR) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_RAISE_INTR)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_RAISE_INTR))))
#define __DEFINED_RAISE_INTR
#define raise_intr(A) (__builtin_raise((A)))
#endif /* __DEFINED_RAISE_INTR */
#if (!defined(__DEFINED_EXCPT) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_EXCPT)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_EXCPT))))
#define __DEFINED_EXCPT
#define excpt(A) (__builtin_excpt((A)))
#endif /* __DEFINED_EXCPT */
#if (!defined(__DEFINED_PREFETCH) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_PREFETCH)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_PREFETCH))))
#define __DEFINED_PREFETCH
#pragma inline
#pragma always_inline
static void prefetch(void * __a) {
__builtin_prefetch(__a);
}
#endif /* __DEFINED_PREFETCH */
#if (!defined(__DEFINED_PREFETCHMODUP) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_PREFETCHMODUP)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_PREFETCHMODUP))))
#define __DEFINED_PREFETCHMODUP
#pragma inline
#pragma always_inline
static void * prefetchmodup(void * __a) {
void * __rval = __builtin_prefetchmodup(__a);
return __rval;
}
#endif /* __DEFINED_PREFETCHMODUP */
#if (!defined(__DEFINED_FLUSHINV) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_FLUSHINV)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_FLUSHINV))))
#define __DEFINED_FLUSHINV
#pragma inline
#pragma always_inline
static void flushinv(void * __a) {
__builtin_flushinv(__a);
}
#endif /* __DEFINED_FLUSHINV */
#if (!defined(__DEFINED_FLUSHINVMODUP) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_FLUSHINVMODUP)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_FLUSHINVMODUP))))
#define __DEFINED_FLUSHINVMODUP
#pragma inline
#pragma always_inline
static void * flushinvmodup(void * __a) {
void * __rval = __builtin_flushinvmodup(__a);
return __rval;
}
#endif /* __DEFINED_FLUSHINVMODUP */
#if (!defined(__DEFINED_FLUSH) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_FLUSH)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_FLUSH))))
#define __DEFINED_FLUSH
#pragma inline
#pragma always_inline
static void flush(void * __a) {
__builtin_flush(__a);
}
#endif /* __DEFINED_FLUSH */
#if (!defined(__DEFINED_FLUSHMODUP) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_FLUSHMODUP)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_FLUSHMODUP))))
#define __DEFINED_FLUSHMODUP
#pragma inline
#pragma always_inline
static void * flushmodup(void * __a) {
void * __rval = __builtin_flushmodup(__a);
return __rval;
}
#endif /* __DEFINED_FLUSHMODUP */
#if (!defined(__DEFINED_IFLUSH) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_IFLUSH)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_IFLUSH))))
#define __DEFINED_IFLUSH
#pragma inline
#pragma always_inline
static void iflush(void * __a) {
__builtin_iflush(__a);
}
#endif /* __DEFINED_IFLUSH */
#if (!defined(__DEFINED_IFLUSHMODUP) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_IFLUSHMODUP)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_IFLUSHMODUP))))
#define __DEFINED_IFLUSHMODUP
#pragma inline
#pragma always_inline
static void * iflushmodup(void * __a) {
void * __rval = __builtin_iflushmodup(__a);
return __rval;
}
#endif /* __DEFINED_IFLUSHMODUP */
#if (!defined(__DEFINED_CSYNC) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_CSYNC)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_CSYNC))))
#define __DEFINED_CSYNC
/* generate a csync instruction protected by CLI/STI for anomaly 05-00-0312;
** you can generate an unprotected csync by using csync_int
*/
#pragma inline
#pragma always_inline
static void csync(void) {
__builtin_csync();
}
#endif /* __DEFINED_CSYNC */
#if (!defined(__DEFINED_SSYNC) && \
((defined(__SPECIFIC_NAMES) && defined(__ENABLE_SSYNC)) || \
(!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_SSYNC))))
#define __DEFINED_SSYNC
/* generate a ssync instruction protected by CLI/STI for anomaly 05-00-0312;
** you can generate an unprotected ssync by using ssync_int
*/
#pragma inline
#pragma always_inline
static void ssync(void) {
__builtin_ssync();
}
#endif /* __DEFINED_SSYNC */
#endif /* __NO_BUILTIN */
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif
#ifdef __cplusplus
}
#endif

13
libgloss/bfin/include/ccblkfn.h
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@ -10,5 +10,14 @@
* they apply.
*/
/* For now, a dummy header file, fill in with gcc-specific items later.
Header files from VisualDSP require that this exists. */
#ifndef _CCBLKFN_H
#define _CCBLKFN_H
#include <stdlib.h>
#include <builtins.h>
#include <sys/anomaly_macros_rtl.h>
#include <sys/mc_typedef.h>
#endif

2
libgloss/bfin/include/cdefBF512.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF514.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF516.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF518.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

4
libgloss/bfin/include/cdefBF51x_base.h
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@ -13,7 +13,7 @@
/*
** cdefBF51x_base.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -100,7 +100,6 @@
#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_MSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
@ -574,7 +573,6 @@
#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_MSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)

2
libgloss/bfin/include/cdefBF522.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF523.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF524.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF525.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF526.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF527.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

4
libgloss/bfin/include/cdefBF52x_base.h
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@ -13,7 +13,7 @@
/*
** cdefBF52x_base.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -109,7 +109,6 @@
#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_MSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
@ -569,7 +568,6 @@
#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_MSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)

2
libgloss/bfin/include/cdefBF531.h
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@ -14,7 +14,7 @@
*
* cdefBF531.h
*
* Copyright (C) 2008 Analog Devices, Inc.
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

3
libgloss/bfin/include/cdefBF532.h
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@ -14,7 +14,7 @@
*
* cdefBF532.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2001-2009 Analog Devices, Inc. All rights reserved.
*
************************************************************************/
@ -87,7 +87,6 @@
#define pUART_LCR ((volatile unsigned short *)UART_LCR)
#define pUART_MCR ((volatile unsigned short *)UART_MCR)
#define pUART_LSR ((volatile unsigned short *)UART_LSR)
/* #define UART_MSR */
#define pUART_SCR ((volatile unsigned short *)UART_SCR)
#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)

2
libgloss/bfin/include/cdefBF533.h
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@ -14,7 +14,7 @@
*
* cdefBF533.h
*
* Copyright (C) 2008 Analog Devices, Inc.
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

4
libgloss/bfin/include/cdefBF534.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2005-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -94,7 +94,6 @@
#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_MSR ((volatile unsigned short *)UART0_LSR)
#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
@ -554,7 +553,6 @@
#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_MSR ((volatile unsigned short *)UART1_LSR)
#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)

2
libgloss/bfin/include/cdefBF535.h
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@ -14,7 +14,7 @@
*
* cdefBF535.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2002-2005 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/cdefBF536.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
** Copyright (C) 2005 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF537.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
** Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF538.h
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@ -14,7 +14,7 @@
*
* cdefBF538.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2006-2009 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/cdefBF539.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/cdefBF53x.h
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@ -14,7 +14,7 @@
*
* cdefBF53x.h
*
* Copyright (C) 2008 Analog Devices, Inc.
* (c) Copyright 2002-2006 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/cdefBF542.h
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@ -13,7 +13,7 @@
/*
** cdefBF542.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/cdefBF542M.h
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@ -13,7 +13,7 @@
/*
** cdefBF542M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
************************************************************************************/
#ifndef _CDEF_BF542M_H
#define _CDEF_BF542M_H
#include <cdefBF542.h>
#endif /* _CDEF_BF542M_H */

2
libgloss/bfin/include/cdefBF544.h
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@ -13,7 +13,7 @@
/*
** cdefBF544.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/cdefBF544M.h
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@ -13,7 +13,7 @@
/*
** cdefBF544M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
************************************************************************************/
#ifndef _CDEF_BF544M_H
#define _CDEF_BF544M_H
#include <cdefBF544.h>
#endif /* _CDEF_BF544M_H */

2
libgloss/bfin/include/cdefBF547.h
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@ -13,7 +13,7 @@
/*
** cdefBF547.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2007 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/cdefBF547M.h
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@ -13,7 +13,7 @@
/*
** cdefBF547M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
************************************************************************************/
#ifndef _CDEF_BF547M_H
#define _CDEF_BF547M_H
#include <cdefBF547.h>
#endif /* _CDEF_BF547M_H */

2
libgloss/bfin/include/cdefBF548.h
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@ -13,7 +13,7 @@
/*
** cdefBF548.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/cdefBF548M.h
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@ -13,7 +13,7 @@
/*
** cdefBF548M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
************************************************************************************/
#ifndef _CDEF_BF548M_H
#define _CDEF_BF548M_H
#include <cdefBF548.h>
#endif /* _CDEF_BF548M_H */

2
libgloss/bfin/include/cdefBF549.h
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@ -13,7 +13,7 @@
/*
** cdefBF549.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/cdefBF549M.h
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@ -13,7 +13,7 @@
/*
** cdefBF549M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
************************************************************************************/
#ifndef _CDEF_BF549M_H
#define _CDEF_BF549M_H
#include <cdefBF549.h>
#endif /* _CDEF_BF549M_H */

2
libgloss/bfin/include/cdefBF54x_base.h
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@ -13,7 +13,7 @@
/*
** cdefBF54x_base.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

3
libgloss/bfin/include/cdefBF561.h
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@ -14,7 +14,7 @@
*
* cdefBF561.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2001-2009 Analog Devices, Inc. All rights reserved.
*
************************************************************************/
@ -114,7 +114,6 @@
#define pUART_LCR ((volatile unsigned short *)UART_LCR)
#define pUART_MCR ((volatile unsigned short *)UART_MCR)
#define pUART_LSR ((volatile unsigned short *)UART_LSR)
#define pUART_MSR ((volatile unsigned short *)UART_MSR)
#define pUART_SCR ((volatile unsigned short *)UART_SCR)
#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)

2
libgloss/bfin/include/cdef_LPBlackfin.h
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@ -14,7 +14,7 @@
*
* cdef_LPBlackfin.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2002-2005 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/cdefblackfin.h
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@ -14,7 +14,7 @@
*
* cdefblackfin.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2002-2005 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/cplb.h
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@ -14,7 +14,7 @@
*
* cplb.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2002-2007 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/cplbtab.h
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@ -18,7 +18,7 @@
*
* cplbtab.h
*
* Copyright (C) 2008 Analog Devices, Inc.
* (c) Copyright 2002-2007 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/defBF512.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF514.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF516.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF518.h
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@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

225
libgloss/bfin/include/defBF51x_base.h
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@ -13,7 +13,7 @@
/*
** defBF51x_base.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -31,6 +31,7 @@
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#include <stdint.h>
#endif /* _MISRA_RULES */
@ -101,7 +102,6 @@
#define UART0_LCR 0xFFC0040C /* Line Control Register */
#define UART0_MCR 0xFFC00410 /* Modem Control Register */
#define UART0_LSR 0xFFC00414 /* Line Status Register */
#define UART0_MSR 0xFFC00418 /* Modem Status Register */
#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART0_GCTL 0xFFC00424 /* Global Control Register */
@ -567,7 +567,6 @@
#define UART1_LCR 0xFFC0200C /* Line Control Register */
#define UART1_MCR 0xFFC02010 /* Modem Control Register */
#define UART1_LSR 0xFFC02014 /* Line Status Register */
#define UART1_MSR 0xFFC02018 /* Modem Status Register */
#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
#define UART1_GCTL 0xFFC02024 /* Global Control Register */
@ -750,19 +749,15 @@
#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
/* SYSCR Masks */
#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
#define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */
#define BMODE_UART1HOST 0x0008 /* Boot from UART1 host */
#define BMODE_SDRAMMEM 0x000A /* Boot from SDRAM memory (warm boot) */
#define BMODE_OTPMEM 0x000B /* Boot from OTP memory */
#define BMODE_HOSTDMA_ACK 0x000E /* Boot from 16-bit host DMA (ACK mode) */
#define BMODE_HOSTDMA_INT 0x000F /* Boot from 8-bit host DMA (INT mode) */
#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
#define BMODE_BYPASS 0x0000 /* No boot mode */
#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
#define BMODE_SPI0MEM_INT 0x0002 /* Boot from internal SPI0 memory */
#define BMODE_SPI0MEM_EXT 0x0003 /* Boot from external SPI0 memory */
#define BMODE_SPI0HOST 0x0004 /* Boot from SPI0 host (slave mode) */
#define BMODE_OTPMEM 0x0005 /* Boot from OTP memory */
#define BMODE_SDRAMMEM 0x0006 /* Boot from SDRAM memory (warm boot) */
#define BMODE_UART0HOST 0x0007 /* Boot from UART0 host */
#define BMODE 0x0007 /* Boot Mode. Mirror of BMODE Mode Pins */
#define BCODE 0x00F0
#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
@ -771,11 +766,6 @@
#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
#define DCB1_PRIO 0x0100 /* DCB1 requests are urgent */
#define DCB_ROT_PRIO 0x0200 /* enable rotating DCB priority */
#define DEB1_PRIO 0x0400 /* DEB1 requests are urgent */
#define DEB_ROT_PRIO 0x0800 /* enable rotating DEB priority */
#define WURESET 0x1000 /* wakeup event since last hardware reset */
#define DFRESET 0x2000 /* recent reset was due to a double fault event */
#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
@ -861,129 +851,130 @@
#define _MF7 7
#endif /* _MISRA_RULES */
/* SIC_IAR0 Macros */
#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
#define P1_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #1 assigned IVG #x */
#define P2_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #2 assigned IVG #x */
#define P3_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #3 assigned IVG #x */
#define P4_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #4 assigned IVG #x */
#define P5_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #5 assigned IVG #x */
#define P6_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #6 assigned IVG #x */
#define P7_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #7 assigned IVG #x */
/* SIC_IAR0 Macros*/
#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Macros */
#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
#define P9_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #9 assigned IVG #x */
#define P10_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #10 assigned IVG #x */
#define P11_IVG(x) /* Reserved */
#define P12_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #12 assigned IVG #x */
#define P13_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #13 assigned IVG #x */
#define P14_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #14 assigned IVG #x */
#define P15_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #15 assigned IVG #x */
/* SIC_IAR1 Macros*/
#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #10 assigned IVG #x */
#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #11 assigned IVG #x */
#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #12 assigned IVG #x */
#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #13 assigned IVG #x */
/* SIC_IAR2 Macros */
#define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */
#define P17_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #17 assigned IVG #x */
#define P18_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #18 assigned IVG #x */
#define P19_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #19 assigned IVG #x */
#define P20_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #20 assigned IVG #x */
#define P21_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #21 assigned IVG #x */
#define P22_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #22 assigned IVG #x */
#define P23_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #23 assigned IVG #x */
/* SIC_IAR2 Macros*/
#define P14_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #14 assigned IVG #x */
#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #15 assigned IVG #x */
#define P16_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #16 assigned IVG #x */
#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #17 assigned IVG #x */
#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #18 assigned IVG #x */
#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #19 assigned IVG #x */
#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #20 assigned IVG #x */
#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #21 assigned IVG #x */
/* SIC_IAR3 Macros */
#define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */
#define P25_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #25 assigned IVG #x */
#define P26_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #26 assigned IVG #x */
#define P27_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #27 assigned IVG #x */
#define P28_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #28 assigned IVG #x */
#define P29_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #29 assigned IVG #x */
#define P30_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #30 assigned IVG #x */
#define P31_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #31 assigned IVG #x */
/* SIC_IAR3 Macros*/
#define P22_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #22 assigned IVG #x */
#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #23 assigned IVG #x */
#define P24_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #24 assigned IVG #x */
#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #25 assigned IVG #x */
#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #26 assigned IVG #x */
#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #27 assigned IVG #x */
#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #28 assigned IVG #x */
#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #29 assigned IVG #x */
/* SIC_IAR4 Macros */
#define P32_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #32 assigned IVG #x */
#define P33_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #33 assigned IVG #x */
#define P34_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #34 assigned IVG #x */
#define P35_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #35 assigned IVG #x */
#define P36_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #36 assigned IVG #x */
#define P37_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #37 assigned IVG #x */
#define P38_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #38 assigned IVG #x */
#define P39_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #39 assigned IVG #x */
/* SIC_IAR4 Macros*/
#define P30_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #30 assigned IVG #x */
#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #31 assigned IVG #x */
#define P32_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #32 assigned IVG #x */
#define P33_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #33 assigned IVG #x */
#define P34_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #34 assigned IVG #x */
#define P35_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #35 assigned IVG #x */
#define P36_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #36 assigned IVG #x */
#define P37_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #37 assigned IVG #x */
/* SIC_IAR5 Macros */
#define P40_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #40 assigned IVG #x */
#define P41_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #41 assigned IVG #x */
#define P42_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #42 assigned IVG #x */
#define P43_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #43 assigned IVG #x */
#define P44_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #44 assigned IVG #x */
#define P45_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #45 assigned IVG #x */
#define P46_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #46 assigned IVG #x */
#define P47_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #47 assigned IVG #x */
/* SIC_IAR5 Macros*/
#define P38_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #38 assigned IVG #x */
#define P39_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #39 assigned IVG #x */
#define P40_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #40 assigned IVG #x */
#define P41_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #41 assigned IVG #x */
#define P42_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #42 assigned IVG #x */
#define P43_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #43 assigned IVG #x */
#define P44_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #44 assigned IVG #x */
#define P45_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #45 assigned IVG #x */
/* SIC_IAR6 Macros */
#define P48_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #48 assigned IVG #x */
#define P49_IVG(x) /* Reserved */
#define P50_IVG(x) /* Reserved */
#define P51_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #51 assigned IVG #x */
#define P52_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #52 assigned IVG #x */
#define P53_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #53 assigned IVG #x */
#define P54_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #54 assigned IVG #x */
#define P55_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #55 assigned IVG #x */
/* SIC_IAR6 Macros*/
#define P46_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #46 assigned IVG #x */
#define P47_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #47 assigned IVG #x */
#define P48_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #48 assigned IVG #x */
#define P49_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #49 assigned IVG #x */
#define P50_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #50 assigned IVG #x */
#define P51_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #51 assigned IVG #x */
#define P52_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #52 assigned IVG #x */
#define P53_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #53 assigned IVG #x */
/* SIC_IAR7 Macros*/
#define P54_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #54 assigned IVG #x */
#define P55_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #55 assigned IVG #x */
#define P56_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #56 assigned IVG #x */
#define P57_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #57 assigned IVG #x */
#define P58_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #58 assigned IVG #x */
#define P59_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #59 assigned IVG #x */
#define P60_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #60 assigned IVG #x */
#define P61_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #61 assigned IVG #x */
/* SIC_IAR7 Macros */
#define P56_IVG(x) /* Reserved */
#define P57_IVG(x) /* Reserved */
#define P58_IVG(x) /* Reserved */
#define P59_IVG(x) /* Reserved */
#define P60_IVG(x) /* Reserved */
#define P61_IVG(x) /* Reserved */
#define P62_IVG(x) /* Reserved */
#define P63_IVG(x) /* Reserved */
/* SIC_IMASK0 Masks*/
#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
#ifdef _MISRA_RULES
#define SIC_MASK0(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/
#define SIC_MASK0(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt */
#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IMASK1 Masks*/
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
#ifdef _MISRA_RULES
#define SIC_MASK1(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/
#define SIC_MASK1(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt */
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IWR0 Masks*/
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
#ifdef _MISRA_RULES
#define IWR0_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Wakeup Disable Peripheral #x */
#define IWR0_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
#else
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */
/* SIC_IWR1 Masks*/
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
#ifdef _MISRA_RULES
#define IWR1_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/* Wakeup Disable Peripheral #x*/
#define IWR1_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x*/
#else
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */
@ -1844,8 +1835,6 @@
#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
#define PGDE_UART PFDE_UART
#define PGDE_DMA PFDE_DMA
#define CKELOW SCKELOW

2
libgloss/bfin/include/defBF522.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF523.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF524.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF525.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF526.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF527.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

206
libgloss/bfin/include/defBF52x_base.h
View File

@ -13,7 +13,7 @@
/*
** defBF52x_base.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -31,6 +31,7 @@
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#include <stdint.h>
#endif /* _MISRA_RULES */
@ -106,7 +107,6 @@
#define UART0_LCR 0xFFC0040C /* Line Control Register */
#define UART0_MCR 0xFFC00410 /* Modem Control Register */
#define UART0_LSR 0xFFC00414 /* Line Status Register */
#define UART0_MSR 0xFFC00418 /* Modem Status Register */
#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART0_GCTL 0xFFC00424 /* Global Control Register */
@ -558,7 +558,6 @@
#define UART1_LCR 0xFFC0200C /* Line Control Register */
#define UART1_MCR 0xFFC02010 /* Modem Control Register */
#define UART1_LSR 0xFFC02014 /* Line Status Register */
#define UART1_MSR 0xFFC02018 /* Modem Status Register */
#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
#define UART1_GCTL 0xFFC02024 /* Global Control Register */
@ -795,127 +794,130 @@
#define _MF7 7
#endif /* _MISRA_RULES */
/* SIC_IAR0 Macros */
#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
#define P1_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #1 assigned IVG #x */
#define P2_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #2 assigned IVG #x */
#define P3_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #3 assigned IVG #x */
#define P4_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #4 assigned IVG #x */
#define P5_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #5 assigned IVG #x */
#define P6_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #6 assigned IVG #x */
#define P7_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR0 Macros */
#define P0_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #0 assigned IVG #x */
#define P1_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #1 assigned IVG #x */
#define P2_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #2 assigned IVG #x */
#define P3_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #3 assigned IVG #x */
#define P4_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #4 assigned IVG #x */
#define P5_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #5 assigned IVG #x */
#define P6_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #6 assigned IVG #x */
#define P7_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Macros */
#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
#define P9_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #9 assigned IVG #x */
#define P10_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #10 assigned IVG #x */
#define P11_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #11 assigned IVG #x */
#define P12_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #12 assigned IVG #x */
#define P13_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #13 assigned IVG #x */
/* SIC_IAR1 Macros */
#define P8_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #8 assigned IVG #x */
#define P9_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #9 assigned IVG #x */
#define P10_IVG(x) /* Reserved */
#define P11_IVG(x) /* Reserved */
#define P12_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #12 assigned IVG #x */
#define P13_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #13 assigned IVG #x */
#define P14_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #14 assigned IVG #x */
#define P15_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #15 assigned IVG #x */
/* SIC_IAR2 Macros */
#define P14_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #14 assigned IVG #x */
#define P15_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #15 assigned IVG #x */
#define P16_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #16 assigned IVG #x */
#define P17_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #17 assigned IVG #x */
#define P18_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #18 assigned IVG #x */
#define P19_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #19 assigned IVG #x */
#define P20_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #20 assigned IVG #x */
#define P21_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #21 assigned IVG #x */
/* SIC_IAR2 Macros */
#define P16_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #16 assigned IVG #x */
#define P17_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #17 assigned IVG #x */
#define P18_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #18 assigned IVG #x */
#define P19_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #19 assigned IVG #x */
#define P20_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #20 assigned IVG #x */
#define P21_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #21 assigned IVG #x */
#define P22_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #22 assigned IVG #x */
#define P23_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #23 assigned IVG #x */
/* SIC_IAR3 Macros */
#define P22_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #22 assigned IVG #x */
#define P23_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #23 assigned IVG #x */
#define P24_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #24 assigned IVG #x */
#define P25_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #25 assigned IVG #x */
#define P26_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #26 assigned IVG #x */
#define P27_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #27 assigned IVG #x */
#define P28_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #28 assigned IVG #x */
#define P29_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #29 assigned IVG #x */
/* SIC_IAR3 Macros */
#define P24_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #24 assigned IVG #x */
#define P25_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #25 assigned IVG #x */
#define P26_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #26 assigned IVG #x */
#define P27_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #27 assigned IVG #x */
#define P28_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #28 assigned IVG #x */
#define P29_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #29 assigned IVG #x */
#define P30_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #30 assigned IVG #x */
#define P31_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #31 assigned IVG #x */
/* SIC_IAR4 Macros */
#define P30_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #30 assigned IVG #x */
#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #31 assigned IVG #x */
#define P32_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #32 assigned IVG #x */
#define P33_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #33 assigned IVG #x */
#define P34_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #34 assigned IVG #x */
#define P35_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #35 assigned IVG #x */
#define P36_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #36 assigned IVG #x */
#define P37_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #37 assigned IVG #x */
/* SIC_IAR4 Macros */
#define P32_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #32 assigned IVG #x */
#define P33_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #33 assigned IVG #x */
#define P34_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #34 assigned IVG #x */
#define P35_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #35 assigned IVG #x */
#define P36_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #36 assigned IVG #x */
#define P37_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #37 assigned IVG #x */
#define P38_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #38 assigned IVG #x */
#define P39_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #39 assigned IVG #x */
/* SIC_IAR5 Macros */
#define P38_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #38assigned IVG #x */
#define P39_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #39assigned IVG #x */
#define P40_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #40 assigned IVG #x */
#define P41_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #41 assigned IVG #x */
#define P42_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #42 assigned IVG #x */
#define P43_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #43 assigned IVG #x */
#define P44_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #44 assigned IVG #x */
#define P45_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #45 assigned IVG #x */
/* SIC_IAR5 Macros */
#define P40_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #40 assigned IVG #x */
#define P41_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #41 assigned IVG #x */
#define P42_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #42 assigned IVG #x */
#define P43_IVG(x) ((((x)&_MF15)-_MF7) << 0xC) /* Peripheral #43 assigned IVG #x */
#define P44_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #44 assigned IVG #x */
#define P45_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #45 assigned IVG #x */
#define P46_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #46 assigned IVG #x */
#define P47_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #47 assigned IVG #x */
/* SIC_IAR6 Macros */
#define P46_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #46 assigned IVG #x */
#define P47_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #47 assigned IVG #x */
#define P48_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #48 assigned IVG #x */
#define P49_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #49 assigned IVG #x */
#define P50_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #50 assigned IVG #x */
#define P51_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #51 assigned IVG #x */
#define P52_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #52 assigned IVG #x */
#define P53_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #53 assigned IVG #x */
/* SIC_IAR6 Macros */
#define P48_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #48 assigned IVG #x */
#define P49_IVG(x) ((((x)&_MF15)-_MF7) << 0x4) /* Peripheral #49 assigned IVG #x */
#define P50_IVG(x) ((((x)&_MF15)-_MF7) << 0x8) /* Peripheral #50 assigned IVG #x */
#define P51_IVG(x) /* Reserved */
#define P52_IVG(x) ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #52 assigned IVG #x */
#define P53_IVG(x) ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #53 assigned IVG #x */
#define P54_IVG(x) ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #54 assigned IVG #x */
#define P55_IVG(x) ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #55 assigned IVG #x */
/* SIC_IAR7 Macros */
#define P54_IVG(x) (((x)&_MF15)-_MF7) /* Peripheral #54 assigned IVG #x */
#define P55_IVG(x) (((x)&_MF15)-_MF7) << 0x4 /* Peripheral #55 assigned IVG #x */
#define P56_IVG(x) (((x)&_MF15)-_MF7) << 0x8 /* Peripheral #56 assigned IVG #x */
#define P57_IVG(x) (((x)&_MF15)-_MF7) << 0xC /* Peripheral #57 assigned IVG #x */
#define P58_IVG(x) (((x)&_MF15)-_MF7) << 0x10 /* Peripheral #58 assigned IVG #x */
#define P59_IVG(x) (((x)&_MF15)-_MF7) << 0x14 /* Peripheral #59 assigned IVG #x */
#define P60_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #60 assigned IVG #x */
#define P61_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #61 assigned IVG #x */
/* SIC_IAR7 Macros */
#define P56_IVG(x) /* Reserved */
#define P57_IVG(x) /* Reserved */
#define P58_IVG(x) /* Reserved */
#define P59_IVG(x) /* Reserved */
#define P60_IVG(x) /* Reserved */
#define P61_IVG(x) /* Reserved */
#define P62_IVG(x) /* Reserved */
#define P63_IVG(x) /* Reserved */
/* SIC_IMASK0 Masks */
#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
/* SIC_IMASK0 Masks*/
#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
#ifdef _MISRA_RULES
#define SIC_MASK0(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK0(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IMASK1 Masks */
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
/* SIC_IMASK1 Masks*/
#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
#ifdef _MISRA_RULES
#define SIC_MASK1(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK1(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IWR0 Masks */
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
/* SIC_IWR0 Masks*/
#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
#ifdef _MISRA_RULES
#define IWR0_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
#define IWR0_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
#else
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */
/* SIC_IWR1 Masks */
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
/* SIC_IWR1 Masks*/
#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
#ifdef _MISRA_RULES
#define IWR1_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
#define IWR1_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x*/
#else
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */
@ -1776,8 +1778,6 @@
#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
#define PGDE_UART PFDE_UART
#define PGDE_DMA PFDE_DMA
#define CKELOW SCKELOW
/* ==== end from defBF534.h ==== */

2
libgloss/bfin/include/defBF531.h
View File

@ -14,7 +14,7 @@
*
* defBF531.h
*
* Copyright (C) 2008 Analog Devices, Inc.
* (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

39
libgloss/bfin/include/defBF532.h
View File

@ -14,7 +14,7 @@
*
* defBF532.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2001-2009 Analog Devices, Inc. All rights reserved.
*
************************************************************************/
@ -33,6 +33,7 @@
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#include <stdint.h>
#endif /* _MISRA_RULES */
/*********************************************************************************** */
@ -85,7 +86,6 @@
#define UART_LCR 0xFFC0040C /* Line Control Register */
#define UART_MCR 0xFFC00410 /* Modem Control Register */
#define UART_LSR 0xFFC00414 /* Line Status Register */
/*#define UART_MSR 0xFFC00418 // Modem Status Register //(UNUSED in ADSP-BF532) */
#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART_GCTL 0xFFC00424 /* Global Control Register */
@ -487,9 +487,9 @@
/* SYSCR Masks */
#define BMODE_BYPASS 0x0000 /* Bypass boot ROM, execute from 16-bit external memory */
#define BMODE_FLASH 0x0001 /* Use Boot ROM to load from 8-bit or 16-bit flash */
#define BMODE_SPIHOST 0x0002 /* Boot from SPI0 host (slave mode) */
#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
#define BMODE_FLASH 0x0002 /* Use Boot ROM to load from 8-bit or 16-bit flash */
#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
#define BMODE_SPIMEM 0x0006 /* Boot from serial SPI memory */
#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
@ -573,28 +573,29 @@
/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
#endif /* _MISRA_RULES */
/* SIC_IMASK Masks */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
/* SIC_IMASK Masks*/
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
#ifdef _MISRA_RULES
#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IWR Masks */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
/* SIC_IWR Masks*/
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
#ifdef _MISRA_RULES
#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
#define IWR_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
#else
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */
/* ********* WATCHDOG TIMER MASKS ******************** */
/* Watchdog Timer WDOG_CTL Register Masks */

2
libgloss/bfin/include/defBF533.h
View File

@ -14,7 +14,7 @@
*
* defBF533.h
*
* Copyright (C) 2008 Analog Devices, Inc.
* (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

35
libgloss/bfin/include/defBF534.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2004-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -29,7 +29,7 @@
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4:"ADI header allows any substitution")
#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
#include <stdint.h>
#endif /* _MISRA_RULES */
/************************************************************************************
@ -82,7 +82,6 @@
#define UART0_LCR 0xFFC0040C /* Line Control Register */
#define UART0_MCR 0xFFC00410 /* Modem Control Register */
#define UART0_LSR 0xFFC00414 /* Line Status Register */
#define UART0_MSR 0xFFC00418 /* Modem Status Register */
#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART0_GCTL 0xFFC00424 /* Global Control Register */
@ -534,7 +533,6 @@
#define UART1_LCR 0xFFC0200C /* Line Control Register */
#define UART1_MCR 0xFFC02010 /* Modem Control Register */
#define UART1_LSR 0xFFC02014 /* Line Status Register */
#define UART1_MSR 0xFFC02018 /* Modem Status Register */
#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
#define UART1_GCTL 0xFFC02024 /* Global Control Register */
@ -1178,27 +1176,26 @@
#define P30_IVG(x) (((x)&_MF15)-_MF7) << 0x18 /* Peripheral #30 assigned IVG #x */
#define P31_IVG(x) (((x)&_MF15)-_MF7) << 0x1C /* Peripheral #31 assigned IVG #x */
/* SIC_IMASK Masks */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
/* SIC_IMASK Masks*/
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
#ifdef _MISRA_RULES
#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IWR Masks */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
/* SIC_IWR Masks*/
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
#ifdef _MISRA_RULES
#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
#define IWR_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
#else
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */

2
libgloss/bfin/include/defBF535.h
View File

@ -14,7 +14,7 @@
*
* defBF535.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2001-2008 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/defBF536.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008 Analog Devices, Inc.
** Copyright (C) 2005 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF537.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2004-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

2
libgloss/bfin/include/defBF538.h
View File

@ -14,7 +14,7 @@
**
** defBF538.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
*************************************************************************/

31
libgloss/bfin/include/defBF539.h
View File

@ -11,7 +11,7 @@
*/
/*
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -29,6 +29,7 @@
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
#include <stdint.h>
#endif /* _MISRA_RULES */
/*********************************************************************************** */
@ -1643,26 +1644,26 @@
/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
#endif /* _MISRA_RULES */
/* SIC_IMASKx Masks */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
/* SIC_IMASKx Masks*/
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
#ifdef _MISRA_RULES
#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IWRx Masks */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
/* SIC_IWRx Masks*/
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
#ifdef _MISRA_RULES
#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */
#define IWR_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
#else
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */

2
libgloss/bfin/include/defBF542.h
View File

@ -13,7 +13,7 @@
/*
** defBF542.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/defBF542M.h
View File

@ -13,7 +13,7 @@
/*
** defBF542M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
**/
#ifndef _DEF_BF542M_H
#define _DEF_BF542M_H
#include <defBF542.h>
#endif /* _DEF_BF542M_H */

2
libgloss/bfin/include/defBF544.h
View File

@ -13,7 +13,7 @@
/*
** defBF544.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/defBF544M.h
View File

@ -13,7 +13,7 @@
/*
** defBF544M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
**/
#ifndef _DEF_BF544M_H
#define _DEF_BF544M_H
#include <defBF544.h>
#endif /* _DEF_BF544M_H */

2
libgloss/bfin/include/defBF547.h
View File

@ -13,7 +13,7 @@
/*
** defBF547.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2007-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/defBF547M.h
View File

@ -13,7 +13,7 @@
/*
** defBF547M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
**/
#ifndef _DEF_BF547M_H
#define _DEF_BF547M_H
#include <defBF547.h>
#endif /* _DEF_BF5447M_H */

2
libgloss/bfin/include/defBF548.h
View File

@ -13,7 +13,7 @@
/*
** defBF548.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/defBF548M.h
View File

@ -13,7 +13,7 @@
/*
** defBF548M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
**/
#ifndef _DEF_BF548M_H
#define _DEF_BF548M_H
#include <defBF548.h>
#endif /* _DEF_BF548M_H */

2
libgloss/bfin/include/defBF549.h
View File

@ -13,7 +13,7 @@
/*
** defBF549.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**

7
libgloss/bfin/include/defBF549M.h
View File

@ -13,7 +13,7 @@
/*
** defBF549M.h
**
** Copyright (C) 2009 Analog Devices, Inc.
** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -22,4 +22,9 @@
**
**/
#ifndef _DEF_BF549M_H
#define _DEF_BF549M_H
#include <defBF549.h>
#endif /* _DEF_BF549M_H */

50
libgloss/bfin/include/defBF54x_base.h
View File

@ -13,7 +13,7 @@
/*
** defBF54x_base.h
**
** Copyright (C) 2008, 2009 Analog Devices, Inc.
** Copyright (C) 2006-2009 Analog Devices Inc., All Rights Reserved.
**
************************************************************************************
**
@ -29,8 +29,10 @@
#ifdef _MISRA_RULES
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#pragma diag(suppress:misra_rule_5_1:"ADI Header allows long identifiers")
#pragma diag(suppress:misra_rule_19_4:"ADI header allows any substitution text")
#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
#include <stdint.h>
#endif /* _MISRA_RULES */
@ -4637,11 +4639,23 @@
/* ******************************************* */
/* SYSCR Masks */
#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
#define BMODE_NOBOOT 0x0000 /* The processor does not boot. Rather, the boot kernel executes an IDLE instruction. */
#define BMODE_FLASH 0x0001 /* Boot from 8-bit or 16-bit external flash memory */
#define BMODE_FIFO 0x0002 /* Boot from 16-bit asynchronous FIFO */
#define BMODE_SPIMEM 0x0003 /* Boot from serial SPI memory */
#define BMODE_SPIHOST 0x0004 /* Boot from SPI0 host (slave mode) */
#define BMODE_TWIMEM 0x0005 /* Boot from serial TWI memory */
#define BMODE_TWIHOST 0x0006 /* Boot from TWI0 host (slave mode) */
#define BMODE_UARTHOST 0x0007 /* Boot from UART host */
#define BMODE_UART1HOST 0x0007 /* Boot from UART1 host */
#define BMODE_SDRAMMEM 0x000A /* Boot from SDRAM memory (warm boot) */
#define BMODE_OTPMEM 0x000B /* Boot from OTP memory */
#define BMODE_NAND 0x000D /* Boot from 8- and 16-bit NAND flash */
#define BMODE_HOSTDMA_ACK 0x000E /* Boot from 16-bit host DMA (ACK mode) */
#define BMODE_HOSTDMA_INT 0x000F /* Boot from 8-bit host DMA (INT mode) */
#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
#define NOBOOT 0x0030 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
#define BCODE 0x00F0
#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
@ -5429,30 +5443,30 @@ PORTJ_DIR_CLEAR, PORTJ_INEN, PORTJ_FER */
/* SIC_IMASKx Masks */
/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
/* SIC_IMASKx Macros */
#ifdef _MISRA_RULES
#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IWR Masks */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
/* SIC_IWR Macros */
/* x = pos 0 to 31, for 32-63 use value-32 */
#ifdef _MISRA_RULES
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
#define IWR_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
#else
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */
#define PIVG(PNr, IVGNr) ( (IVGNr) - 7) << ( ((PNr)%8) * 4) /* Peripheral #PNr assigned IVG #IVGNr */

35
libgloss/bfin/include/defBF561.h
View File

@ -14,7 +14,7 @@
*
* defBF561.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2001-2009 Analog Devices, Inc. All rights reserved.
*
************************************************************************/
@ -33,6 +33,7 @@
#pragma diag(push)
#pragma diag(suppress:misra_rule_19_4)
#pragma diag(suppress:misra_rule_19_7)
#include <stdint.h>
#endif /* _MISRA_RULES */
/*********************************************************************************** */
@ -111,7 +112,6 @@
#define UART_LCR 0xFFC0040C /* Line Control Register */
#define UART_MCR 0xFFC00410 /* Modem Control Register */
#define UART_LSR 0xFFC00414 /* Line Status Register */
#define UART_MSR 0xFFC00418 /* Modem Status Register */
#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART_GCTL 0xFFC00424 /* Global Control Register */
@ -969,20 +969,33 @@
/* r0.h = hi(Peripheral_IVG(62, 10)); */
/* SICx_IMASKw Masks */
/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
/* SIC_IMASKx Macros */
#ifdef _MISRA_RULES
#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Unmask Peripheral #x interrupt*/
#else
#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
#endif /* _MISRA_RULES */
/* SIC_IWR Masks */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
/* SIC_IWR Macros */
/* x = pos 0 to 31, for 32-63 use value-32 */
#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
#ifdef _MISRA_RULES
#define IWR_ENABLE(x) ((int32_t)1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu))) /*Wakeup Disable Peripheral #x */
#else
#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
#endif /* _MISRA_RULES */
/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */

2
libgloss/bfin/include/defblackfin.h
View File

@ -14,7 +14,7 @@
*
* defblackfin.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2001-2009 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

168
libgloss/bfin/include/sys/anomaly_macros_rtl.h
View File

@ -14,7 +14,7 @@
*
* anomaly_macros_rtl.h : $Revision$
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2005-2009 Analog Devices, Inc. All rights reserved.
*
* This file defines macros used within the run-time libraries to enable
* certain anomaly workarounds for the appropriate chips and silicon
@ -314,6 +314,72 @@
(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)))
/* 050000244 - "If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control
** Causes Failures"
**
** When instruction cache is enabled, a CSYNC/SSYNC/IDLE around a
** change of control (including asynchronous exceptions/interrupts)
** can cause unpredictable results.
**
** This macro is used by System Services/Device Drivers.
**
** Impacted:
**
** BF531/2/3 - 0.0-0.4 (fixed 0.5)
** BF534/6/7 - 0.0-0.2 (fixed 0.3)
** BF534/8/9 - 0.0-0.1 (fixed 0.2)
** BF561 - 0.0-0.3 (fixed 0.5)
*/
#define WA_05000244 \
(defined(__SILICON_REVISION__) && \
((defined(__ADSPBF533_FAMILY__) && \
(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF537_FAMILY__) && \
(__SILICON_REVISION__ <= 0x2 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF538_FAMILY__) && \
(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF561_FAMILY__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))))
/* 050000245 - "False Hardware Error from an Access in the Shadow of a
** Conditional Branch"
**
** If a load accesses reserved or illegal memory on the opposite control
** flow of a conditional jump to the taken path, a false hardware error
** will occur.
**
** This macro is used by System Services/Device Drivers.
**
** This is for all Blackfin LP parts.
*/
#define WA_05000245 \
(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
/* 050000248 - "TESTSET Operation Forces Stall on the Other Core "
**
** Use by System Services/Device Drivers.
**
** Succeed any testset to L2 with a write to L2 to avoid the other core
** stalling. This must be atomic, as an interrupt between the two would
** cause the lockout to occur until the interrupt is fully serviced.
**
** This macro is used by System Services/Device Drivers.
**
** Impacted:
**
** BF561 - 0.0-0.3 (fixed 0.5)
**
*/
#define WA_05000248 \
(defined (__SILICON_REVISION__) && defined(__ADSPBF561_FAMILY__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff))
/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of
* the ICPLB Data registers differ"
*
@ -356,18 +422,6 @@
(!defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)))
/* 05-00-0259 - "Non-deterministic ICPLB descriptors delivered to
* hardware". Whenever ICPLBs are disabled via an MMR write, immediately
* follow this write with a CSYNC, and locate the MMR write and CSYNC
* within the same aligned 64 bit word.
*
* This problem impacts all revisions of Blackfins.
*/
#define WA_05000259 \
(defined(__ADSPBLACKFIN__) && defined(__SILICON_REVISION__))
/* 05-00-0261 - "DCPLB_FAULT_ADDR MMR may be corrupted".
* The DCPLB_FAULT_ADDR MMR may contain the fault address of a
* aborted memory access which generated both a protection exception
@ -486,6 +540,31 @@
(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)))
/* 05-00-0312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers
** Are Interrupted
**
** Impacted:
** ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6)
** ADSP-BF53[467] - all supported revisions
** ADSP-BF53[89] - 0.0-0.4 (fixed in 0.5)
** ADSP-BF561 - all supported revisions
** ADSP-BF54[24789] - 0.0 (fixed in 0.1)
**
** Used by VDK
*/
#define WA_05000312 \
(defined(__SILICON_REVISION__) && \
(defined(__ADSPBF533_FAMILY__) && \
(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF537_FAMILY__)) || \
(defined(__ADSPBF538_FAMILY__) && \
(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF548_FAMILY__) && \
(__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF561_FAMILY__)))
/* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
**
** Impacted:
@ -511,6 +590,34 @@
defined(__SILICON_REVISION__))
/* 05-00-0371 - Possible RETS Register Corruption when Subroutine Is under
** 5 Cycles in Duration
**
** This problem impacts:
** BF531/2/3 - 0.0-0.5 (fixed in 0.6)
** BF534/6/7 - 0.0-0.3
** BF538/9 - 0.0-0.4 (fixed in 0.5)
** BF561 - 0.0-0.5
** BF542/4/7/8/9 - 0.0-0.1 (fixed in 0.2)
** BF523/5/7 - 0.0-0.1 (fixed in 0.2)
**
*/
#define WA_05000371 \
(defined(__SILICON_REVISION__) && \
(defined(__ADSPBF533_FAMILY__) && \
(__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF537_FAMILY__) && \
(__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF538_FAMILY__) && \
(__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF548_FAMILY__) && \
(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF527_FAMILY__) && \
(__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
(defined(__ADSPBF561__) || defined(__ADSPBF566__)))
/* 05-00-0380 - Data Read From L3 Memory by USB DMA May be Corrupted
**
** Impacted:
@ -552,6 +659,31 @@
(defined (__SILICON_REVISION__) && defined(__ADSPBF561__))
/* 05-00-0426 - Speculative Fetches of Indirect-Pointer Instructions Can
** Cause False Hardware Errors
**
**
** A false hardware error is generated if there is an indirect jump or
** call through a pointer which may point to reserved or illegal memory
** on the opposite control flow of a conditional jump to the taken path.
** This commonly occurs when using function pointers, which can be
** invalid (e.g., set to -1).
**
** Workaround: If instruction cache is on or the ICPLBs are enabled,
** this anomaly does not apply. If instruction cache is off and ICPLBs
** are disabled, the indirect pointer instructions must be 2 instructions
** away from the branch instruction, which can be implemented using NOPs:
**
**
** Impacted:
** All parts and revisions other than BF535 based parts.
**
** Used by System Services/Device Drivers.
*/
#define WA_05000426 \
(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
/* 05-00-0428 - "Lost/Corrupted Write to L2 Memory Following Speculative Read
* by Core B from L2 Memory"
*
@ -608,6 +740,16 @@
(__SILICON_REVISION__ == 0x5)))
/* 05-00-0443 - IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall
**
** Impacted:
** All parts and revisions other than BF535 based parts.
**
** Used by System Services/Device Drivers.
*/
#define WA_05000443 \
(defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
#ifdef _MISRA_RULES
#pragma diag(pop)
#endif /* _MISRA_RULES */

2
libgloss/bfin/include/sys/excause.h
View File

@ -14,7 +14,7 @@
*
* excause.h
*
* Copyright (C) 2008 Analog Devices, Inc.
* (c) Copyright 2001-2003 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

2
libgloss/bfin/include/sys/exception.h
View File

@ -18,7 +18,7 @@
*
* exception.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2001-2008 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

11
libgloss/bfin/include/sys/mc_typedef.h
View File

@ -18,7 +18,7 @@
*
* sys/mc_typedef.h
*
* Copyright (C) 2008 Analog Devices, Inc.
* (c) Copyright 2007-2009 Analog Devices, Inc. All rights reserved.
*
************************************************************************/
@ -28,11 +28,12 @@
#define _SYS_MC_TYPEDEF_H
#if !defined(__ADSPLPBLACKFIN__)
typedef volatile unsigned char testset_t;
#elif defined(__WORKAROUND_TESTSET_ALIGN) /* require 32-bit aligned address */
typedef volatile unsigned int testset_t;
typedef volatile unsigned char testset_t;
#elif defined(__WORKAROUND_TESTSET_ALIGN) || defined(__WORKAROUND_05000412)
/* these workarounds require 32-bit aligned address */
typedef volatile unsigned int testset_t;
#else
typedef volatile unsigned short testset_t;
typedef volatile unsigned short testset_t;
#endif
#endif /* _SYS_MC_TYPEDEF_H */

2
libgloss/bfin/include/sys/platform.h
View File

@ -13,7 +13,7 @@
#ifndef _PLATFORM_H
#define _PLATFORM_H
/* Generic Wrapper for platform specific header file.
Copyright (C) 2008 Analog Devices, Inc.
Copyright (C.) 2004, Analog Devices Inc. All Rights Reserved.
*/
#include <sys/_adi_platform.h>
#endif

2
libgloss/bfin/include/sys/pll.h
View File

@ -14,7 +14,7 @@
*
* pll.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2003-2004 Analog Devices, Inc. All rights reserved.
*
************************************************************************/

6
libgloss/bfin/include/sysreg.h
View File

@ -10,10 +10,10 @@
* they apply.
*/
/* This file must be used with compiler version 8.0.6.4 */
/* This file must be used with compiler version 8.0.8.1 */
#ifdef __VERSIONNUM__
#if __VERSIONNUM__ != 0x08000604
#if __VERSIONNUM__ != 0x08000801
#error The compiler version does not match the version of the sysreg.h include
#endif
#endif
@ -22,7 +22,7 @@
*
* sysreg.h
*
* Copyright (C) 2008, 2009 Analog Devices, Inc.
* (c) Copyright 2001-2006 Analog Devices, Inc. All rights reserved.
*
***********************************************************************/