diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 4daf47bc0..189a1d417 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2013-06-23  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
+
 2013-06-17  Catherine Moore  <clm@codesourcery.com>
 	    Maciej W. Rozycki  <macro@codesourcery.com>
 	    Chao-Ying Fu  <fu@mips.com>
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 9d241e847..e62ecd6e6 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1811,7 +1811,7 @@ extern const int bfd_mips16_num_opcodes;
 
    Coprocessor instructions:
    "E" 5-bit target register (MICROMIPSOP_*_RT)
-   "G" 5-bit destination register (MICROMIPSOP_*_RD)
+   "G" 5-bit destination register (MICROMIPSOP_*_RS)
    "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
    "+D" combined destination register ("G") and sel ("H") for CP0 ops,
 	for pretty-printing in disassembly only