From 0fe1b31bca6f1cbb9b3b9fbade71ea37c7eaf6eb Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Wed, 20 Mar 2013 16:56:34 +0000 Subject: [PATCH] PR gas/15082 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro from ORREGD1324 to ORXREGD1324 and make it cross-path-able through tic6x_operand_xregpair operand coding type. Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' opcode field, usu ORXREGD1324 for the src2 operand and remove the TIC6X_FLAG_NO_CROSS. * gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with cross-path. * gas/tic6x/insns-bad-1.l: Update expected output. * gas/tic6x/insns-c674x.s: Add a test-case for mpydp with cross-path. * gas/tic6x/insns-c674x.d: Update expected output. --- include/opcode/ChangeLog | 10 ++++++++++ include/opcode/tic6x-opcode-table.h | 14 +++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 69d0859e1..cc7ef5fb1 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,13 @@ +2013-03-20 Alexis Deruelle + + PR gas/15082 + * tic6x-opcode-table.h: Rename mpydp's specific operand type macro + from ORREGD1324 to ORXREGD1324 and make it cross-path-able through + tic6x_operand_xregpair operand coding type. + Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' + opcode field, usu ORXREGD1324 for the src2 operand and remove the + TIC6X_FLAG_NO_CROSS. + 2013-03-20 Alexis Deruelle PR gas/15095 diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h index abebd3c17..e9cfab917 100644 --- a/include/opcode/tic6x-opcode-table.h +++ b/include/opcode/tic6x-opcode-table.h @@ -75,7 +75,7 @@ #define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 } #define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 } #define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 } -#define ORREGD1324 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 3, 2, 4 } +#define ORXREGD1324 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 3, 2, 4 } #define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 } #define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 } #define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 } @@ -1154,11 +1154,11 @@ INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(mpydp, m, mpy, mpydp, C67X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x0e), FIX(x, 0)), - OP3(ORREGD1234, ORREGD1324, OWREGD910), - ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) +INSN(mpydp, m, mpy, mpydp, C67X, 0, + FIX1(FIX(op, 0x0e)), + OP3(ORREGD1234, ORXREGD1324, OWREGD910), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(mpyh, m, mpy, 1616_m, C62X, 0, FIX1(FIX(op, 0x01)), @@ -2520,7 +2520,7 @@ INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X, #undef OWDREGD5 #undef ORREGD12 #undef ORXREGD12 -#undef ORREGD1234 +#undef ORXREGD1234 #undef ORREGD1324 #undef OWREGD910 #undef ORCREG1