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fhandler_proc.cc(format_proc_cpuinfo): add flags and TLB size
update to Linux-next 5.8 order fields and flags: add amd_dcm, arch_lbr, arch_perfmon, art, cpuid, extd_apicid, ibpb, ibrs, ibrs_enhanced, nonstop_tsc_s3, nopl, rep_good, ring3mwait, ssbd, stibp, tsc_known_freq, tsc_reliable, xtopology flags; add TLB size line; add ftuprint macro for feature test unconditional flag print; add commented out flags requiring CR or MSR access in print order with comment explaining issue; make cpuid leaf numbers consistent 8 hex digits for searching
This commit is contained in:
Brian Inglis
Corinna Vinschen
parent
1c803a6d88
commit
0947efb859
@ -609,8 +609,10 @@ format_proc_stat (void *, char *&destbuf)
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}
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#define print(x) { bufptr = stpcpy (bufptr, (x)); }
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/* feature test unconditional print */
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#define ftuprint(msg) print (" " msg)
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/* feature test bit position (0-32) and conditional print */
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#define ftcprint(feat,bitno,msg) if ((feat) & (1 << (bitno))) { print (" " msg); }
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#define ftcprint(feat,bitno,msg) if ((feat) & (1 << (bitno))) { ftuprint (msg); }
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static inline uint32_t
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get_msb (uint32_t in)
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@ -1021,8 +1023,8 @@ format_proc_cpuinfo (void *, char *&destbuf)
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ftcprint (features1, 22, "acpi"); /* ACPI via MSR */
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ftcprint (features1, 23, "mmx"); /* multimedia extensions */
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ftcprint (features1, 24, "fxsr"); /* fxsave/fxrstor */
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ftcprint (features1, 25, "sse"); /* xmm */
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ftcprint (features1, 26, "sse2"); /* xmm2 */
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ftcprint (features1, 25, "sse"); /* xmm sse */
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ftcprint (features1, 26, "sse2"); /* xmm2 sse2 */
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ftcprint (features1, 27, "ss"); /* CPU self snoop */
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ftcprint (features1, 28, "ht"); /* hyper threading */
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ftcprint (features1, 29, "tm"); /* acc automatic clock control */
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@ -1041,27 +1043,171 @@ format_proc_cpuinfo (void *, char *&destbuf)
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ftcprint (features1, 25, "fxsr_opt"); /* fxsave/fxrstor optims */
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ftcprint (features1, 26, "pdpe1gb"); /* GB large pages */
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ftcprint (features1, 27, "rdtscp"); /* rdtscp */
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ftcprint (features1, 29, "lm"); /* long mode (x86 64) */
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ftcprint (features1, 29, "lm"); /* long mode (x86-64 amd64) */
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ftcprint (features1, 30, "3dnowext"); /* 3DNow extensions */
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ftcprint (features1, 31, "3dnow"); /* 3DNow */
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}
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/* cpuid 0x80000007 edx */
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if (maxe >= 0x80000007)
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{
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cpuid (&unused, &unused, &unused, &features1, 0x80000007);
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ftcprint (features1, 8, "constant_tsc"); /* TSC ticks at a constant rate */
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}
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/* ftcprint (features2, 9, "up"); *//* SMP kernel running on UP N/A */
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/* cpuid 0x00000007 ebx */
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if (maxf >= 0x00000007)
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cpuid (&unused, &features1, &unused, &unused, 0x00000007, 0);
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else
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features1 = 0;
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/* cpuid 0x80000007 edx */
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if (maxe >= 0x80000007)
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cpuid (&unused, &unused, &unused, &features2, 0x80000007);
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else
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features2 = 0;
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uint32_t cr_den, cr_num, Hz;
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/* cpuid 0x00000015 eax ebx ecx clock ratios optional Hz */
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if (is_intel && maxf >= 0x00000015)
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cpuid (&cr_den, &cr_num, &Hz, &unused, 0x00000015);
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else
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cr_den = 0;
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/* TSC requires adjustment, nonstop, and clock ratio divider min */
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if ((features1 & (1 << 1)) && /* TSC adjustment MSR 0x3B */
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(features2 & (1 << 8)) && /* nonstop C states */
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(cr_den > 1)) /* clock ratio denominator > min */
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ftuprint ("art"); /* Always running timer (ART) */
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/* Intel cpuid 0x0000000a eax Arch Perf Mon */
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if (is_intel && maxf >= 0x0000000a)
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{
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cpuid (&features2, &unused, &unused, &unused, 0x0000000a);
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/* rev > 0 and # counters/cpu > 1 */
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if ((features2 & 0xff) > 0 && (((features2 >> 8) & 0xff) > 1))
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ftuprint ("arch_perfmon"); /* Intel Arch Perf Mon */
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}
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/* ftcprint (features2, 12, "pebs");*//* MSR_IA32_MISC_ENABLE 12 Precise-Event Based Sampling */
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/* ftcprint (features2, 13, "bts"); *//* MSR_IA32_MISC_ENABLE 11 Branch Trace Store */
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/* AMD cpuid 0x00000001 eax */
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if (is_amd && maxf >= 0x00000001)
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cpuid(&features2, &unused, &unused, &unused, 0x00000001);
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else
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features2 = 0;
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/* Intel family 6 or AMD family >= x10 or ... */
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/* ... or AMD cpuid 0x00000001 eax in [0x0f58,) or [0x0f48,0x0f50) */
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if ((is_intel && family == 6) ||
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(is_amd && (family >= 0x10 ||
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(features2 >= 0x0f58 ||
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(features2 >= 0x0f48 && features2 < 0x0f50)))))
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ftuprint ("rep_good"); /* REP microcode works well */
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/* cpuid 0x80000007 edx Advanced power management */
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if (maxe >= 0x80000007)
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{
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cpuid (&unused, &unused, &unused, &features2, 0x80000007);
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ftcprint (features2, 12, "acc_power"); /* accum power */
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}
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#if __x86_64__
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ftuprint ("nopl"); /* NOPL (0F 1F) instructions */
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#endif
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/* cpuid 0x0000000b ecx[8:15] type */
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#define BAD_TYPE 0
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#define SMT_TYPE 1
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#define CORE_TYPE 2
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/* cpuid 0x0000000b ebx ecx */
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if (maxf >= 0x0000000b)
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{
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cpuid(&unused, &features1, &features2, &unused, 0x0000000b);
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/* check if SMT implemented */
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if (features1 != 0 && (((features2 >> 8) & 0xff) == SMT_TYPE))
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ftuprint ("xtopology"); /* CPU topology enum extensions */
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}
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/* AMD cpuid 0x80000007 edx */
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if (is_amd && maxe >= 0x80000007)
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{
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cpuid (&unused, &unused, &unused, &features1, 0x80000007);
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ftcprint (features1, 8, "constant_tsc"); /* TSC constant rate */
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ftcprint (features1, 8, "tsc_reliable"); /* TSC constant rate */
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ftcprint (features1, 8, "nonstop_tsc"); /* nonstop C states */
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}
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/* cpuid 0x00000006 ecx */
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if (maxf >= 0x06)
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if (is_amd || is_intel)
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ftuprint ("cpuid"); /* CPU has CPUID instruction */
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if (is_amd && family > 0x16)
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ftuprint ("extd_apicid"); /* Extended APICID (8 bits) */
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/* AMD cpuid 0x8000001e ecx */
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if (is_amd && maxe >= 0x8000001e)
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{
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cpuid (&unused, &unused, &features1, &unused, 0x06);
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cpuid (&unused, &unused, &features1, &unused, 0x8000001e);
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if (((features1 >> 8) & 7) + 1 > 1) /* nodes/socket */
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ftuprint ("amd_dcm"); /* AMD multi-node processor */
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}
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/* cpuid 0x00000006 ecx */
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if (maxf >= 0x00000006)
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{
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cpuid (&unused, &unused, &features1, &unused, 0x00000006);
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ftcprint (features1, 0, "aperfmperf"); /* P state hw coord fb */
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}
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/* Penwell, Cloverview, ... TSC doesn't sleep on S3 */
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if (is_intel && family == 6)
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switch (model)
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{
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case 0x27: /* Atom Saltwell Mid Penwell */
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case 0x35: /* Atom Saltwell Tablet Cloverview */
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case 0x4a: /* Atom Silvermont Mid Merriefield */
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case 0x75: /* Atom Airmont NP Lightning Mountain */
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ftuprint ("nonstop_tsc_s3"); /* TSC doesn't stop in S3 state */
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break;
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}
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/* cpuid 0x00000015 eax ebx ecx clock ratios optional Hz */
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if (is_intel && maxf >= 0x00000015)
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{
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uint32_t cr_den, cr_num, Hz, kHz;
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cpuid (&cr_den, &cr_num, &Hz, &unused, 0x00000015);
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if (cr_num != 0 && cr_den != 0)
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{
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kHz = Hz / 1000;
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/* Denverton don't report hz nor support cpuid 0x16 so set 25MHz */
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if (kHz == 0 && model == 0x5F) /* Atom Goldmont D Denverton */
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kHz = 25000;
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/* cpuid TSC frequency is known */
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if (kHz != 0)
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ftuprint ("tsc_known_freq"); /* TSC has known frequency */
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#if 0 /* keep for future and doc */
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else /* kHz == 0 */
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/* Skylake and Kabylake don't report clock so use CPU speed and ratio */
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if (maxf >= 0x00000016)
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{
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uint32_t mHz;
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cpuid(&mHz, &unused, &unused, &unused, 0x00000016);
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kHz = mHz * 1000 * cr_num / cr_den;
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}
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#endif
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}
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}
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/* cpuid 0x00000001 ecx */
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cpuid (&unused, &unused, &features2, &unused, 0x00000001);
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ftcprint (features2, 0, "pni"); /* xmm3 sse3 */
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ftcprint (features2, 1, "pclmuldq"); /* pclmulqdq instruction */
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ftcprint (features2, 2, "dtes64"); /* 64-bit debug store */
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@ -1088,7 +1234,7 @@ format_proc_cpuinfo (void *, char *&destbuf)
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ftcprint (features2, 24, "tsc_deadline_timer"); /* TSC deadline timer */
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ftcprint (features2, 25, "aes"); /* AES instructions */
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ftcprint (features2, 26, "xsave"); /* xsave/xrstor/xsetbv/xgetbv */
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/* ftcprint (features2, 27, "osxsave"); */ /* not output on Linux */
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/* ftcprint (features2, 27, "osxsave");*//* "" XSAVE supported in OS */
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ftcprint (features2, 28, "avx"); /* advanced vector extensions */
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ftcprint (features2, 29, "f16c"); /* 16 bit FP conversions */
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ftcprint (features2, 30, "rdrand"); /* RNG rdrand instruction */
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@ -1133,34 +1279,49 @@ format_proc_cpuinfo (void *, char *&destbuf)
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}
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}
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/* features scattered in various CPUID levels. */
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/* ring 3 monitor/mwait */
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if (is_intel && family == 6)
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switch (model)
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{
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case 0x57: /* Xeon Phi Knights Landing */
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case 0x85: /* Xeon Phi Knights Mill */
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ftuprint ("ring3mwait"); /* Ring 3 MONITOR/MWAIT instructions */
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break;
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}
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/* ftcprint (features1, 1, "cpuid_fault");*//* MSR_PLATFORM_INFO Intel CPUID faulting */
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/* features scattered in various CPUID levels. */
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/* cpuid 0x80000007 edx */
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if (maxf >= 0x07)
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if (maxf >= 0x00000007)
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{
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cpuid (&unused, &unused, &unused, &features1, 0x80000007);
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ftcprint (features1, 9, "cpb"); /* core performance boost */
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}
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/* cpuid 0x00000006 ecx */
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if (maxf >= 0x06)
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if (maxf >= 0x00000006)
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{
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cpuid (&unused, &unused, &features1, &unused, 0x06);
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cpuid (&unused, &unused, &features1, &unused, 0x00000006);
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ftcprint (features1, 3, "epb"); /* energy perf bias */
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}
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/* cpuid 0x00000010 ebx */
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if (maxf >= 0x10)
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if (maxf >= 0x00000010)
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{
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cpuid (&unused, &features1, &unused, &unused, 0x10);
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cpuid (&unused, &features1, &unused, &unused, 0x00000010);
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ftcprint (features1, 1, "cat_l3"); /* cache alloc tech l3 */
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ftcprint (features1, 2, "cat_l2"); /* cache alloc tech l2 */
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/* cpuid 0x00000010:1 ecx */
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cpuid (&unused, &unused, &features1, &unused, 0x10, 1);
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cpuid (&unused, &unused, &features1, &unused, 0x00000010, 1);
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ftcprint (features1, 2, "cdp_l3"); /* code data prior l3 */
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}
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/* ftcprint (features1, 7, "invpcid_single");*//* INVPCID && CR4.PCIDE=1 */
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/* cpuid 0x80000007 edx */
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if (maxe >= 0x80000007)
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{
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@ -1176,51 +1337,87 @@ format_proc_cpuinfo (void *, char *&destbuf)
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ftcprint (features1, 0, "sme"); /* secure memory encryption */
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}
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/* ftcprint (features1, 11, "pti");*//* Page Table Isolation reqd with Meltdown */
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/* ftcprint (features1, 14, "intel_ppin");*//* MSR_PPIN_CTL Prot Proc Id No */
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/* cpuid 0x00000010:2 ecx */
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if (maxf >= 0x10)
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if (maxf >= 0x00000010)
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{
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cpuid (&unused, &unused, &features1, &unused, 0x10, 2);
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cpuid (&unused, &unused, &features2, &unused, 0x00000010, 2);
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ftcprint (features1, 2, "cdp_l2"); /* code data prior l2 */
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ftcprint (features2, 2, "cdp_l2"); /* code data prior l2 */
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}
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/* cpuid 0x80000008 ebx */
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if (maxe >= 0x80000008)
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{
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cpuid (&unused, &features1, &unused, &unused, 0x80000008, 0);
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/* cpuid 0x00000010 ebx */
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cpuid (&unused, &features1, &unused, &unused, 0x10);
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ftcprint (features1, 24, "ssbd"); /* spec store byp dis */
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}
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/* cpuid 0x00000010 ebx */
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if (maxf >= 0x00000010)
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{
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cpuid (&unused, &features2, &unused, &unused, 0x00000010);
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ftcprint (features1, 3, "mba"); /* memory bandwidth alloc */
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ftcprint (features2, 3, "mba"); /* memory bandwidth alloc */
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}
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/* cpuid 0x80000008 ebx */
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if (maxe >= 0x80000008)
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{
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cpuid (&unused, &features1, &unused, &unused, 0x80000008);
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/* cpuid (&unused, &features1, &unused, &unused, 0x80000008, 0); */
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/* from above */
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ftcprint (features1, 6, "mba"); /* memory bandwidth alloc */
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}
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/* cpuid 0x8000001f eax */
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if (maxe >= 0x8000001f)
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{
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cpuid (&features1, &unused, &unused, &unused, 0x8000001f);
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cpuid (&features2, &unused, &unused, &unused, 0x8000001f);
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ftcprint (features1, 1, "sev"); /* secure encrypted virt */
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ftcprint (features2, 1, "sev"); /* secure encrypted virt */
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}
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/* cpuid 0x80000008 ebx */
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if (maxe >= 0x80000008)
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{
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/* cpuid (&unused, &features1, &unused, &unused, 0x80000008, 0); */
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/* from above */
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/* ftcprint (features1, 0, "clzero"); *//* clzero instruction */
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/* ftcprint (features1, 1, "irperf"); *//* instr retired count */
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/* ftcprint (features1, 2, "xsaveerptr");*//* save/rest FP err ptrs */
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/* ftcprint (features1, 4, "rdpru"); *//* user level rd proc reg */
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/* ftcprint (features1, 6, "mba"); *//* memory BW alloc */
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/* ftcprint (features1, 9, "wbnoinvd"); *//* wbnoinvd instruction */
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ftcprint (features1, 14, "ibrs"); /* ind br restricted spec */
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ftcprint (features1, 12, "ibpb"); /* ind br pred barrier */
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ftcprint (features1, 15, "stibp"); /* 1 thread ind br pred */
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ftcprint (features1, 16, "ibrs_enhanced"); /* IBRS_ALL enhanced IBRS always on */
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/* ftcprint (features1, 17, "stibp_always_on"); */ /* stibp always on */
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/* ftcprint (features1, 18, "ibrs_pref");*//* IBRS_PREF IBRS preferred */
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/* ftcprint (features1, 23, "amd_ppin"); *//* protected proc id no */
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/* ftcprint (features1, 24, "ssbd"); *//* spec store byp dis */
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/* ftcprint (features1, 25, "virt_ssbd");*//* vir spec store byp dis */
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/* ftcprint (features1, 26, "ssb_no"); *//* ssb fixed in hardware */
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}
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/* cpuid 0x00000007 ebx */
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if (maxf >= 0x07)
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if (maxf >= 0x00000007)
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{
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cpuid (&unused, &features1, &unused, &unused, 0x07, 0);
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cpuid (&unused, &features1, &unused, &unused, 0x00000007, 0);
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ftcprint (features1, 0, "fsgsbase"); /* rd/wr fs/gs base */
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ftcprint (features1, 1, "tsc_adjust"); /* TSC adjustment MSR 0x3B */
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ftcprint (features1, 3, "bmi1"); /* bit manip ext group 1 */
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ftcprint (features1, 4, "hle"); /* hardware lock elision */
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ftcprint (features1, 5, "avx2"); /* AVX ext instructions */
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/* ftcprint (features1, 6, "fpdx"); */ /* FP data ptr upd on exc */
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/* ftcprint (features1, 6, "fpdx"); */ /* "" FP data ptr upd on exc */
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ftcprint (features1, 7, "smep"); /* super mode exec prot */
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ftcprint (features1, 8, "bmi2"); /* bit manip ext group 2 */
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ftcprint (features1, 9, "erms"); /* enh rep movsb/stosb */
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ftcprint (features1, 10, "invpcid"); /* inv proc context id */
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ftcprint (features1, 11, "rtm"); /* restricted txnal mem */
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ftcprint (features1, 12, "cqm"); /* cache QoS monitoring */
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/* ftcprint (features1, 13, "fpcsdsz"); */ /* zero FP cs/ds */
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/* ftcprint (features1, 13, "fpcsdsz"); */ /* "" zero FP cs/ds */
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ftcprint (features1, 14, "mpx"); /* mem prot ext */
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ftcprint (features1, 15, "rdt_a"); /* rsrc dir tech alloc */
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ftcprint (features1, 16, "avx512f"); /* vec foundation */
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@ -1242,9 +1439,9 @@ format_proc_cpuinfo (void *, char *&destbuf)
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||||
/* more random feature flags */
|
||||
/* cpuid 0x0000000d:1 eax */
|
||||
if (maxf >= 0x0d)
|
||||
if (maxf >= 0x0000000d)
|
||||
{
|
||||
cpuid (&features1, &unused, &unused, &unused, 0x0d, 1);
|
||||
cpuid (&features1, &unused, &unused, &unused, 0x0000000d, 1);
|
||||
|
||||
ftcprint (features1, 0, "xsaveopt"); /* xsaveopt instruction */
|
||||
ftcprint (features1, 1, "xsavec"); /* xsavec instruction */
|
||||
@ -1252,23 +1449,26 @@ format_proc_cpuinfo (void *, char *&destbuf)
|
||||
ftcprint (features1, 3, "xsaves"); /* xsaves/xrstors */
|
||||
}
|
||||
/* cpuid 0x0000000f edx */
|
||||
if (maxf >= 0x0f)
|
||||
if (maxf >= 0x0000000f)
|
||||
{
|
||||
cpuid (&unused, &unused, &unused, &features1, 0x0f);
|
||||
cpuid (&unused, &unused, &unused, &features1, 0x0000000f);
|
||||
|
||||
ftcprint (features1, 1, "cqm_llc"); /* llc QoS */
|
||||
|
||||
/* cpuid 0x0000000f:1 edx */
|
||||
cpuid (&unused, &unused, &unused, &features1, 0x0f, 1);
|
||||
cpuid (&unused, &unused, &unused, &features1, 0x0000000f, 1);
|
||||
|
||||
ftcprint (features1, 0, "cqm_occup_llc"); /* llc occup monitor */
|
||||
ftcprint (features1, 1, "cqm_mbm_total"); /* llc total MBM mon */
|
||||
ftcprint (features1, 2, "cqm_mbm_local"); /* llc local MBM mon */
|
||||
}
|
||||
|
||||
/* ftcprint (features1, 6, "split_lock_detect");*//* MSR_TEST_CTRL split lock */
|
||||
|
||||
/* cpuid 0x00000007:1 eax */
|
||||
if (maxf >= 0x07)
|
||||
if (maxf >= 0x00000007)
|
||||
{
|
||||
cpuid (&features1, &unused, &unused, &unused, 0x07, 1);
|
||||
cpuid (&features1, &unused, &unused, &unused, 0x00000007, 1);
|
||||
|
||||
ftcprint (features1, 5, "avx512_bf16"); /* vec bfloat16 short */
|
||||
}
|
||||
@ -1287,7 +1487,9 @@ format_proc_cpuinfo (void *, char *&destbuf)
|
||||
/* ftcprint (features1, 12, "ibpb" ); */ /* ind br pred barrier */
|
||||
/* ftcprint (features1, 14, "ibrs" ); */ /* ind br restricted spec */
|
||||
/* ftcprint (features1, 15, "stibp"); */ /* 1 thread ind br pred */
|
||||
/* ftcprint (features1, 16, "ibrs_enhanced");*//* IBRS_ALL enhanced IBRS always on */
|
||||
/* ftcprint (features1, 17, "stibp_always_on"); */ /* stibp always on */
|
||||
/* ftcprint (features1, 18, "ibrs_pref");*//* IBRS_PREF IBRS preferred */
|
||||
ftcprint (features1, 23, "amd_ppin"); /* protected proc id no */
|
||||
/* ftcprint (features1, 24, "ssbd"); */ /* spec store byp dis */
|
||||
ftcprint (features1, 25, "virt_ssbd"); /* vir spec store byp dis */
|
||||
@ -1295,9 +1497,9 @@ format_proc_cpuinfo (void *, char *&destbuf)
|
||||
}
|
||||
|
||||
/* thermal & power cpuid 0x00000006 eax */
|
||||
if (maxf >= 0x06)
|
||||
if (maxf >= 0x00000006)
|
||||
{
|
||||
cpuid (&features1, &unused, &features2, &unused, 0x06);
|
||||
cpuid (&features1, &unused, &features2, &unused, 0x00000006);
|
||||
|
||||
ftcprint (features1, 0, "dtherm"); /* digital thermal sensor */
|
||||
ftcprint (features1, 1, "ida"); /* Intel dynamic acceleration */
|
||||
@ -1332,9 +1534,9 @@ format_proc_cpuinfo (void *, char *&destbuf)
|
||||
}
|
||||
|
||||
/* Intel cpuid 0x00000007 ecx */
|
||||
if (is_intel && maxf >= 0x07)
|
||||
if (is_intel && maxf >= 0x00000007)
|
||||
{
|
||||
cpuid (&unused, &unused, &features1, &unused, 0x07, 0);
|
||||
cpuid (&unused, &unused, &features1, &unused, 0x00000007, 0);
|
||||
|
||||
ftcprint (features1, 1, "avx512vbmi"); /* vec bit manip */
|
||||
ftcprint (features1, 2, "umip"); /* user mode ins prot */
|
||||
@ -1367,9 +1569,9 @@ format_proc_cpuinfo (void *, char *&destbuf)
|
||||
}
|
||||
|
||||
/* Intel cpuid 0x00000007 edx */
|
||||
if (is_intel && maxf >= 0x07)
|
||||
if (is_intel && maxf >= 0x00000007)
|
||||
{
|
||||
cpuid (&unused, &unused, &unused, &features1, 0x07, 0);
|
||||
cpuid (&unused, &unused, &unused, &features1, 0x00000007, 0);
|
||||
|
||||
ftcprint (features1, 2, "avx512_4vnniw"); /* vec dot prod dw */
|
||||
ftcprint (features1, 3, "avx512_4fmaps"); /* vec 4 FMA single */
|
||||
@ -1377,6 +1579,7 @@ format_proc_cpuinfo (void *, char *&destbuf)
|
||||
ftcprint (features1, 8, "avx512_vp2intersect"); /* vec intcpt d/q */
|
||||
ftcprint (features1, 10, "md_clear"); /* verw clear buf */
|
||||
ftcprint (features1, 18, "pconfig"); /* platform config */
|
||||
ftcprint (features1, 19, "arch_lbr"); /* last branch records */
|
||||
ftcprint (features1, 28, "flush_l1d"); /* flush l1d cache */
|
||||
ftcprint (features1, 29, "arch_capabilities"); /* arch cap MSR */
|
||||
}
|
||||
@ -1386,6 +1589,16 @@ format_proc_cpuinfo (void *, char *&destbuf)
|
||||
bufptr += __small_sprintf (bufptr, "bogomips\t: %d.00\n",
|
||||
bogomips);
|
||||
|
||||
/* cpuid 0x80000006 ebx TLB size */
|
||||
if (maxe >= 0x80000006)
|
||||
{
|
||||
cpuid( &unused, &features1, &unused, &unused, 0x80000006, 0);
|
||||
uint32_t tlbsize = ((features1 >> 16) & 0xfff) + (features1 & 0xfff);
|
||||
if (tlbsize > 0)
|
||||
bufptr += __small_sprintf (bufptr, "TLB size\t: %d 4K pages\n",
|
||||
tlbsize);
|
||||
}
|
||||
|
||||
bufptr += __small_sprintf (bufptr, "clflush size\t: %d\n"
|
||||
"cache_alignment\t: %d\n",
|
||||
clflush,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user