ARC: Use new definitions for optional ARC CPU features
GCC for ARC has been updated to provide consistent naming of preprocessor
definitions for different optional architecture features:
* __ARC_BARREL_SHIFTER__ instead of __Xbarrel_shifter for
-mbarrel-shifter
* __ARC_LL64__ instead of __LL64__ for -mll64
* __ARCEM__ instead of __EM__ for -mcpu=arcem
* __ARCHS__ instead of __HS__ for -mcpu=archs
* etc (not used in newlib)
This patch updates assembly routines for ARC to use new definitions instead
of a deprecated ones. To ensure compatibility with older compiler new
definitions are also defined in asm.h if needed, based on deprecated
preprocessor definitions.
*** newlib/ChangeLog ***
2015-12-15 Anton Kolesov <Anton.Kolesov@synopsys.com>
* libc/machine/arc/asm.h: Define new GCC definition for old compiler.
* libc/machine/arc/memcmp-bs-norm.S: Use new GCC defines to detect
processor features.
* libc/machine/arc/memcmp.S: Likewise.
* libc/machine/arc/memcpy-archs.S: Likewise.
* libc/machine/arc/memcpy-bs.S: Likewise.
* libc/machine/arc/memcpy.S: Likewise.
* libc/machine/arc/memset-archs.S: Likewise.
* libc/machine/arc/memset-bs.S: Likewise.
* libc/machine/arc/memset.S: Likewise.
* libc/machine/arc/setjmp.S: Likewise.
* libc/machine/arc/strchr-bs-norm.S: Likewise.
* libc/machine/arc/strchr-bs.S: Likewise.
* libc/machine/arc/strchr.S: Likewise.
* libc/machine/arc/strcmp-archs.S: Likewise.
* libc/machine/arc/strcmp.S: Likewise.
* libc/machine/arc/strcpy-bs-arc600.S: Likewise.
* libc/machine/arc/strcpy-bs.S: Likewise.
* libc/machine/arc/strcpy.S: Likewise.
* libc/machine/arc/strlen-bs-norm.S: Likewise.
* libc/machine/arc/strlen-bs.S: Likewise.
* libc/machine/arc/strlen.S: Likewise.
* libc/machine/arc/strncpy-bs.S: Likewise.
* libc/machine/arc/strncpy.S: Likewise.
Signed-off-by: Anton Kolesov <Anton.Kolesov@synopsys.com>
This commit is contained in:
Anton Kolesov
Corinna Vinschen
parent
088f7a7239
commit
06537f05d4
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@ -1,3 +1,30 @@
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2015-12-17 Anton Kolesov <Anton.Kolesov@synopsys.com>
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* libc/machine/arc/asm.h: Define new GCC definition for old compiler.
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* libc/machine/arc/memcmp-bs-norm.S: Use new GCC defines to detect
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processor features.
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* libc/machine/arc/memcmp.S: Likewise.
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* libc/machine/arc/memcpy-archs.S: Likewise.
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* libc/machine/arc/memcpy-bs.S: Likewise.
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* libc/machine/arc/memcpy.S: Likewise.
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* libc/machine/arc/memset-archs.S: Likewise.
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* libc/machine/arc/memset-bs.S: Likewise.
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* libc/machine/arc/memset.S: Likewise.
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* libc/machine/arc/setjmp.S: Likewise.
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* libc/machine/arc/strchr-bs-norm.S: Likewise.
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* libc/machine/arc/strchr-bs.S: Likewise.
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* libc/machine/arc/strchr.S: Likewise.
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* libc/machine/arc/strcmp-archs.S: Likewise.
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* libc/machine/arc/strcmp.S: Likewise.
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* libc/machine/arc/strcpy-bs-arc600.S: Likewise.
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* libc/machine/arc/strcpy-bs.S: Likewise.
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* libc/machine/arc/strcpy.S: Likewise.
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* libc/machine/arc/strlen-bs-norm.S: Likewise.
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* libc/machine/arc/strlen-bs.S: Likewise.
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* libc/machine/arc/strlen.S: Likewise.
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* libc/machine/arc/strncpy-bs.S: Likewise.
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* libc/machine/arc/strncpy.S: Likewise.
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2015-12-17 Corinna Vinschen <corinna@vinschen.de>
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* libc/include/sys/types.h: Remove including <sys/select.h>.
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@ -61,4 +61,22 @@
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#define bcc_s bhs_s
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/* Compatibility with older ARC GCC, that doesn't provide some of the
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preprocessor defines used by newlib for ARC. */
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#if defined (__Xbarrel_shifter) && !defined (__ARC_BARREL_SHIFTER__)
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#define __ARC_BARREL_SHIFTER__ 1
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#endif
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#if defined (__EM__) && !defined (__ARCEM__)
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#define __ARCEM__ 1
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#endif
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#if defined (__HS__) && !defined (__ARCHS__)
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#define __ARCHS__ 1
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#endif
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#if defined (__LL64__) && !defined (__ARC_LL64__)
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#define __ARC_LL64__ 1
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#endif
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#endif /* ARC_NEWLIB_ASM_H */
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@ -35,7 +35,9 @@
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#include "asm.h"
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#if !defined (__ARC601__) && defined (__ARC_NORM__) && defined (__Xbarrel_shifter)
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#if !defined (__ARC601__) && defined (__ARC_NORM__) \
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&& defined (__ARC_BARREL_SHIFTER__)
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#ifdef __LITTLE_ENDIAN__
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#define WORD2 r2
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#define SHIFT r3
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@ -47,7 +49,7 @@
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ENTRY (memcmp)
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or r12,r0,r1
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asl_s r12,r12,30
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#if defined (__ARC700__) || defined (__EM__) || defined (__HS__)
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#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
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sub_l r3,r2,1
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brls r2,r12,.Lbytewise
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#else
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@ -57,7 +59,7 @@ ENTRY (memcmp)
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ld r4,[r0,0]
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ld r5,[r1,0]
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lsr.f lp_count,r3,3
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#ifdef __EM__
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#ifdef __ARCEM__
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/* A branch can't be the last instruction in a zero overhead loop.
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So we move the branch to the start of the loop, duplicate it
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after the end, and set up r12 so that the branch isn't taken
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@ -74,12 +76,12 @@ ENTRY (memcmp)
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brne r4,r5,.Leven
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ld.a r4,[r0,8]
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ld.a r5,[r1,8]
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#ifdef __EM__
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#ifdef __ARCEM__
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.Loop_end:
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brne WORD2,r12,.Lodd
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#else
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brne WORD2,r12,.Lodd
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#ifdef __HS__
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#ifdef __ARCHS__
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nop
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#endif
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.Loop_end:
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@ -90,7 +92,7 @@ ENTRY (memcmp)
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ld r4,[r0,4]
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ld r5,[r1,4]
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#ifdef __LITTLE_ENDIAN__
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#if defined (__ARC700__) || defined (__EM__) || defined (__HS__)
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#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
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nop_s
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; one more load latency cycle
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.Last_cmp:
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@ -167,14 +169,14 @@ ENTRY (memcmp)
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bset.cs r0,r0,31
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.Lodd:
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cmp_s WORD2,r12
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#if defined (__ARC700__) || defined (__EM__) || defined (__HS__)
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#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
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mov_s r0,1
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j_s.d [blink]
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bset.cs r0,r0,31
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#else /* !__ARC700__ */
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#else
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j_s.d [blink]
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rrc r0,2
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#endif /* !__ARC700__ */
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#endif /* __ARC700__ || __ARCEM__ || __ARCHS__ */
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#endif /* ENDIAN */
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.balign 4
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.Lbytewise:
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@ -182,7 +184,7 @@ ENTRY (memcmp)
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ldb r4,[r0,0]
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ldb r5,[r1,0]
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lsr.f lp_count,r3
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#ifdef __EM__
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#ifdef __ARCEM__
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mov r12,r3
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lpne .Lbyte_end
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brne r3,r12,.Lbyte_odd
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@ -194,12 +196,12 @@ ENTRY (memcmp)
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brne r4,r5,.Lbyte_even
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ldb.a r4,[r0,2]
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ldb.a r5,[r1,2]
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#ifdef __EM__
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#ifdef __ARCEM__
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.Lbyte_end:
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brne r3,r12,.Lbyte_odd
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#else
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brne r3,r12,.Lbyte_odd
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#ifdef __HS__
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#ifdef __ARCHS__
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nop
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#endif
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.Lbyte_end:
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@ -218,6 +220,6 @@ ENTRY (memcmp)
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j_s.d [blink]
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mov_l r0,0
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ENDFUNC (memcmp)
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#endif /* !__ARC601__ && __ARC_NORM__ && __Xbarrel_shifter */
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#endif /* !__ARC601__ && __ARC_NORM__ && __ARC_BARREL_SHIFTER__ */
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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#include "asm.h"
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#if defined (__ARC601__) || !defined (__ARC_NORM__) || !defined (__Xbarrel_shifter)
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#if defined (__ARC601__) || !defined (__ARC_NORM__) \
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|| !defined (__ARC_BARREL_SHIFTER__)
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/* Addresses are unsigned, and at 0 is the vector table, so it's OK to assume
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that we can subtract 8 from a source end address without underflow. */
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@ -148,6 +149,6 @@ ENTRY (memcmp)
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j_s.d [blink]
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mov_s r0,0
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ENDFUNC (memcmp)
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#endif /* __ARC601__ || !__ARC_NORM__ || !__Xbarrel_shifter */
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#endif /* __ARC601__ || !__ARC_NORM__ || !__ARC_BARREL_SHIFTER__ */
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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#include "asm.h"
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#if defined (__HS__)
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#if defined (__ARCHS__)
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#ifdef __LITTLE_ENDIAN__
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# define SHIFT_1(RX,RY,IMM) asl RX, RY, IMM ; <<
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# define EXTRACT_2(RX,RY,IMM) lsr RX, RY, 0x08
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#endif
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#ifdef __LL64__
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#ifdef __ARC_LL64__
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# define PREFETCH_READ(RX) prefetch [RX, 56]
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# define PREFETCH_WRITE(RX) prefetchw [RX, 64]
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# define LOADX(DST,RX) ldd.ab DST, [RX, 8]
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@ -263,6 +263,6 @@ ENTRY (memcpy)
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j [blink]
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ENDFUNC (memcpy)
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#endif /* __HS__ */
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#endif /* __ARCHS__ */
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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#include "asm.h"
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#if !defined (__ARC601__) && !defined (__HS__) && defined (__Xbarrel_shifter)
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#if !defined (__ARC601__) && !defined (__ARCHS__) \
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&& defined (__ARC_BARREL_SHIFTER__)
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/* Mostly optimized for ARC700, but not bad for ARC600 either. */
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/* This memcpy implementation does not support objects of 1GB or larger -
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the check for alignment does not work then. */
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@ -98,6 +100,6 @@ ENTRY (memcpy)
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j_s.d [blink]
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stb r12,[r5,0]
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ENDFUNC (memcpy)
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#endif /* !__ARC601__ && !__HS__ && __Xbarrel_shifter */
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#endif /* !__ARC601__ && !__ARCHS__ && __ARC_BARREL_SHIFTER__ */
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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@ -35,7 +35,9 @@
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#include "asm.h"
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#if defined (__ARC601__) || (!defined (__Xbarrel_shifter) && !defined (__HS__))
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#if defined (__ARC601__) || \
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(!defined (__ARC_BARREL_SHIFTER__) && !defined (__ARCHS__))
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/* Adapted from memcpy-bs.S. */
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/* We assume that most sources and destinations are aligned, and
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that also lengths are mostly a multiple of four, although to a lesser
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@ -104,6 +106,6 @@ ENTRY (memcpy)
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j_s.d [blink]
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stb r12,[r5,0]
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ENDFUNC (memcpy)
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#endif /* __ARC601__ || (!__Xbarrel_shifter && !__HS__) */
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#endif /* __ARC601__ || (!__ARC_BARREL_SHIFTER__ && !__ARCHS__) */
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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@ -35,7 +35,7 @@
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#include "asm.h"
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#ifdef __HS__
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#ifdef __ARCHS__
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#ifdef USE_PREFETCH
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#define PREWRITE(A,B) prefetchw [(A),(B)]
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@ -81,7 +81,7 @@ ENTRY (memset)
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lpnz @.Lset64bytes
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; LOOP START
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PREWRITE (r3, 64) ;Prefetch the next write location
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#ifdef __LL64__
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#ifdef __ARC_LL64__
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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@ -114,7 +114,7 @@ ENTRY (memset)
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lpnz .Lset32bytes
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; LOOP START
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prefetchw [r3, 32] ;Prefetch the next write location
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#ifdef __LL64__
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#ifdef __ARC_LL64__
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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std.ab r4, [r3, 8]
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@ -141,6 +141,6 @@ ENTRY (memset)
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j [blink]
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ENDFUNC (memset)
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#endif /* __HS__ */
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#endif /* __ARCHS__ */
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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@ -42,7 +42,7 @@
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better would be to avoid a second entry point into function. ARC HS always
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has barrel-shifter, so this implementation will be always used for this
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purpose. */
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#if !defined (__ARC601__) && defined (__Xbarrel_shifter)
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#if !defined (__ARC601__) && defined (__ARC_BARREL_SHIFTER__)
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/* To deal with alignment/loop issues, SMALL must be at least 2. */
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#define SMALL 7
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@ -57,12 +57,12 @@
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cases, because the copying of a string presumably leaves start address
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and length alignment for the zeroing randomly distributed. */
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#ifdef __HS__
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#ifdef __ARCHS__
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ENTRY (__dummy_memset)
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#else
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ENTRY (memset)
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#endif
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#if !defined (__ARC700__) && !defined (__EM__)
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#if !defined (__ARC700__) && !defined (__ARCEM__)
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#undef SMALL
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#define SMALL 8 /* Even faster if aligned. */
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brls.d r2,SMALL,.Ltiny
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@ -74,7 +74,7 @@ ENTRY (memset)
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asl r12,r1,8
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beq.d .Laligned
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or_s r1,r1,r12
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#if defined (__ARC700__) || defined (__EM__)
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#if defined (__ARC700__) || defined (__ARCEM__)
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brls r2,SMALL,.Ltiny
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#endif
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.Lnot_tiny:
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@ -90,7 +90,7 @@ ENTRY (memset)
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stw.ab r1,[r3,2]
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bclr_s r3,r3,1
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.Laligned: ; This code address should be aligned for speed.
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#if defined (__ARC700__) || defined (__EM__)
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#if defined (__ARC700__) || defined (__ARCEM__)
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asl r12,r1,16
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lsr.f lp_count,r2,2
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or_s r1,r1,r12
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@ -111,7 +111,7 @@ ENTRY (memset)
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st_s r1,[r3]
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#endif /* !__ARC700 */
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#if defined (__ARC700__) || defined (__EM__)
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#if defined (__ARC700__) || defined (__ARCEM__)
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.balign 4
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__strncpy_bzero:
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brhi.d r2,17,.Lnot_tiny
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@ -144,11 +144,11 @@ __strncpy_bzero:
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stb_s r1,[r3]
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j_s [blink]
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#endif /* !__ARC700 */
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#ifdef __HS__
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#ifdef __ARCHS__
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ENDFUNC (__dummy_memset)
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#else
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ENDFUNC (memset)
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#endif
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#endif /* !__ARC601__ && __Xbarrel_shifter */
|
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#endif /* !__ARC601__ && __ARC_BARREL_SHIFTER__ */
|
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
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|
|
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|
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@ -35,7 +35,8 @@
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|
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#include "asm.h"
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|
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#if defined (__ARC601__) || (!defined (__Xbarrel_shifter) && !defined (__HS__))
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#if defined (__ARC601__) \
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|| (!defined (__ARC_BARREL_SHIFTER__) && !defined (__ARCHS__))
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/* To deal with alignment/loop issues, SMALL must be at least 2. */
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#define SMALL 8 /* Even faster if aligned. */
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|
|
@ -104,6 +105,6 @@ __strncpy_bzero:
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stb_s r1,[r3]
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j_s [blink]
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ENDFUNC (memset)
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#endif /* __ARC601__ || (!__Xbarrel_shifter && !__HS__) */
|
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#endif /* __ARC601__ || (!__ARC_BARREL_SHIFTER__ && !__ARCHS__) */
|
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|
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#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
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|
|
|
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|
|
@ -92,7 +92,7 @@ setjmp:
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st r2, [r0, ABIlps]
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st r3, [r0, ABIlpe]
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#if (!defined (__A7__) && !defined (__EM__) && !defined (__HS__))
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#if (!defined (__ARC700__) && !defined (__ARCEM__) && !defined (__ARCHS__))
|
||||
; Till the configure changes are decided, and implemented, the code working on
|
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; mlo/mhi and using mul64 should be disabled.
|
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; st mlo, [r0, ABImlo]
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|
|
@ -145,7 +145,7 @@ longjmp:
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sr r2, [lp_start]
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sr r3, [lp_end]
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#if (!defined (__A7__) && !defined (__EM__) && !defined (__HS__))
|
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#if (!defined (__ARC700__) && !defined (__ARCEM__) && !defined (__ARCHS__))
|
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ld r2, [r0, ABImlo]
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ld r3, [r0, ABImhi]
|
||||
; We do not support restoring of mulhi and mlo registers, yet.
|
||||
|
|
|
|||
|
|
@ -39,8 +39,8 @@
|
|||
words branch-free. */
|
||||
#include "asm.h"
|
||||
|
||||
#if (defined (__ARC700__) || defined (__EM__) || defined (__HS__)) \
|
||||
&& defined (__ARC_NORM__) && defined (__Xbarrel_shifter)
|
||||
#if (defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)) \
|
||||
&& defined (__ARC_NORM__) && defined (__ARC_BARREL_SHIFTER__)
|
||||
|
||||
ENTRY (strchr)
|
||||
extb_s r1,r1
|
||||
|
|
@ -160,6 +160,7 @@ ENTRY (strchr)
|
|||
mov.mi r0,0
|
||||
#endif /* ENDIAN */
|
||||
ENDFUNC (strchr)
|
||||
#endif /* (__ARC700__ || __EM__ || __HS__) && __ARC_NORM__ && __Xbarrel_shifter */
|
||||
#endif /* (__ARC700__ || __ARCEM__ || __ARCHS__) && __ARC_NORM__
|
||||
&& __ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -49,8 +49,9 @@
|
|||
Each byte in Y is 0x80 if the the corresponding byte in
|
||||
W is zero, otherwise that byte of Y is 0. */
|
||||
|
||||
#if defined (__Xbarrel_shifter) && \
|
||||
#if defined (__ARC_BARREL_SHIFTER__) && \
|
||||
(defined (__ARC600__) || (!defined (__ARC_NORM__) && !defined (__ARC601__)))
|
||||
|
||||
ENTRY (strchr)
|
||||
bmsk.f r2,r0,1
|
||||
mov_s r3,0x01010101
|
||||
|
|
@ -195,6 +196,7 @@ ENTRY (strchr)
|
|||
add.eq r0,r0,1
|
||||
#endif /* ENDIAN */
|
||||
ENDFUNC (strchr)
|
||||
#endif /* __Xbarrel_shifter && (__ARC600__ || (!__ARC_NORM__ && !__ARC601__)) */
|
||||
#endif /* __ARC_BARREL_SHIFTER__ &&
|
||||
(__ARC600__ || (!__ARC_NORM__ && !__ARC601__)) */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@
|
|||
Each byte in Y is 0x80 if the the corresponding byte in
|
||||
W is zero, otherwise that byte of Y is 0. */
|
||||
|
||||
#if defined (__ARC601__) || !defined (__Xbarrel_shifter)
|
||||
#if defined (__ARC601__) || !defined (__ARC_BARREL_SHIFTER__)
|
||||
ENTRY (strchr)
|
||||
bmsk.f r2,r0,1
|
||||
mov_s r3,0x01010101
|
||||
|
|
@ -203,6 +203,6 @@ ENTRY (strchr)
|
|||
add.eq r0,r0,1
|
||||
#endif /* ENDIAN */
|
||||
ENDFUNC (strchr)
|
||||
#endif /* __ARC601__ || !__Xbarrel_shifter */
|
||||
#endif /* __ARC601__ || !__ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
#include "asm.h"
|
||||
|
||||
#ifdef __HS__
|
||||
#ifdef __ARCHS__
|
||||
ENTRY (strcmp)
|
||||
or r2, r0, r1
|
||||
bmsk_s r2, r2, 1
|
||||
|
|
@ -104,6 +104,6 @@ ENTRY (strcmp)
|
|||
j_s.d [blink]
|
||||
sub r0, r2, r3
|
||||
ENDFUNC (strcmp)
|
||||
#endif /* __HS__ */
|
||||
#endif /* __ARCHS__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
by a factor of two, and speculatively loading the second word / byte of
|
||||
source 1; however, that would increase the overhead for loop setup / finish,
|
||||
and strcmp might often terminate early. */
|
||||
#ifndef __HS__
|
||||
#ifndef __ARCHS__
|
||||
|
||||
ENTRY (strcmp)
|
||||
or r2,r0,r1
|
||||
|
|
@ -128,6 +128,6 @@ ENTRY (strcmp)
|
|||
j_s.d [blink]
|
||||
sub r0,r2,r3
|
||||
ENDFUNC (strcmp)
|
||||
#endif /* !__HS__ */
|
||||
#endif /* !__ARCHS__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
#include "asm.h"
|
||||
|
||||
#if defined (__ARC600__) && defined (__Xbarrel_shifter)
|
||||
#if defined (__ARC600__) && defined (__ARC_BARREL_SHIFTER__)
|
||||
/* If dst and src are 4 byte aligned, copy 8 bytes at a time.
|
||||
If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
|
||||
it 8 byte aligned. Thus, we can do a little read-ahead, without
|
||||
|
|
@ -115,6 +115,6 @@ ENTRY (strcpy)
|
|||
stb.ab r3,[r10,1]
|
||||
j [blink]
|
||||
ENDFUNC (strcpy)
|
||||
#endif /* __ARC600__ && __Xbarrel_shifter */
|
||||
#endif /* __ARC600__ && __ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -35,8 +35,8 @@
|
|||
|
||||
#include "asm.h"
|
||||
|
||||
#if (defined (__ARC700__) || defined (__EM__) || defined (__HS__)) \
|
||||
&& defined (__Xbarrel_shifter)
|
||||
#if (defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)) \
|
||||
&& defined (__ARC_BARREL_SHIFTER__)
|
||||
|
||||
/* If dst and src are 4 byte aligned, copy 8 bytes at a time.
|
||||
If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
|
||||
|
|
@ -98,6 +98,6 @@ charloop:
|
|||
stb.ab r3,[r10,1]
|
||||
j [blink]
|
||||
ENDFUNC (strcpy)
|
||||
#endif /* (__ARC700__ || __EM__ || __HS__) && __Xbarrel_shifter */
|
||||
#endif /* (__ARC700__ || __ARCEM__ || __ARCHS__) && __ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
#include "asm.h"
|
||||
|
||||
#if defined (__ARC601__) || !defined (__Xbarrel_shifter)
|
||||
#if defined (__ARC601__) || !defined (__ARC_BARREL_SHIFTER__)
|
||||
/* If dst and src are 4 byte aligned, copy 8 bytes at a time.
|
||||
If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
|
||||
it 8 byte aligned. Thus, we can do a little read-ahead, without
|
||||
|
|
@ -85,6 +85,6 @@ ENTRY (strcpy)
|
|||
stb.ab r3,[r10,1]
|
||||
j_s [blink]
|
||||
ENDFUNC (strcpy)
|
||||
#endif /* __ARC601__ || !__Xbarrel_shifter */
|
||||
#endif /* __ARC601__ || !__ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -34,8 +34,8 @@
|
|||
#if !defined (__OPTIMIZE_SIZE__) && !defined (PREFER_SIZE_OVER_SPEED)
|
||||
|
||||
#include "asm.h"
|
||||
#if (defined (__ARC700__) || defined (__EM__) || defined (__HS__)) \
|
||||
&& defined (__ARC_NORM__) && defined (__Xbarrel_shifter)
|
||||
#if (defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)) \
|
||||
&& defined (__ARC_NORM__) && defined (__ARC_BARREL_SHIFTER__)
|
||||
|
||||
ENTRY (strlen)
|
||||
or r3,r0,7
|
||||
|
|
@ -110,6 +110,7 @@ ENTRY (strlen)
|
|||
b.d .Lend
|
||||
sub_s.ne r1,r1,r1
|
||||
ENDFUNC (strlen)
|
||||
#endif /* (__ARC700__ || __EM__ || __HS__) && __ARC_NORM__ && _Xbarrel_shifter */
|
||||
#endif /* (__ARC700__ || __ARCEM__ || __ARCHS__) && __ARC_NORM__
|
||||
&& __ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
#include "asm.h"
|
||||
|
||||
#if (defined (__ARC600__) || !defined (__ARC_NORM__)) && !defined (__ARC601__) \
|
||||
&& defined (__Xbarrel_shifter)
|
||||
&& defined (__ARC_BARREL_SHIFTER__)
|
||||
/* This code is optimized for the ARC600 pipeline. */
|
||||
|
||||
ENTRY (strlen)
|
||||
|
|
@ -117,6 +117,6 @@ ENTRY (strlen)
|
|||
b.d .Lend
|
||||
sub_s.ne r1,r1,r1
|
||||
ENDFUNC (strlen)
|
||||
#endif /* (__ARC600__ || !__ARC_NORM__) && !__ARC601__ && __Xbarrel_shifter */
|
||||
#endif /* (__ARC600__ || !__ARC_NORM__) && !__ARC601__ && __ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
#include "asm.h"
|
||||
|
||||
#if defined(__ARC601__) || !defined (__Xbarrel_shifter)
|
||||
#if defined(__ARC601__) || !defined (__ARC_BARREL_SHIFTER__)
|
||||
/* This code is optimized for the ARC601 pipeline without barrel shifter. */
|
||||
|
||||
ENTRY (strlen)
|
||||
|
|
@ -160,6 +160,6 @@ ENTRY (strlen)
|
|||
sub_s.ne r1,r1,r1
|
||||
#endif /* !SPECIAL_EARLY_END */
|
||||
ENDFUNC (strlen)
|
||||
#endif /* __ARC601__ || !__Xbarrel_shifter*/
|
||||
#endif /* __ARC601__ || !__ARC_BARREL_SHIFTER__*/
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -45,9 +45,9 @@
|
|||
there, but the it is not likely to be taken often, and it
|
||||
would also be likey to cost an unaligned mispredict at the next call. */
|
||||
|
||||
#if !defined (__ARC601__) && defined (__Xbarrel_shifter)
|
||||
#if !defined (__ARC601__) && defined (__ARC_BARREL_SHIFTER__)
|
||||
|
||||
#if defined (__ARC700___) || defined (__EM__) || defined (__HS__)
|
||||
#if defined (__ARC700___) || defined (__ARCEM__) || defined (__ARCHS__)
|
||||
#define BRand(a,b,l) tst a,b ` bne_l l
|
||||
#else
|
||||
#define BRand(a,b,l) and a,a,b ` brne_s a,0,l
|
||||
|
|
@ -112,7 +112,7 @@ ENTRY (strncpy)
|
|||
.Lr4z:
|
||||
mov_l r3,r4
|
||||
.Lr3z:
|
||||
#if defined (__ARC700__) || defined (__EM__) || defined (__HS__)
|
||||
#if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__)
|
||||
#ifdef __LITTLE_ENDIAN__
|
||||
bmsk.f r1,r3,7
|
||||
lsr_s r3,r3,8
|
||||
|
|
@ -166,6 +166,6 @@ ENTRY (strncpy)
|
|||
j_s.d [blink]
|
||||
stb_l r12,[r3]
|
||||
ENDFUNC (strncpy)
|
||||
#endif /* !__ARC601__ && __Xbarrel_shifter */
|
||||
#endif /* !__ARC601__ && __ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
it 8 byte aligned. Thus, we can do a little read-ahead, without
|
||||
dereferencing a cache line that we should not touch. */
|
||||
|
||||
#if defined (__ARC601__) || !defined (__Xbarrel_shifter)
|
||||
#if defined (__ARC601__) || !defined (__ARC_BARREL_SHIFTER__)
|
||||
|
||||
#define BRand(a,b,l) and a,a,b ` brne_s a,0,l
|
||||
|
||||
|
|
@ -129,6 +129,6 @@ ENTRY (strncpy)
|
|||
j_s.d [blink]
|
||||
stb_s r12,[r3]
|
||||
ENDFUNC (strncpy)
|
||||
#endif /* __ARC601__ || !__Xbarrel_shifter */
|
||||
#endif /* __ARC601__ || !__ARC_BARREL_SHIFTER__ */
|
||||
|
||||
#endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */
|
||||
|
|
|
|||
Loading…
Reference in New Issue