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This commit was manufactured by cvs2svn to create branch 'msnyder- 

reverse-20060502-branch'.

Sprout from readline_5_1-import-branch 2006-04-19 00:58:00 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'readline_5_1'
Cherrypick from master 2006-04-30 18:34:39 UTC Thiemo Seufer <ths@networkno.de> '[ gas/ChangeLog ]':
    include/ChangeLog
    include/opcode/ChangeLog
    include/opcode/arm.h
    include/opcode/mips.h
This commit is contained in:
cvs2svn 2006-04-30 18:34:40 +00:00
parent b86926951d
commit 0565597a7a
4 changed files with 58 additions and 7 deletions
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5
include/ChangeLog
View File

@ -17,6 +17,11 @@
R_BFIN_GOTOFFLO): New relocs.
(EF_BFIN_PIC, EF_BFIN_FDPIC, EF_BFIN_PIC_FLAGS): New macros.
2006-03-23 Michael Matz <matz@suse.de>
* elf/x86-64.h: Add the new relocations with their official
numbers.
2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
Anil Paranjape <anilp1@kpitcummins.com>
Shilin Shakti <shilins@kpitcummins.com>

22
include/opcode/ChangeLog
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@ -1,4 +1,24 @@
2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
2006-04-30 Thiemo Seufer <ths@mips.com>
David Ung <davidu@mips.com>
* mips.h: Defines udi bits and masks. Add description of
characters which may appear in the args field of udi
instructions.
2006-04-26 Thiemo Seufer <ths@networkno.de>
* mips.h: Improve comments describing the bitfield instruction
fields.
2006-04-26 Julian Brown <julian@codesourcery.com>
* arm.h (FPU_VFP_EXT_V3): Define constant.
(FPU_NEON_EXT_V1): Likewise.
(FPU_VFP_HARD): Update.
(FPU_VFP_V3): Define macro.
(FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
* avr.h (AVR_ISA_PWMx): New.

10
include/opcode/arm.h
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@ -58,6 +58,8 @@
#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */
#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */
/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@ -105,7 +107,9 @@
#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2)
#define FPU_VFP_V3 (FPU_VFP_V2 | FPU_VFP_EXT_V3)
#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
| FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1)
#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
/* Deprecated */
@ -117,6 +121,10 @@
#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)

28
include/opcode/mips.h
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@ -203,6 +203,16 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US
#define MDMX_FMTSEL_VEC_QH 0x15
#define MDMX_FMTSEL_VEC_OB 0x16
/* UDI */
#define OP_SH_UDI1 6
#define OP_MASK_UDI1 0x1f
#define OP_SH_UDI2 6
#define OP_MASK_UDI2 0x3ff
#define OP_SH_UDI3 6
#define OP_MASK_UDI3 0x7fff
#define OP_SH_UDI4 6
#define OP_MASK_UDI4 0xfffff
/* This structure holds information for a particular instruction. */
struct mips_opcode
@ -268,19 +278,20 @@ struct mips_opcode
"x" accept and ignore register name
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
"+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
LSB (OP_*_SHAMT).
Enforces: 0 <= pos < 32.
"+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
"+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
"+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
"+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
(Also used by "dext" w/ different limits, but limits for
that are checked by the M_DEXT macro.)
"+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
"+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
Enforces: 32 <= pos < 64.
"+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
"+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
@ -350,6 +361,12 @@ struct mips_opcode
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
UDI immediates:
"+1" UDI immediate bits 6-10
"+2" UDI immediate bits 6-15
"+3" UDI immediate bits 6-20
"+4" UDI immediate bits 6-25
Other:
"()" parens surrounding optional value
"," separates operands
@ -364,6 +381,7 @@ struct mips_opcode
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
"1234"
"ABCDEFGHIT"
"t"
*/