2015-02-17 17:26:54 +08:00
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/*
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* Copyright (c) 2015 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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.thumb
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.syntax unified
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.global __aeabi_memset
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.type __aeabi_memset, %function
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ASM_ALIAS __aeabi_memset4 __aeabi_memset
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ASM_ALIAS __aeabi_memset8 __aeabi_memset
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__aeabi_memset:
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push {r4, r5, r6, lr}
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lsls r3, r0, #30
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2015-06-01 18:49:37 +08:00
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beq 10f
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2015-02-17 17:26:54 +08:00
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subs r4, r1, #1
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cmp r1, #0
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2015-06-01 18:49:37 +08:00
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beq 9f
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lsls r5, r2, #24
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lsrs r5, r5, #24
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2015-02-17 17:26:54 +08:00
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movs r3, r0
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2015-06-01 18:49:37 +08:00
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movs r6, #3
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b 2f
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1:
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2015-02-17 17:26:54 +08:00
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subs r1, r4, #1
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cmp r4, #0
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2015-06-01 18:49:37 +08:00
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beq 9f
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2015-02-17 17:26:54 +08:00
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movs r4, r1
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2015-06-01 18:49:37 +08:00
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2:
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2015-02-17 17:26:54 +08:00
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adds r3, r3, #1
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subs r1, r3, #1
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2015-06-01 18:49:37 +08:00
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strb r5, [r1]
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tst r3, r6
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bne 1b
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3:
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2015-02-17 17:26:54 +08:00
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cmp r4, #3
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2015-06-01 18:49:37 +08:00
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bls 7f
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2015-02-17 17:26:54 +08:00
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movs r5, #255
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ands r5, r2
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lsls r1, r5, #8
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orrs r5, r1
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lsls r1, r5, #16
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orrs r5, r1
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cmp r4, #15
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2015-06-01 18:49:37 +08:00
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bls 5f
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2015-02-17 17:26:54 +08:00
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movs r6, r4
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subs r6, r6, #16
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lsrs r6, r6, #4
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adds r6, r6, #1
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lsls r6, r6, #4
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movs r1, r3
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adds r3, r3, r6
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2015-06-01 18:49:37 +08:00
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4:
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2015-02-17 17:26:54 +08:00
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str r5, [r1]
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str r5, [r1, #4]
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str r5, [r1, #8]
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str r5, [r1, #12]
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adds r1, r1, #16
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cmp r3, r1
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2015-06-01 18:49:37 +08:00
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bne 4b
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2015-02-17 17:26:54 +08:00
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movs r1, #15
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ands r4, r1
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cmp r4, #3
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2015-06-01 18:49:37 +08:00
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bls 7f
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5:
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2015-02-17 17:26:54 +08:00
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subs r6, r4, #4
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lsrs r6, r6, #2
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adds r6, r6, #1
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lsls r6, r6, #2
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movs r1, r3
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adds r3, r3, r6
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2015-06-01 18:49:37 +08:00
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6:
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2015-02-17 17:26:54 +08:00
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stmia r1!, {r5}
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cmp r3, r1
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2015-06-01 18:49:37 +08:00
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bne 6b
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2015-02-17 17:26:54 +08:00
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movs r1, #3
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ands r4, r1
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2015-06-01 18:49:37 +08:00
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7:
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2015-02-17 17:26:54 +08:00
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cmp r4, #0
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2015-06-01 18:49:37 +08:00
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beq 9f
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lsls r2, r2, #24
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lsrs r2, r2, #24
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2015-02-17 17:26:54 +08:00
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adds r4, r3, r4
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2015-06-01 18:49:37 +08:00
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8:
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2015-02-17 17:26:54 +08:00
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strb r2, [r3]
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adds r3, r3, #1
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cmp r4, r3
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2015-06-01 18:49:37 +08:00
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bne 8b
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9:
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pop {r4, r5, r6}
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pop {r1}
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bx r1
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10:
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2015-02-17 17:26:54 +08:00
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movs r3, r0
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2015-06-01 18:49:37 +08:00
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movs r4, r1
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b 3b
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2015-02-17 17:26:54 +08:00
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.size __aeabi_memset, . - __aeabi_memset
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