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107 lines
3.2 KiB
ArmAsm
107 lines
3.2 KiB
ArmAsm
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/*
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Copyright (c) 2024, Synopsys, Inc. All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1) Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2) Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3) Neither the name of the Synopsys, Inc., nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/asm.h>
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/* ABI interface file
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these are the stack mappings for the registers
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as stored in the ABI for ARC */
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ABIr14 = 0
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ABIr15 = ABIr14 + REG_SZ
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ABIr16 = ABIr15 + REG_SZ
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ABIr17 = ABIr16 + REG_SZ
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ABIr18 = ABIr17 + REG_SZ
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ABIr19 = ABIr18 + REG_SZ
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ABIr20 = ABIr19 + REG_SZ
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ABIr21 = ABIr20 + REG_SZ
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ABIr22 = ABIr21 + REG_SZ
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ABIr23 = ABIr22 + REG_SZ
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ABIr24 = ABIr23 + REG_SZ
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ABIr25 = ABIr24 + REG_SZ
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ABIr26 = ABIr25 + REG_SZ
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ABIr27 = ABIr26 + REG_SZ
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ABIr28 = ABIr27 + REG_SZ
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ABIr29 = ABIr28 + REG_SZ
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ABIr30 = ABIr29 + REG_SZ
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ABIr31 = ABIr30 + REG_SZ
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ENTRY (setjmp)
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REG_ST r14, [r0, ABIr14]
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REG_ST r15, [r0, ABIr15]
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REG_ST r16, [r0, ABIr16]
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REG_ST r17, [r0, ABIr17]
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REG_ST r18, [r0, ABIr18]
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REG_ST r19, [r0, ABIr19]
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REG_ST r20, [r0, ABIr20]
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REG_ST r21, [r0, ABIr21]
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REG_ST r22, [r0, ABIr22]
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REG_ST r23, [r0, ABIr23]
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REG_ST r24, [r0, ABIr24]
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REG_ST r25, [r0, ABIr25]
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REG_ST r26, [r0, ABIr26]
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REG_ST r27, [r0, ABIr27]
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REG_ST r28, [r0, ABIr28]
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REG_ST r29, [r0, ABIr29]
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REG_ST r30, [r0, ABIr30]
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REG_ST blink, [r0, ABIr31]
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j.d [blink]
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mov r0,0
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.size setjmp,.-setjmp
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ENTRY (longjmp)
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; load registers
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REG_LD r14, [r0, ABIr14]
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REG_LD r15, [r0, ABIr15]
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REG_LD r16, [r0, ABIr16]
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REG_LD r17, [r0, ABIr17]
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REG_LD r18, [r0, ABIr18]
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REG_LD r19, [r0, ABIr19]
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REG_LD r20, [r0, ABIr20]
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REG_LD r21, [r0, ABIr21]
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REG_LD r22, [r0, ABIr22]
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REG_LD r23, [r0, ABIr23]
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REG_LD r24, [r0, ABIr24]
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REG_LD r25, [r0, ABIr25]
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REG_LD r26, [r0, ABIr26]
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REG_LD r27, [r0, ABIr27]
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REG_LD r28, [r0, ABIr28]
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REG_LD r29, [r0, ABIr29]
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REG_LD r30, [r0, ABIr30]
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REG_LD blink, [r0, ABIr31]
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mov.f r1, r1 ; to avoid return 0 from longjmp
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mov.z r1, 1
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j.d [blink]
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mov r0,r1
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.size longjmp,.-longjmp
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