2007-11-29 20:23:44 +08:00
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2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
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* mips.h (INSN_LOONGSON_2E): New.
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(INSN_LOONGSON_2F): New.
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(CPU_LOONGSON_2E): New.
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(CPU_LOONGSON_2F): New.
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(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
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2007-11-29 19:55:19 +08:00
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2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
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* mips.h (INSN_ISA*): Redefine certain values as an
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enumeration. Update comments.
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(mips_isa_table): New.
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(ISA_MIPS*): Redefine to match enumeration.
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(OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
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values.
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binutils/
* doc/binutils.texi (objdump): Document -Mppcps.
gas/
* config/tc-ppc.c (parse_cpu): Handle "750cl".
(pre_defined_registers): Add "gqr0" to "gqr7", "gqr.0" to "gqr.7".
(md_show_usage): Document -m750cl.
(md_assemble): Handle two delimiters in succession (eg. `),').
* doc/c-ppc.texi (PowerPC-Opts): Document -m750cl.
* testsuite/gas/ppc/ppc.exp: Run ppc70ps dump tests.
* testsuite/gas/ppc/ppc750ps.s: New file.
* testsuite/gas/ppc/ppc750ps.d: Likewise.
include/opcode/
* ppc.h (PPC_OPCODE_PPCPS): New.
opcodes/
* ppc-opc.c (PSW, PSWM, PSQ, PSQM, PSD, MTMSRD_L): New.
(XOPS, XOPS_MASK, XW, XW_MASK): Likewise.
(PPCPS): Likewise.
(powerpc_opcodes): Add all pair singles instructions.
* ppc-dis.c (powerpc_dialect): Handle "ppcps".
(print_ppc_disassembler_options): Document -Mppcps.
2007-08-24 08:56:30 +08:00
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2007-08-08 Ben Elliston <bje@au.ibm.com>
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* ppc.h (PPC_OPCODE_PPCPS): New.
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2007-08-01 23:27:55 +08:00
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2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
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* m68k.h: Document j K & E.
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2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
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2007-06-29 22:09:34 +08:00
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* cr16.h: New file for CR16 target.
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2007-05-02 19:24:17 +08:00
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2007-05-02 Alan Modra <amodra@bigpond.net.au>
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* ppc.h (PPC_OPERAND_PLUS1): Update comment.
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gas/testsuite/
* gas/m68k/br-isaa.s: New.
* gas/m68k/br-isaa.d: New.
* gas/m68k/br-isab.s: New.
* gas/m68k/br-isab.d: New.
* gas/m68k/br-isac.s: New.
* gas/m68k/br-isac.d: New.
* gas/m68k/all.exp: Adjust.
gas/
* config/tc-m68k.c (mcf54455_ctrl): New.
(HAVE_LONG_DISP, HAVE_LONG_CALL, HAVE_LONG_COND): New.
(m68k_archs): Add isac.
(m68k_cpus): Add 54455 family.
(m68k_ip): Split Bg into Bb, Bs, Bg.
(m68k_elf_final_processing): Add ISA_C.
* doc/c-m68k.texi (M680x0 Options): Add isac.
include/opcode/
* m68k.h (mcfisa_c): New.
(mcfusp, mcf_mask): Adjust.
bfd/
* archures.c (bfd_mach_mcf_isa_c, bfd_mach_mcf_isa_c_mac,
bfd_mach_mcf_isa_c_emac): New.
* elf32-m68k.c (ISAC_PLT_ENTRY_SIZE, elf_isac_plt0_entry,
elf_isac_plt_entry, elf_isac_plt_info): New.
(elf32_m68k_object_p): Add ISA_C.
(elf32_m68k_print_private_bfd_data): Print ISA_C.
(elf32_m68k_get_plt_info): Detect ISA_C.
* cpu-m68k.c (arch_info): Add ISAC.
(m68k_arch_features): Likewise,
(bfd_m68k_compatible): ISAs B & C are not compatible.
opcodes/
* m68k-opc.c: Mark mcfisa_c instructions.
2007-04-23 15:51:30 +08:00
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2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
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* m68k.h (mcfisa_c): New.
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(mcfusp, mcf_mask): Adjust.
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include/opcode/
* ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
(num_powerpc_operands): Declare.
(PPC_OPERAND_SIGNED et al): Redefine as hex.
(PPC_OPERAND_PLUS1): Define.
opcodes/
* ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand
change.
* ppc-opc.c (powerpc_operands): Replace bit count with bit mask
in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove
references to following deleted functions.
(insert_bd, extract_bd, insert_dq, extract_dq): Delete.
(insert_ds, extract_ds, insert_de, extract_de): Delete.
(insert_des, extract_des, insert_li, extract_li): Delete.
(insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete.
(insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete.
(num_powerpc_operands): New constant.
(XSPRG_MASK): Remove entire SPRG field.
(powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
gas/
* messages.c (as_internal_value_out_of_range): Extend to report
errors for values with invalid low bits set.
* config/tc-ppc.c (ppc_setup_opcodes): Check powerpc_operands bitm
fields. Check that operands and opcode fields are disjoint.
(ppc_insert_operand): Check operands using mask rather than bit
count. Check low bits too. Handle PPC_OPERAND_PLUS1. Adjust
insertion code.
(md_apply_fix): Adjust for struct powerpc_operand change.
2007-04-20 20:25:12 +08:00
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2007-04-20 Alan Modra <amodra@bigpond.net.au>
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* ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
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(num_powerpc_operands): Declare.
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(PPC_OPERAND_SIGNED et al): Redefine as hex.
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(PPC_OPERAND_PLUS1): Define.
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2007-03-28 06:45:19 +08:00
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2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
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2007-03-22 05:23:43 +08:00
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* i386.h (REX_MODE64): Renamed to ...
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(REX_W): This.
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(REX_EXTX): Renamed to ...
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(REX_R): This.
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(REX_EXTY): Renamed to ...
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(REX_X): This.
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(REX_EXTZ): Renamed to ...
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(REX_B): This.
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2007-03-15 22:31:24 +08:00
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2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386.h: Add entries from config/tc-i386.h and move tables
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to opcodes/i386-opc.h.
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2007-03-14 11:26:06 +08:00
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2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
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* i386.h (FloatDR): Removed.
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(i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
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2007-03-01 19:17:41 +08:00
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2007-03-01 Alan Modra <amodra@bigpond.net.au>
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* spu-insns.h: Add soma double-float insns.
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[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 21:28:54 +08:00
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2007-02-20 Thiemo Seufer <ths@mips.com>
|
2007-03-14 11:26:06 +08:00
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Chao-Ying Fu <fu@mips.com>
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 21:28:54 +08:00
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* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
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(INSN_DSPR2): Add flag for DSP R2 instructions.
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(M_BALIGN): New macro.
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2007-02-14 07:23:53 +08:00
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2007-02-14 Alan Modra <amodra@bigpond.net.au>
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* i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
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and Seg3ShortFrom with Shortform.
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2007-02-12 12:51:40 +08:00
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2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/4027
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* i386.h (i386_optab): Put the real "test" before the pseudo
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one.
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2007-01-09 02:42:37 +08:00
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2007-01-08 Kazu Hirata <kazu@codesourcery.com>
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* m68k.h (m68010up): OR fido_a.
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bfd/
* archures.c (bfd_mach_cpu32_fido): New.
(bfd_mach_mcf_isa_a_nodiv, bfd_mach_mcf_isa_a,
bfd_mach_mcf_isa_a_mac, bfd_mach_mcf_isa_a_emac,
bfd_mach_mcf_isa_aplus, bfd_mach_mcf_isa_aplus_mac,
bfd_mach_mcf_isa_aplus_emac, bfd_mach_mcf_isa_b_nousp,
bfd_mach_mcf_isa_b_nousp_mac, bfd_mach_mcf_isa_b_nousp_emac,
bfd_mach_mcf_isa_b, bfd_mach_mcf_isa_b_mac,
bfd_mach_mcf_isa_b_emac, bfd_mach_mcf_isa_b_float,
bfd_mach_mcf_isa_b_float_mac, bfd_mach_mcf_isa_b_float_emac):
Increment the defined values.
* bfd-in2.h: Regenerate.
* cpu-m68k.c (arch_info_struct): Add en entry for
bfd_mach_cpu32_fido.
* elf32-m68k.c (elf32_m68k_object_p): Handle
EF_M68K_CPU32_FIDO_A.
(elf32_m68k_merge_private_bfd_data): Use EF_M68K_CPU32_MASK.
(elf32_m68k_print_private_bfd_data): Handle
EF_M68K_CPU32_FIDO_A.
binutils/
* readelf.c (get_machine_flags): Handle EF_M68K_CPU32_FIDO_A.
gas/
* config/tc-m68k.c (cpu_of_arch): Add fido.
(m68k_archs, m68k_cpu): Add entries for fido.
(m68k_elf_final_processing): Handle EF_M68K_CPU32_FIDO_A.
include/elf/
* m68k.h (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): New.
include/opcode/
* m68k.h (fido_a): New.
2006-12-26 06:39:21 +08:00
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2006-12-25 Kazu Hirata <kazu@codesourcery.com>
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* m68k.h (fido_a): New.
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2006-12-24 10:58:37 +08:00
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2006-12-24 Kazu Hirata <kazu@codesourcery.com>
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* m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
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mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
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values.
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2006-11-09 03:56:02 +08:00
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2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
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* i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
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2006-10-31 17:54:41 +08:00
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2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
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* score-inst.h (enum score_insn_type): Add Insn_internal.
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2006-10-25 14:49:18 +08:00
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2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
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Yukishige Shibata <shibata@rd.scei.sony.co.jp>
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Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
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Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
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Alan Modra <amodra@bigpond.net.au>
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* spu-insns.h: New file.
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* spu.h: New file.
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2006-10-24 09:27:28 +08:00
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2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
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* ppc.h (PPC_OPCODE_CELL): Define.
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2006-10-24 06:53:28 +08:00
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2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
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* i386.h : Modify opcode to support for the change in POPCNT opcode
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in amdfam10 architecture.
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2006-09-28 22:06:36 +08:00
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2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
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|
|
* i386.h: Replace CpuMNI with CpuSSSE3.
|
|
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|
bfd/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* archures.c: Add definition for bfd_mach_arm_iWMMXt2.
* cpu-arm.c (processors): Add bfd_mach_arm_iWMMXt2.
(arch_info_struct, bfd_arm_update_notes): Likewise.
(architectures): Likewise.
(bfd_arm_merge_machines): Check for iWMMXt2.
* bfd-in2.h: Rebuild.
gas/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* config/tc-arm.c (arm_cext_iwmmxt2): New.
(enum operand_parse_code): New code OP_RIWR_I32z.
(parse_operands): Handle OP_RIWR_I32z.
(do_iwmmxt_wmerge): New function.
(do_iwmmxt_wldstd): Handle iwmmxt2 case where second operand is
a register.
(do_iwmmxt_wrwrwr_or_imm5): New function.
(insns): Mark instructions as RIWR_I32z as appropriate.
Also add torvsc<b,h,w>, wabs<b,h,w>, wabsdiff<b,h,w>,
waddbhus<l,m>, waddhc, waddwc, waddsubhx, wavg4{r}, wmaddu{x,n},
wmadds{x,n}, wmerge, wmiaxy{n}, wmiawxy{n}, wmul<sm,um>{r},
wmulw<um,sm,l>{r}, wqmiaxy{n}, wqmulm{r}, wqmulwm{r}, wsubaddhx.
(md_begin): Handle IWMMXT2.
(arm_cpus): Add iwmmxt2.
(arm_extensions): Likewise.
(arm_archs): Likewise.
gas/testsuite/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* gas/arm/iwmmxt2.s: New file.
* gas/arm/iwmmxt2.d: New file.
include/opcode/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
opcodes/
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Ian Lance Taylor <ian@wasabisystems.com>
Ben Elliston <bje@wasabisystems.com>
* arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
only be used with the default multiply-add operation, so if N is
set, don't bother printing X. Add new iwmmxt instructions.
(IWMMXT_INSN_COUNT): Update.
(iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
with a 'c' suffix.
(print_insn_coprocessor): Check for iWMMXt2. Handle format
specifiers 'r', 'i'.
2006-09-26 20:04:45 +08:00
|
|
|
|
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
|
|
|
|
|
|
Joseph Myers <joseph@codesourcery.com>
|
|
|
|
|
|
Ian Lance Taylor <ian@wasabisystems.com>
|
|
|
|
|
|
Ben Elliston <bje@wasabisystems.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
|
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|
2006-09-17 07:51:50 +08:00
|
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|
2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
|
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|
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|
* score-datadep.h: New file.
|
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|
* score-inst.h: New file.
|
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|
2006-07-15 00:15:27 +08:00
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|
2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
|
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|
|
* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
|
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|
movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
|
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|
movdq2q and movq2dq.
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2006-07-14 06:25:48 +08:00
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2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
|
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Michael Meissner <michael.meissner@amd.com>
|
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* i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
|
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2006-06-13 02:59:36 +08:00
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2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
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* i386.h (i386_optab): Add "nop" with memory reference.
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|
gas/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Don't add rex64 for
"xchg %rax,%rax".
gas/testsuite/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/opcode.s: Add "xchg %ax,%ax".
* gas/i386/opcode.d: Updated.
* gas/i386/x86-64-opcode.s: Add xchg %ax,%ax, xchg %eax,%eax,
xchg %rax,%rax, rex64 xchg %rax,%rax and xchg %rax,%r8.
* gas/i386/x86-64-opcode.d: Updated.
include/opcode/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Update comment for 64bit NOP.
opcodes/
2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (NOP_Fixup): Removed.
(NOP_Fixup1): New.
(NOP_Fixup2): Likewise.
(dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
2006-06-13 02:55:42 +08:00
|
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2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
|
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* i386.h (i386_optab): Update comment for 64bit NOP.
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2006-06-07 13:23:59 +08:00
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2006-06-06 Ben Elliston <bje@au.ibm.com>
|
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Anton Blanchard <anton@samba.org>
|
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|
* ppc.h (PPC_OPCODE_POWER6): Define.
|
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|
Adjust whitespace.
|
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2006-06-06 00:28:36 +08:00
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2006-06-05 Thiemo Seufer <ths@mips.com>
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* mips.h: Improve description of MT flags.
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2006-05-25 16:09:03 +08:00
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2006-05-25 Richard Sandiford <richard@codesourcery.com>
|
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* m68k.h (mcf_mask): Define.
|
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|
2006-05-05 23:41:23 +08:00
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2006-05-05 Thiemo Seufer <ths@mips.com>
|
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|
David Ung <davidu@mips.com>
|
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|
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|
|
* mips.h (enum): Add macro M_CACHE_AB.
|
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|
[ gas/testsuite/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
* gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2.
* gas/mips/set-arch.d: Adjust according to opcode table changes.
[ include/opcode/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips.h: Add INSN_SMARTMIPS define.
[ opcodes/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips-dis.c (mips_arch_choices): Add smartmips instruction
decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
MIPS64R2.
* mips-opc.c: fix random typos in comments.
(INSN_SMARTMIPS): New defines.
(mips_builtin_opcodes): Add paired single support for MIPS32R2.
Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
FP_S and FP_D flags to denote single and double register
accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
for MIPS32R2. Add SmartMIPS instructions. Add two-argument
variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
release 2 ISAs.
* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
2006-05-04 18:47:05 +08:00
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2006-05-04 Thiemo Seufer <ths@mips.com>
|
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Nigel Stephens <nigel@mips.com>
|
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|
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|
|
David Ung <davidu@mips.com>
|
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|
|
* mips.h: Add INSN_SMARTMIPS define.
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2006-05-01 02:34:39 +08:00
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2006-04-30 Thiemo Seufer <ths@mips.com>
|
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|
|
David Ung <davidu@mips.com>
|
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|
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* mips.h: Defines udi bits and masks. Add description of
|
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|
characters which may appear in the args field of udi
|
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|
instructions.
|
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|
2006-04-27 02:19:15 +08:00
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2006-04-26 Thiemo Seufer <ths@networkno.de>
|
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|
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* mips.h: Improve comments describing the bitfield instruction
|
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|
fields.
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2006-04-30 00:54:51 +08:00
|
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2006-04-26 Julian Brown <julian@codesourcery.com>
|
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|
|
* arm.h (FPU_VFP_EXT_V3): Define constant.
|
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|
(FPU_NEON_EXT_V1): Likewise.
|
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|
(FPU_VFP_HARD): Update.
|
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|
(FPU_VFP_V3): Define macro.
|
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|
(FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
|
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|
2006-04-27 02:19:15 +08:00
|
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|
|
2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
|
Add support for attiny261, attiny461, attiny861, attiny25, attiny45,
attiny85, attiny24, attiny44, attiny84, at90pwm2, at90pwm3, atmega164,
atmega324, atmega644, atmega329, atmega3290, atmega649, atmega6490,
atmega406, atmega640, atmega1280, atmega1281, at90can32, at90can64,
at90usb646, at90usb647, at90usb1286 and at90usb1287.
Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
2006-04-07 23:18:08 +08:00
|
|
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|
|
|
|
|
|
* avr.h (AVR_ISA_PWMx): New.
|
|
|
|
|
|
|
gas:
* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
m68020_control_regs, m68040_control_regs, m68060_control_regs,
mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl,
mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
mcf5282_ctrl, mcfv4e_ctrl): ... these.
(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
(struct m68k_cpu): Change chip field to control_regs.
(current_chip): Remove.
(control_regs): New.
(m68k_archs, m68k_extensions): Adjust.
(m68k_cpus): Reorder to be in cpu number order. Adjust.
(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
(find_cf_chip): Reimplement for new organization of cpu table.
(select_control_regs): Remove.
(mri_chip): Adjust.
(struct save_opts): Save control regs, not chip.
(s_save, s_restore): Adjust.
(m68k_lookup_cpu): Give deprecated warning when necessary.
(m68k_init_arch): Adjust.
(md_show_usage): Adjust for new cpu table organization.
include/opcodes:
* m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
2006-03-28 15:19:16 +08:00
|
|
|
|
2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
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|
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|
|
* m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
|
|
|
|
|
|
cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
|
|
|
|
|
|
cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
|
|
|
|
|
|
cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
|
|
|
|
|
|
cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
|
|
|
|
|
|
|
2006-03-11 01:16:49 +08:00
|
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|
|
2006-03-10 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
|
|
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|
|
2006-03-05 06:11:48 +08:00
|
|
|
|
2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
|
|
|
|
|
|
first. Correct mask of bb "B" opcode.
|
|
|
|
|
|
|
2006-02-27 23:35:37 +08:00
|
|
|
|
2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Support Intel Merom New Instructions.
|
|
|
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
gas/
* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
(struct asm_barrier_opt): Define.
(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
(parse_psr): Accept V7M psr names.
(parse_barrier): New function.
(enum operand_parse_code): Add OP_oBARRIER.
(parse_operands): Implement OP_oBARRIER.
(do_barrier): New function.
(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
(do_t_cpsi): Add V7M restrictions.
(do_t_mrs, do_t_msr): Validate V7M variants.
(md_assemble): Check for NULL variants.
(v7m_psrs, barrier_opt_names): New tables.
(insns): Add V7 instructions. Mark V6 instructions absent from V7M.
(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
(struct cpu_arch_ver_table): Define.
(cpu_arch_ver): New.
(aeabi_set_public_attributes): Use cpu_arch_ver. Set
Tag_CPU_arch_profile.
* doc/c-arm.texi: Document new cpu and arch options.
gas/testsuite/
* gas/arm/thumb32.d: Fix expected msr and mrs output.
* gas/arm/arch7.d: New test.
* gas/arm/arch7.s: New test.
* gas/arm/arch7m-bad.l: New test.
* gas/arm/arch7m-bad.d: New test.
* gas/arm/arch7m-bad.s: New test.
include/opcode/
* arm.h: Add V7 feature bits.
opcodes/
* arm-dis.c (arm_opcodes): Add V7 instructions.
(thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
(print_arm_address): New function.
(print_insn_arm): Use it. Add 'P' and 'U' cases.
(psr_name): New function.
(print_insn_thumb32): Add 'U', 'C' and 'D' cases.
2006-02-24 23:36:36 +08:00
|
|
|
|
2006-02-24 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h: Add V7 feature bits.
|
|
|
|
|
|
|
2006-02-24 05:36:17 +08:00
|
|
|
|
2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
|
|
|
|
|
|
|
2006-01-31 Paul Brook <paul@codesourcery.com>
Richard Earnshaw <rearnsha@arm.com>
* gas/config/tc-arm.c: Use arm_feature_set.
(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
New variables.
(insns): Use them.
(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
feature flags.
(arm_legacy_option_table, arm_option_cpu_value_table): New types.
(arm_opts): Move old cpu/arch options from here...
(arm_legacy_opts): ... to here.
(md_parse_option): Search arm_legacy_opts.
(arm_cpus, arm_archs, arm_extensions, arm_fpus)
(arm_float_abis, arm_eabis): Make const.
* include/opcode/arm.h: Use ARM_CPU_FEATURE.
(ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
(arm_feature_set): Change to a structure.
(ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
ARM_FEATURE): New macros.
2006-01-31 22:11:13 +08:00
|
|
|
|
2006-01-31 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h: Use ARM_CPU_FEATURE.
|
|
|
|
|
|
(ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
|
|
|
|
|
|
(arm_feature_set): Change to a structure.
|
|
|
|
|
|
(ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
|
|
|
|
|
|
ARM_FEATURE): New macros.
|
|
|
|
|
|
|
2005-12-07 20:53:57 +08:00
|
|
|
|
2005-12-07 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
|
|
|
|
|
|
(MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
|
|
|
|
|
|
(ADD_PC_INCR_OPCODE): Don't define.
|
|
|
|
|
|
|
2005-12-06 20:40:57 +08:00
|
|
|
|
2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/1874
|
|
|
|
|
|
* i386.h (i386_optab): Add 64bit support for monitor and mwait.
|
|
|
|
|
|
|
2005-11-14 10:25:39 +08:00
|
|
|
|
2005-11-14 David Ung <davidu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
|
|
|
|
|
|
instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
|
|
|
|
|
|
save/restore encoding of the args field.
|
|
|
|
|
|
|
2005-10-29 03:38:59 +08:00
|
|
|
|
2005-10-28 Dave Brolley <brolley@redhat.com>
|
|
|
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|
|
|
|
|
|
|
|
Contribute the following changes:
|
|
|
|
|
|
2005-02-16 Dave Brolley <brolley@redhat.com>
|
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|
|
|
|
|
|
|
|
* cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
|
|
|
|
|
|
cgen_isa_mask_* to cgen_bitset_*.
|
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|
|
|
|
* cgen.h: Likewise.
|
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|
|
2005-10-29 03:41:01 +08:00
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|
2003-10-21 Richard Sandiford <rsandifo@redhat.com>
|
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|
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|
|
* cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
|
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|
|
(CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
|
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|
|
(CGEN_CPU_TABLE): Make isas a ponter.
|
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|
2003-09-29 Dave Brolley <brolley@redhat.com>
|
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|
|
* cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
|
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|
|
|
(CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
|
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|
|
|
(CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
|
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|
2002-12-13 Dave Brolley <brolley@redhat.com>
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|
|
* cgen.h (symcat.h): #include it.
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|
(cgen-bitset.h): #include it.
|
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|
|
(CGEN_ATTR_VALUE_TYPE): Now a union.
|
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|
|
(CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
|
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|
|
(CGEN_ATTR_ENTRY): 'value' now unsigned.
|
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|
|
(cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
|
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|
|
* cgen-bitset.h: New file.
|
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|
|
2005-10-26 01:40:19 +08:00
|
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|
2005-09-30 Catherine Moore <clm@cm00re.com>
|
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|
|
* bfin.h: New file.
|
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|
2005-10-24 15:42:50 +08:00
|
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|
2005-10-24 Jan Beulich <jbeulich@novell.com>
|
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|
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|
|
* ia64.h (enum ia64_opnd): Move memory operand out of set of
|
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|
|
indirect operands.
|
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|
|
2005-10-17 04:42:14 +08:00
|
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|
2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
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|
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|
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|
|
* hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
|
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|
|
Add FLAG_STRICT to pa10 ftest opcode.
|
|
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|
|
2005-10-13 10:26:34 +08:00
|
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|
2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
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|
|
* hppa.h (pa_opcodes): Remove lha entries.
|
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|
2005-10-09 03:01:29 +08:00
|
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|
|
2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
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|
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|
|
|
|
* hppa.h (FLAG_STRICT): Revise comment.
|
|
|
|
|
|
(pa_opcode): Revise ordering rules. Add/move strict pa10 variants
|
|
|
|
|
|
before corresponding pa11 opcodes. Add strict pa10 register-immediate
|
|
|
|
|
|
entries for "fdc".
|
|
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|
|
|
|
2005-09-25 10:33:54 +08:00
|
|
|
|
2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
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|
|
|
|
|
|
|
|
* hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
|
|
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|
|
|
* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
define.
Document !, $, *, &, g, +t, +T operand formats for MT instructions.
(INSN_ASE_MASK): Update to include INSN_MT.
(INSN_MT): New define for MT ASE.
2005-09-07 02:42:58 +08:00
|
|
|
|
2005-09-06 Chao-ying Fu <fu@mips.com>
|
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|
|
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|
|
|
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|
|
* mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
|
|
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|
|
|
OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
|
|
|
|
|
|
define.
|
|
|
|
|
|
Document !, $, *, &, g, +t, +T operand formats for MT instructions.
|
|
|
|
|
|
(INSN_ASE_MASK): Update to include INSN_MT.
|
|
|
|
|
|
(INSN_MT): New define for MT ASE.
|
|
|
|
|
|
|
* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
instructions.
(INSN_DSP): New define for DSP ASE.
2005-08-26 02:09:24 +08:00
|
|
|
|
2005-08-25 Chao-ying Fu <fu@mips.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
|
|
|
|
|
|
OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
|
|
|
|
|
|
OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
|
|
|
|
|
|
OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
|
|
|
|
|
|
OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
|
|
|
|
|
|
Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
|
|
|
|
|
|
instructions.
|
|
|
|
|
|
(INSN_DSP): New define for DSP ASE.
|
|
|
|
|
|
|
2005-08-18 11:59:23 +08:00
|
|
|
|
2005-08-18 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* a29k.h: Delete.
|
|
|
|
|
|
|
2005-08-15 23:37:15 +08:00
|
|
|
|
2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc.h (PPC_OPCODE_E300): Define.
|
|
|
|
|
|
|
2005-08-13 02:02:38 +08:00
|
|
|
|
2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
|
|
|
|
|
|
|
2005-07-29 04:32:21 +08:00
|
|
|
|
2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/336
|
|
|
|
|
|
* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
|
|
|
|
|
|
and pitlb.
|
|
|
|
|
|
|
2005-07-27 15:04:31 +08:00
|
|
|
|
2005-07-27 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Add comment to movd. Use LongMem for all
|
|
|
|
|
|
movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
|
|
|
|
|
|
Add movq-s as 64-bit variants of movd-s.
|
|
|
|
|
|
|
2005-07-19 08:11:48 +08:00
|
|
|
|
2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
|
|
|
|
|
2005-07-19 11:09:33 +08:00
|
|
|
|
* hppa.h: Fix punctuation in comment.
|
|
|
|
|
|
|
2005-07-19 08:11:48 +08:00
|
|
|
|
* hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
|
|
|
|
|
|
implicit space-register addressing. Set space-register bits on opcodes
|
|
|
|
|
|
using implicit space-register addressing. Add various missing pa20
|
|
|
|
|
|
long-immediate opcodes. Remove various opcodes using implicit 3-bit
|
|
|
|
|
|
space-register addressing. Use "fE" instead of "fe" in various
|
|
|
|
|
|
fstw opcodes.
|
|
|
|
|
|
|
2005-07-18 14:11:00 +08:00
|
|
|
|
2005-07-18 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Operands of aam and aad are unsigned.
|
|
|
|
|
|
|
2005-07-15 21:49:53 +08:00
|
|
|
|
2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Support Intel VMX Instructions.
|
|
|
|
|
|
|
2005-07-11 10:31:34 +08:00
|
|
|
|
2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
|
|
|
|
|
|
|
2005-07-05 15:16:53 +08:00
|
|
|
|
2005-07-05 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Add new insns.
|
|
|
|
|
|
|
2005-07-01 19:16:27 +08:00
|
|
|
|
2005-07-01 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* sparc.h: Add typedefs to structure declarations.
|
|
|
|
|
|
|
2005-06-21 07:18:38 +08:00
|
|
|
|
2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 1013
|
|
|
|
|
|
* i386.h (i386_optab): Update comments for 64bit addressing on
|
|
|
|
|
|
mov. Allow 64bit addressing for mov and movq.
|
|
|
|
|
|
|
2005-06-11 23:33:52 +08:00
|
|
|
|
2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
|
|
|
|
|
|
respectively, in various floating-point load and store patterns.
|
|
|
|
|
|
|
2005-05-24 00:26:43 +08:00
|
|
|
|
2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
|
|
|
|
|
|
|
|
|
|
|
|
* hppa.h (FLAG_STRICT): Correct comment.
|
|
|
|
|
|
(pa_opcodes): Update load and store entries to allow both PA 1.X and
|
|
|
|
|
|
PA 2.0 mneumonics when equivalent. Entries with cache control
|
|
|
|
|
|
completers now require PA 1.1. Adjust whitespace.
|
|
|
|
|
|
|
2005-05-19 14:59:36 +08:00
|
|
|
|
2005-05-19 Anton Blanchard <anton@samba.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc.h (PPC_OPCODE_POWER5): Define.
|
|
|
|
|
|
|
2005-05-10 18:21:13 +08:00
|
|
|
|
2005-05-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Update the address and phone number of the FSF organization in
|
|
|
|
|
|
the GPL notices in the following files:
|
|
|
|
|
|
a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
|
|
|
|
|
|
crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
|
|
|
|
|
|
i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
|
|
|
|
|
|
mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
|
|
|
|
|
|
pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
|
|
|
|
|
|
tic54x.h, tic80.h, v850.h, vax.h
|
|
|
|
|
|
|
2005-05-09 14:49:01 +08:00
|
|
|
|
2005-05-09 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Add ht and hnt.
|
|
|
|
|
|
|
2005-04-19 04:59:19 +08:00
|
|
|
|
2005-04-18 Mark Kettenis <kettenis@gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h: Insert hyphens into selected VIA PadLock extensions.
|
|
|
|
|
|
Add xcrypt-ctr. Provide aliases without hyphens.
|
|
|
|
|
|
|
2005-04-14 00:53:25 +08:00
|
|
|
|
2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
2005-04-14 01:33:48 +08:00
|
|
|
|
Moved from ../ChangeLog
|
|
|
|
|
|
|
2005-04-14 00:53:25 +08:00
|
|
|
|
2005-04-12 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
* m88k.h: Rename psr macros to avoid conflicts.
|
|
|
|
|
|
|
|
|
|
|
|
2005-03-12 Zack Weinberg <zack@codesourcery.com>
|
|
|
|
|
|
* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
|
|
|
|
|
|
Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
|
|
|
|
|
|
and ARM_ARCH_V6ZKT2.
|
|
|
|
|
|
|
|
|
|
|
|
2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
|
|
|
|
|
|
Remove redundant instruction types.
|
|
|
|
|
|
(struct argument): X_op - new field.
|
|
|
|
|
|
(struct cst4_entry): Remove.
|
|
|
|
|
|
(no_op_insn): Declare.
|
|
|
|
|
|
|
|
|
|
|
|
2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
* crx.h (enum argtype): Rename types, remove unused types.
|
|
|
|
|
|
|
|
|
|
|
|
2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
|
|
|
|
|
|
(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
|
|
|
|
|
|
(enum operand_type): Rearrange operands, edit comments.
|
|
|
|
|
|
replace us<N> with ui<N> for unsigned immediate.
|
|
|
|
|
|
replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
|
|
|
|
|
|
displacements (respectively).
|
|
|
|
|
|
replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
|
|
|
|
|
|
(instruction type): Add NO_TYPE_INS.
|
|
|
|
|
|
(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
|
|
|
|
|
|
(operand_entry): New field - 'flags'.
|
|
|
|
|
|
(operand flags): New.
|
|
|
|
|
|
|
|
|
|
|
|
2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
* crx.h (operand_type): Remove redundant types i3, i4,
|
|
|
|
|
|
i5, i8, i12.
|
|
|
|
|
|
Add new unsigned immediate types us3, us4, us5, us16.
|
|
|
|
|
|
|
2005-04-13 01:12:30 +08:00
|
|
|
|
2005-04-12 Mark Kettenis <kettenis@gnu.org>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
|
|
|
|
|
|
adjust them accordingly.
|
|
|
|
|
|
|
2005-04-02 00:03:39 +08:00
|
|
|
|
2005-04-01 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Add rdtscp.
|
|
|
|
|
|
|
2005-03-30 03:30:46 +08:00
|
|
|
|
2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Don't allow the `l' suffix for moving
|
2005-04-05 00:06:26 +08:00
|
|
|
|
between memory and segment register. Allow movq for moving between
|
|
|
|
|
|
general-purpose register and segment register.
|
2005-03-30 03:30:46 +08:00
|
|
|
|
|
2005-02-09 16:05:43 +08:00
|
|
|
|
2005-02-09 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR gas/707
|
|
|
|
|
|
* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
|
|
|
|
|
|
FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
|
|
|
|
|
|
fnstsw.
|
|
|
|
|
|
|
2006-03-06 21:46:53 +08:00
|
|
|
|
2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k.h (m68008, m68ec030, m68882): Remove.
|
|
|
|
|
|
(m68k_mask): New.
|
|
|
|
|
|
(cpu_m68k, cpu_cf): New.
|
|
|
|
|
|
(mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
|
|
|
|
|
|
mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
|
|
|
|
|
|
|
2005-01-26 04:22:35 +08:00
|
|
|
|
2005-01-25 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
2004-11-10 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
* cgen.h (enum cgen_parse_operand_type): Add
|
|
|
|
|
|
CGEN_PARSE_OPERAND_SYMBOLIC.
|
|
|
|
|
|
|
2005-01-22 03:42:08 +08:00
|
|
|
|
2005-01-21 Fred Fish <fnf@specifixinc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
|
|
|
|
|
|
Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
|
|
|
|
|
|
Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
|
|
|
|
|
|
|
2005-01-20 07:29:12 +08:00
|
|
|
|
2005-01-19 Fred Fish <fnf@specifixinc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips.h (struct mips_opcode): Add new pinfo2 member.
|
|
|
|
|
|
(INSN_ALIAS): New define for opcode table entries that are
|
|
|
|
|
|
specific instances of another entry, such as 'move' for an 'or'
|
|
|
|
|
|
with a zero operand.
|
|
|
|
|
|
(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
|
|
|
|
|
|
(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
|
|
|
|
|
|
|
2004-12-09 14:13:44 +08:00
|
|
|
|
2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
|
|
|
|
|
|
|
|
|
|
|
|
* mips.h (CPU_RM9000): Define.
|
|
|
|
|
|
(OPCODE_IS_MEMBER): Handle CPU_RM9000.
|
|
|
|
|
|
|
2004-11-25 16:42:54 +08:00
|
|
|
|
2004-11-25 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
|
|
|
|
|
|
to/from test registers are illegal in 64-bit mode. Add missing
|
|
|
|
|
|
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
|
|
|
|
|
|
(previously one had to explicitly encode a rex64 prefix). Re-enable
|
|
|
|
|
|
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
|
|
|
|
|
|
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
|
|
|
|
|
|
|
|
|
|
|
|
2004-11-23 Jan Beulich <jbeulich@novell.com>
|
2004-11-23 15:55:12 +08:00
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
|
|
|
|
|
|
available only with SSE2. Change the MMX additions introduced by SSE
|
|
|
|
|
|
and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
|
|
|
|
|
|
instructions by their now designated identifier (since combining i686
|
|
|
|
|
|
and 3DNow! does not really imply 3DNow!A).
|
|
|
|
|
|
|
2004-11-19 20:28:01 +08:00
|
|
|
|
2004-11-19 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
|
|
|
|
|
|
struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
|
|
|
|
|
|
|
2004-11-08 21:17:39 +08:00
|
|
|
|
2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
|
|
|
|
|
|
Vineet Sharma <vineets@noida.hcltech.com>
|
|
|
|
|
|
|
|
|
|
|
|
* maxq.h: New file: Disassembly information for the maxq port.
|
|
|
|
|
|
|
2004-11-06 07:14:30 +08:00
|
|
|
|
2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Put back "movzb".
|
|
|
|
|
|
|
* cris.h (enum cris_insn_version_usage): Tweak formatting and
comments. Remove member cris_ver_sim. Add members
cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
(struct cris_support_reg, struct cris_cond15): New types.
(cris_conds15): Declare.
(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
(NOP_Z_BITS): Define in terms of NOP_OPCODE.
(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
SIZE_FIELD_UNSIGNED.
2004-11-04 22:53:41 +08:00
|
|
|
|
2004-11-04 Hans-Peter Nilsson <hp@axis.com>
|
|
|
|
|
|
|
|
|
|
|
|
* cris.h (enum cris_insn_version_usage): Tweak formatting and
|
|
|
|
|
|
comments. Remove member cris_ver_sim. Add members
|
|
|
|
|
|
cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
|
|
|
|
|
|
cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
|
|
|
|
|
|
(struct cris_support_reg, struct cris_cond15): New types.
|
|
|
|
|
|
(cris_conds15): Declare.
|
|
|
|
|
|
(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
|
|
|
|
|
|
(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
|
|
|
|
|
|
(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
|
|
|
|
|
|
(NOP_Z_BITS): Define in terms of NOP_OPCODE.
|
|
|
|
|
|
(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
|
|
|
|
|
|
SIZE_FIELD_UNSIGNED.
|
|
|
|
|
|
|
2004-11-25 16:42:54 +08:00
|
|
|
|
2004-11-04 Jan Beulich <jbeulich@novell.com>
|
gas/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
intel syntax and no register prefix, allow $ in symbol names when
intel syntax.
(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
(intel_float_operand): Add fourth return value indicating math control
operations. Make classification more precise.
(md_assemble): Complain if memory operand of mov[sz]x has no size
specified.
(parse_insn): Translate word operands to floating point instructions
operating on integers as well as control instructions to short ones
as expected by AT&T syntax. Translate 'd' suffix to short one only for
floating point instructions operating on non-integer operands.
(match_template): Remove fldcw special case. Adjust q-suffix handling
to permit it on fild/fistp/fisttp in AT&T mode.
(process_suffix): Don't guess DefaultSize insns' suffix from
stackop_size for certain floating point control instructions. Guess
suffix for branch and [ls][gi]dt based on flag_code. Split error
messages for Intel and AT&T syntax, and make the condition more strict
for the former. Adjust suppressing of generation of operand size
overrides.
(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
more error checking.
* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
gas/testsuite/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* gas/i386/i386.exp: Execute new tests intelbad and intelok.
* gas/i386/intelbad.[sl]: New test to check for various things not
permitted in Intel mode.
* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
Adjust for change to segment register store.
* gas/i386/intelok.[sd]: New test to check various Intel mode specific
things get handled correctly.
* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
'high' and 'low' parts of an operand, which the parser previously
accepted while neither telling that it's not supported nor that it
ignored the remainder of the line following these supposed keywords.
include/opcode/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386.h (sldx_Suf): Remove.
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
(q_FP): Define, implying no REX64.
(x_FP, sl_FP): Imply FloatMF.
(i386_optab): Split reg and mem forms of moving from segment registers
so that the memory forms can ignore the 16-/32-bit operand size
distinction. Adjust a few others for Intel mode. Remove *FP uses from
all non-floating-point instructions. Unite 32- and 64-bit forms of
movsx, movzx, and movd. Adjust floating point operations for the above
changes to the *FP macros. Add DefaultSize to floating point control
insns operating on larger memory ranges. Remove left over comments
hinting at certain insns being Intel-syntax ones where the ones
actually meant are already gone.
opcodes/
2004-11-04 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
(indirEb): Remove.
(Mp): Use f_mode rather than none at all.
(t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
replaces what previously was x_mode; x_mode now means 128-bit SSE
operands.
(dis386): Make far jumps and calls have an 'l' prefix only in AT&T
mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
pinsrw's second operand is Edqw.
(grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
mode when an operand size override is present or always suffixing.
More instructions will need to be added to this group.
(putop): Handle new macro chars 'C' (short/long suffix selector),
'I' (Intel mode override for following macro char), and 'J' (for
adding the 'l' prefix to far branches in AT&T mode). When an
alternative was specified in the template, honor macro character when
specified for Intel mode.
(OP_E): Handle new *_mode values. Correct pointer specifications for
memory operands. Consolidate output of index register.
(OP_G): Handle new *_mode values.
(OP_I): Handle const_1_mode.
(OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
respective opcode prefix bits have been consumed.
(OP_EM, OP_EX): Provide some default handling for generating pointer
specifications.
2004-11-04 17:16:08 +08:00
|
|
|
|
|
|
|
|
|
|
* i386.h (sldx_Suf): Remove.
|
|
|
|
|
|
(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
|
|
|
|
|
|
(q_FP): Define, implying no REX64.
|
|
|
|
|
|
(x_FP, sl_FP): Imply FloatMF.
|
|
|
|
|
|
(i386_optab): Split reg and mem forms of moving from segment registers
|
|
|
|
|
|
so that the memory forms can ignore the 16-/32-bit operand size
|
|
|
|
|
|
distinction. Adjust a few others for Intel mode. Remove *FP uses from
|
|
|
|
|
|
all non-floating-point instructions. Unite 32- and 64-bit forms of
|
|
|
|
|
|
movsx, movzx, and movd. Adjust floating point operations for the above
|
|
|
|
|
|
changes to the *FP macros. Add DefaultSize to floating point control
|
|
|
|
|
|
insns operating on larger memory ranges. Remove left over comments
|
|
|
|
|
|
hinting at certain insns being Intel-syntax ones where the ones
|
|
|
|
|
|
actually meant are already gone.
|
|
|
|
|
|
|
2004-10-07 22:18:17 +08:00
|
|
|
|
2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx.h: Add COPS_REG_INS - Coprocessor Special register
|
|
|
|
|
|
instruction type.
|
|
|
|
|
|
|
2004-10-01 00:21:43 +08:00
|
|
|
|
2004-09-30 Paul Brook <paul@codesourcery.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
|
|
|
|
|
|
(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
|
|
|
|
|
|
|
* gas/config/tc-avr.c: Add support for
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
* include/opcode/avr.h: Add support for
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2004-09-11 21:15:05 +08:00
|
|
|
|
2004-09-11 Theodore A. Roth <troth@openavr.org>
|
|
|
|
|
|
|
|
|
|
|
|
* avr.h: Add support for
|
|
|
|
|
|
atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
|
|
|
|
|
|
|
2004-09-09 20:42:37 +08:00
|
|
|
|
2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
|
|
|
|
|
|
|
|
|
|
|
|
* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
|
|
|
|
|
|
|
2004-08-25 20:54:15 +08:00
|
|
|
|
2004-08-24 Dmitry Diky <diwil@spec.ru>
|
|
|
|
|
|
|
|
|
|
|
|
* msp430.h (msp430_opc): Add new instructions.
|
|
|
|
|
|
(msp430_rcodes): Declare new instructions.
|
|
|
|
|
|
(msp430_hcodes): Likewise..
|
|
|
|
|
|
|
2004-08-13 16:14:02 +08:00
|
|
|
|
2004-08-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR/301
|
|
|
|
|
|
* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
|
|
|
|
|
|
processors.
|
|
|
|
|
|
|
2004-07-30 20:36:37 +08:00
|
|
|
|
2004-08-30 Michal Ludvig <mludvig@suse.cz>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
|
|
|
|
|
|
|
2004-07-23 03:10:49 +08:00
|
|
|
|
2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
|
|
|
|
|
|
|
2004-07-22 02:18:04 +08:00
|
|
|
|
2004-07-21 Jan Beulich <jbeulich@novell.com>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h: Adjust instruction descriptions to better match the
|
|
|
|
|
|
specification.
|
|
|
|
|
|
|
2004-07-17 05:59:35 +08:00
|
|
|
|
2004-07-16 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm.h: Remove all old content. Replace with architecture defines
|
|
|
|
|
|
from gas/config/tc-arm.c.
|
|
|
|
|
|
|
2004-07-10 02:42:14 +08:00
|
|
|
|
2004-07-09 Andreas Schwab <schwab@suse.de>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k.h: Fix comment.
|
|
|
|
|
|
|
2004-07-08 01:28:50 +08:00
|
|
|
|
2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
|
|
|
|
|
|
|
|
|
|
|
|
* crx.h: New file.
|
|
|
|
|
|
|
2004-06-23 23:06:53 +08:00
|
|
|
|
2004-06-24 Alan Modra <amodra@bigpond.net.au>
|
|
|
|
|
|
|
|
|
|
|
|
* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
|
|
|
|
|
|
|
2004-05-24 22:33:21 +08:00
|
|
|
|
2004-05-24 Peter Barada <peter@the-baradas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k.h: Add 'size' to m68k_opcode.
|
|
|
|
|
|
|
2004-05-05 22:33:14 +08:00
|
|
|
|
2004-05-05 Peter Barada <peter@the-baradas.com>
|
|
|
|
|
|
|
|
|
|
|
|
* m68k.h: Switch from ColdFire chip name to core variant.
|
|
|
|
|
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2004-04-22 Peter Barada <peter@the-baradas.com>
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2004-04-22 18:33:16 +08:00
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* m68k.h: Add mcfmac/mcfemac definitions. Update operand
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descriptions for new EMAC cases.
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Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
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handle Motorola MAC syntax.
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Allow disassembly of ColdFire V4e object files.
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opcodes/
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
2004-03-16 08:58:42 +08:00
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2004-03-16 Alan Modra <amodra@bigpond.net.au>
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* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
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2004-03-21 07:44:18 +08:00
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2004-03-12 Jakub Jelinek <jakub@redhat.com>
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* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
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2004-03-12 21:38:46 +08:00
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2004-03-12 Michal Ludvig <mludvig@suse.cz>
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* i386.h (i386_optab): Added xstore as an alias for xstorerng.
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2004-03-12 18:14:29 +08:00
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2004-03-12 Michal Ludvig <mludvig@suse.cz>
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* i386.h (i386_optab): Added xstore/xcrypt insns.
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2004-02-09 20:15:57 +08:00
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2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (32bit ldc/stc): Add relaxing support.
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2004-01-12 23:02:20 +08:00
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2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
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opcodes/
* ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
PPC_OPERANDS_GPR_0.
* ppc-opc.c (RA0): Define.
(RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
(RAOPT): Rename from RAO. Update all uses.
(powerpc_opcodes): Use RA0 as appropriate. Add "lsdx", "lsdi",
"stsdx", "stsdi", "lmd" and "stmd" insns.
include/opcode/
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
gas/testsuite/
Update gas/ppc/.
ld/testsuite/
Update ld-powerpc/.
2004-03-16 08:58:42 +08:00
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2004-01-12 23:02:20 +08:00
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* h8300.h (BITOP): Pass MEMRELAX flag.
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2004-01-10 01:47:17 +08:00
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2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
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except for the H8S.
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1999-05-03 15:29:06 +08:00
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2004-01-02 19:16:20 +08:00
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For older changes see ChangeLog-9103
|
1999-05-03 15:29:06 +08:00
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Local Variables:
|
2004-01-02 19:16:20 +08:00
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mode: change-log
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left-margin: 8
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fill-column: 74
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1999-05-03 15:29:06 +08:00
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version-control: never
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End:
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